1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 * written by Carsten Langgaard, carstenl@mips.com 12 */ 13#include <asm/asm.h> 14#include <asm/cachectl.h> 15#include <asm/fpregdef.h> 16#include <asm/mipsregs.h> 17#include <asm/asm-offsets.h> 18#include <asm/pgtable-bits.h> 19#include <asm/regdef.h> 20#include <asm/stackframe.h> 21#include <asm/thread_info.h> 22 23#include <asm/asmmacro.h> 24 25/* 26 * Offset to the current process status flags, the first 32 bytes of the 27 * stack are not used. 28 */ 29#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 30 31/* 32 * task_struct *resume(task_struct *prev, task_struct *next, 33 * struct thread_info *next_ti, int usedfpu) 34 */ 35 .align 7 36 LEAF(resume) 37 .set arch=octeon 38 mfc0 t1, CP0_STATUS 39 LONG_S t1, THREAD_STATUS(a0) 40 cpu_save_nonscratch a0 41 LONG_S ra, THREAD_REG31(a0) 42 43 /* check if we need to save COP2 registers */ 44 PTR_L t2, TASK_THREAD_INFO(a0) 45 LONG_L t0, ST_OFF(t2) 46 bbit0 t0, 30, 1f 47 48 /* Disable COP2 in the stored process state */ 49 li t1, ST0_CU2 50 xor t0, t1 51 LONG_S t0, ST_OFF(t2) 52 53 /* Enable COP2 so we can save it */ 54 mfc0 t0, CP0_STATUS 55 or t0, t1 56 mtc0 t0, CP0_STATUS 57 58 /* Save COP2 */ 59 daddu a0, THREAD_CP2 60 jal octeon_cop2_save 61 dsubu a0, THREAD_CP2 62 63 /* Disable COP2 now that we are done */ 64 mfc0 t0, CP0_STATUS 65 li t1, ST0_CU2 66 xor t0, t1 67 mtc0 t0, CP0_STATUS 68 691: 70#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 71 /* Check if we need to store CVMSEG state */ 72 mfc0 t0, $11,7 /* CvmMemCtl */ 73 bbit0 t0, 6, 3f /* Is user access enabled? */ 74 75 /* Store the CVMSEG state */ 76 /* Extract the size of CVMSEG */ 77 andi t0, 0x3f 78 /* Multiply * (cache line size/sizeof(long)/2) */ 79 sll t0, 7-LONGLOG-1 80 li t1, -32768 /* Base address of CVMSEG */ 81 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ 82 synciobdma 832: 84 .set noreorder 85 LONG_L t8, 0(t1) /* Load from CVMSEG */ 86 subu t0, 1 /* Decrement loop var */ 87 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ 88 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ 89 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ 90 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ 91 bnez t0, 2b /* Loop until we've copied it all */ 92 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ 93 .set reorder 94 95 /* Disable access to CVMSEG */ 96 mfc0 t0, $11,7 /* CvmMemCtl */ 97 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ 98 mtc0 t0, $11,7 /* CvmMemCtl */ 99#endif 1003: 101 /* 102 * The order of restoring the registers takes care of the race 103 * updating $28, $29 and kernelsp without disabling ints. 104 */ 105 move $28, a2 106 cpu_restore_nonscratch a1 107 108#if (_THREAD_SIZE - 32) < 0x8000 109 PTR_ADDIU t0, $28, _THREAD_SIZE - 32 110#else 111 PTR_LI t0, _THREAD_SIZE - 32 112 PTR_ADDU t0, $28 113#endif 114 set_saved_sp t0, t1, t2 115 116 mfc0 t1, CP0_STATUS /* Do we really need this? */ 117 li a3, 0xff01 118 and t1, a3 119 LONG_L a2, THREAD_STATUS(a1) 120 nor a3, $0, a3 121 and a2, a3 122 or a2, t1 123 mtc0 a2, CP0_STATUS 124 move v0, a0 125 jr ra 126 END(resume) 127 128/* 129 * void octeon_cop2_save(struct octeon_cop2_state *a0) 130 */ 131 .align 7 132 LEAF(octeon_cop2_save) 133 134 dmfc0 t9, $9,7 /* CvmCtl register. */ 135 136 /* Save the COP2 CRC state */ 137 dmfc2 t0, 0x0201 138 dmfc2 t1, 0x0202 139 dmfc2 t2, 0x0200 140 sd t0, OCTEON_CP2_CRC_IV(a0) 141 sd t1, OCTEON_CP2_CRC_LENGTH(a0) 142 sd t2, OCTEON_CP2_CRC_POLY(a0) 143 /* Skip next instructions if CvmCtl[NODFA_CP2] set */ 144 bbit1 t9, 28, 1f 145 146 /* Save the LLM state */ 147 dmfc2 t0, 0x0402 148 dmfc2 t1, 0x040A 149 sd t0, OCTEON_CP2_LLM_DAT(a0) 150 sd t1, OCTEON_CP2_LLM_DAT+8(a0) 151 1521: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ 153 154 /* Save the COP2 crypto state */ 155 /* this part is mostly common to both pass 1 and later revisions */ 156 dmfc2 t0, 0x0084 157 dmfc2 t1, 0x0080 158 dmfc2 t2, 0x0081 159 dmfc2 t3, 0x0082 160 sd t0, OCTEON_CP2_3DES_IV(a0) 161 dmfc2 t0, 0x0088 162 sd t1, OCTEON_CP2_3DES_KEY(a0) 163 dmfc2 t1, 0x0111 /* only necessary for pass 1 */ 164 sd t2, OCTEON_CP2_3DES_KEY+8(a0) 165 dmfc2 t2, 0x0102 166 sd t3, OCTEON_CP2_3DES_KEY+16(a0) 167 dmfc2 t3, 0x0103 168 sd t0, OCTEON_CP2_3DES_RESULT(a0) 169 dmfc2 t0, 0x0104 170 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ 171 dmfc2 t1, 0x0105 172 sd t2, OCTEON_CP2_AES_IV(a0) 173 dmfc2 t2, 0x0106 174 sd t3, OCTEON_CP2_AES_IV+8(a0) 175 dmfc2 t3, 0x0107 176 sd t0, OCTEON_CP2_AES_KEY(a0) 177 dmfc2 t0, 0x0110 178 sd t1, OCTEON_CP2_AES_KEY+8(a0) 179 dmfc2 t1, 0x0100 180 sd t2, OCTEON_CP2_AES_KEY+16(a0) 181 dmfc2 t2, 0x0101 182 sd t3, OCTEON_CP2_AES_KEY+24(a0) 183 mfc0 t3, $15,0 /* Get the processor ID register */ 184 sd t0, OCTEON_CP2_AES_KEYLEN(a0) 185 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 186 sd t1, OCTEON_CP2_AES_RESULT(a0) 187 sd t2, OCTEON_CP2_AES_RESULT+8(a0) 188 /* Skip to the Pass1 version of the remainder of the COP2 state */ 189 beq t3, t0, 2f 190 191 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ 192 dmfc2 t1, 0x0240 193 dmfc2 t2, 0x0241 194 dmfc2 t3, 0x0242 195 dmfc2 t0, 0x0243 196 sd t1, OCTEON_CP2_HSH_DATW(a0) 197 dmfc2 t1, 0x0244 198 sd t2, OCTEON_CP2_HSH_DATW+8(a0) 199 dmfc2 t2, 0x0245 200 sd t3, OCTEON_CP2_HSH_DATW+16(a0) 201 dmfc2 t3, 0x0246 202 sd t0, OCTEON_CP2_HSH_DATW+24(a0) 203 dmfc2 t0, 0x0247 204 sd t1, OCTEON_CP2_HSH_DATW+32(a0) 205 dmfc2 t1, 0x0248 206 sd t2, OCTEON_CP2_HSH_DATW+40(a0) 207 dmfc2 t2, 0x0249 208 sd t3, OCTEON_CP2_HSH_DATW+48(a0) 209 dmfc2 t3, 0x024A 210 sd t0, OCTEON_CP2_HSH_DATW+56(a0) 211 dmfc2 t0, 0x024B 212 sd t1, OCTEON_CP2_HSH_DATW+64(a0) 213 dmfc2 t1, 0x024C 214 sd t2, OCTEON_CP2_HSH_DATW+72(a0) 215 dmfc2 t2, 0x024D 216 sd t3, OCTEON_CP2_HSH_DATW+80(a0) 217 dmfc2 t3, 0x024E 218 sd t0, OCTEON_CP2_HSH_DATW+88(a0) 219 dmfc2 t0, 0x0250 220 sd t1, OCTEON_CP2_HSH_DATW+96(a0) 221 dmfc2 t1, 0x0251 222 sd t2, OCTEON_CP2_HSH_DATW+104(a0) 223 dmfc2 t2, 0x0252 224 sd t3, OCTEON_CP2_HSH_DATW+112(a0) 225 dmfc2 t3, 0x0253 226 sd t0, OCTEON_CP2_HSH_IVW(a0) 227 dmfc2 t0, 0x0254 228 sd t1, OCTEON_CP2_HSH_IVW+8(a0) 229 dmfc2 t1, 0x0255 230 sd t2, OCTEON_CP2_HSH_IVW+16(a0) 231 dmfc2 t2, 0x0256 232 sd t3, OCTEON_CP2_HSH_IVW+24(a0) 233 dmfc2 t3, 0x0257 234 sd t0, OCTEON_CP2_HSH_IVW+32(a0) 235 dmfc2 t0, 0x0258 236 sd t1, OCTEON_CP2_HSH_IVW+40(a0) 237 dmfc2 t1, 0x0259 238 sd t2, OCTEON_CP2_HSH_IVW+48(a0) 239 dmfc2 t2, 0x025E 240 sd t3, OCTEON_CP2_HSH_IVW+56(a0) 241 dmfc2 t3, 0x025A 242 sd t0, OCTEON_CP2_GFM_MULT(a0) 243 dmfc2 t0, 0x025B 244 sd t1, OCTEON_CP2_GFM_MULT+8(a0) 245 sd t2, OCTEON_CP2_GFM_POLY(a0) 246 sd t3, OCTEON_CP2_GFM_RESULT(a0) 247 sd t0, OCTEON_CP2_GFM_RESULT+8(a0) 248 jr ra 249 2502: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ 251 dmfc2 t3, 0x0040 252 dmfc2 t0, 0x0041 253 dmfc2 t1, 0x0042 254 dmfc2 t2, 0x0043 255 sd t3, OCTEON_CP2_HSH_DATW(a0) 256 dmfc2 t3, 0x0044 257 sd t0, OCTEON_CP2_HSH_DATW+8(a0) 258 dmfc2 t0, 0x0045 259 sd t1, OCTEON_CP2_HSH_DATW+16(a0) 260 dmfc2 t1, 0x0046 261 sd t2, OCTEON_CP2_HSH_DATW+24(a0) 262 dmfc2 t2, 0x0048 263 sd t3, OCTEON_CP2_HSH_DATW+32(a0) 264 dmfc2 t3, 0x0049 265 sd t0, OCTEON_CP2_HSH_DATW+40(a0) 266 dmfc2 t0, 0x004A 267 sd t1, OCTEON_CP2_HSH_DATW+48(a0) 268 sd t2, OCTEON_CP2_HSH_IVW(a0) 269 sd t3, OCTEON_CP2_HSH_IVW+8(a0) 270 sd t0, OCTEON_CP2_HSH_IVW+16(a0) 271 2723: /* pass 1 or CvmCtl[NOCRYPTO] set */ 273 jr ra 274 END(octeon_cop2_save) 275 276/* 277 * void octeon_cop2_restore(struct octeon_cop2_state *a0) 278 */ 279 .align 7 280 .set push 281 .set noreorder 282 LEAF(octeon_cop2_restore) 283 /* First cache line was prefetched before the call */ 284 pref 4, 128(a0) 285 dmfc0 t9, $9,7 /* CvmCtl register. */ 286 287 pref 4, 256(a0) 288 ld t0, OCTEON_CP2_CRC_IV(a0) 289 pref 4, 384(a0) 290 ld t1, OCTEON_CP2_CRC_LENGTH(a0) 291 ld t2, OCTEON_CP2_CRC_POLY(a0) 292 293 /* Restore the COP2 CRC state */ 294 dmtc2 t0, 0x0201 295 dmtc2 t1, 0x1202 296 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ 297 dmtc2 t2, 0x4200 298 299 /* Restore the LLM state */ 300 ld t0, OCTEON_CP2_LLM_DAT(a0) 301 ld t1, OCTEON_CP2_LLM_DAT+8(a0) 302 dmtc2 t0, 0x0402 303 dmtc2 t1, 0x040A 304 3052: 306 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */ 307 nop 308 309 /* Restore the COP2 crypto state common to pass 1 and pass 2 */ 310 ld t0, OCTEON_CP2_3DES_IV(a0) 311 ld t1, OCTEON_CP2_3DES_KEY(a0) 312 ld t2, OCTEON_CP2_3DES_KEY+8(a0) 313 dmtc2 t0, 0x0084 314 ld t0, OCTEON_CP2_3DES_KEY+16(a0) 315 dmtc2 t1, 0x0080 316 ld t1, OCTEON_CP2_3DES_RESULT(a0) 317 dmtc2 t2, 0x0081 318 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ 319 dmtc2 t0, 0x0082 320 ld t0, OCTEON_CP2_AES_IV(a0) 321 dmtc2 t1, 0x0098 322 ld t1, OCTEON_CP2_AES_IV+8(a0) 323 dmtc2 t2, 0x010A /* only really needed for pass 1 */ 324 ld t2, OCTEON_CP2_AES_KEY(a0) 325 dmtc2 t0, 0x0102 326 ld t0, OCTEON_CP2_AES_KEY+8(a0) 327 dmtc2 t1, 0x0103 328 ld t1, OCTEON_CP2_AES_KEY+16(a0) 329 dmtc2 t2, 0x0104 330 ld t2, OCTEON_CP2_AES_KEY+24(a0) 331 dmtc2 t0, 0x0105 332 ld t0, OCTEON_CP2_AES_KEYLEN(a0) 333 dmtc2 t1, 0x0106 334 ld t1, OCTEON_CP2_AES_RESULT(a0) 335 dmtc2 t2, 0x0107 336 ld t2, OCTEON_CP2_AES_RESULT+8(a0) 337 mfc0 t3, $15,0 /* Get the processor ID register */ 338 dmtc2 t0, 0x0110 339 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 340 dmtc2 t1, 0x0100 341 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ 342 dmtc2 t2, 0x0101 343 344 /* this code is specific for pass 1 */ 345 ld t0, OCTEON_CP2_HSH_DATW(a0) 346 ld t1, OCTEON_CP2_HSH_DATW+8(a0) 347 ld t2, OCTEON_CP2_HSH_DATW+16(a0) 348 dmtc2 t0, 0x0040 349 ld t0, OCTEON_CP2_HSH_DATW+24(a0) 350 dmtc2 t1, 0x0041 351 ld t1, OCTEON_CP2_HSH_DATW+32(a0) 352 dmtc2 t2, 0x0042 353 ld t2, OCTEON_CP2_HSH_DATW+40(a0) 354 dmtc2 t0, 0x0043 355 ld t0, OCTEON_CP2_HSH_DATW+48(a0) 356 dmtc2 t1, 0x0044 357 ld t1, OCTEON_CP2_HSH_IVW(a0) 358 dmtc2 t2, 0x0045 359 ld t2, OCTEON_CP2_HSH_IVW+8(a0) 360 dmtc2 t0, 0x0046 361 ld t0, OCTEON_CP2_HSH_IVW+16(a0) 362 dmtc2 t1, 0x0048 363 dmtc2 t2, 0x0049 364 b done_restore /* unconditional branch */ 365 dmtc2 t0, 0x004A 366 3673: /* this is post-pass1 code */ 368 ld t2, OCTEON_CP2_HSH_DATW(a0) 369 ld t0, OCTEON_CP2_HSH_DATW+8(a0) 370 ld t1, OCTEON_CP2_HSH_DATW+16(a0) 371 dmtc2 t2, 0x0240 372 ld t2, OCTEON_CP2_HSH_DATW+24(a0) 373 dmtc2 t0, 0x0241 374 ld t0, OCTEON_CP2_HSH_DATW+32(a0) 375 dmtc2 t1, 0x0242 376 ld t1, OCTEON_CP2_HSH_DATW+40(a0) 377 dmtc2 t2, 0x0243 378 ld t2, OCTEON_CP2_HSH_DATW+48(a0) 379 dmtc2 t0, 0x0244 380 ld t0, OCTEON_CP2_HSH_DATW+56(a0) 381 dmtc2 t1, 0x0245 382 ld t1, OCTEON_CP2_HSH_DATW+64(a0) 383 dmtc2 t2, 0x0246 384 ld t2, OCTEON_CP2_HSH_DATW+72(a0) 385 dmtc2 t0, 0x0247 386 ld t0, OCTEON_CP2_HSH_DATW+80(a0) 387 dmtc2 t1, 0x0248 388 ld t1, OCTEON_CP2_HSH_DATW+88(a0) 389 dmtc2 t2, 0x0249 390 ld t2, OCTEON_CP2_HSH_DATW+96(a0) 391 dmtc2 t0, 0x024A 392 ld t0, OCTEON_CP2_HSH_DATW+104(a0) 393 dmtc2 t1, 0x024B 394 ld t1, OCTEON_CP2_HSH_DATW+112(a0) 395 dmtc2 t2, 0x024C 396 ld t2, OCTEON_CP2_HSH_IVW(a0) 397 dmtc2 t0, 0x024D 398 ld t0, OCTEON_CP2_HSH_IVW+8(a0) 399 dmtc2 t1, 0x024E 400 ld t1, OCTEON_CP2_HSH_IVW+16(a0) 401 dmtc2 t2, 0x0250 402 ld t2, OCTEON_CP2_HSH_IVW+24(a0) 403 dmtc2 t0, 0x0251 404 ld t0, OCTEON_CP2_HSH_IVW+32(a0) 405 dmtc2 t1, 0x0252 406 ld t1, OCTEON_CP2_HSH_IVW+40(a0) 407 dmtc2 t2, 0x0253 408 ld t2, OCTEON_CP2_HSH_IVW+48(a0) 409 dmtc2 t0, 0x0254 410 ld t0, OCTEON_CP2_HSH_IVW+56(a0) 411 dmtc2 t1, 0x0255 412 ld t1, OCTEON_CP2_GFM_MULT(a0) 413 dmtc2 t2, 0x0256 414 ld t2, OCTEON_CP2_GFM_MULT+8(a0) 415 dmtc2 t0, 0x0257 416 ld t0, OCTEON_CP2_GFM_POLY(a0) 417 dmtc2 t1, 0x0258 418 ld t1, OCTEON_CP2_GFM_RESULT(a0) 419 dmtc2 t2, 0x0259 420 ld t2, OCTEON_CP2_GFM_RESULT+8(a0) 421 dmtc2 t0, 0x025E 422 dmtc2 t1, 0x025A 423 dmtc2 t2, 0x025B 424 425done_restore: 426 jr ra 427 nop 428 END(octeon_cop2_restore) 429 .set pop 430 431/* 432 * void octeon_mult_save() 433 * sp is assumed to point to a struct pt_regs 434 * 435 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only 436 * safely modify k0 and k1. 437 */ 438 .align 7 439 .set push 440 .set noreorder 441 LEAF(octeon_mult_save) 442 dmfc0 k0, $9,7 /* CvmCtl register. */ 443 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */ 444 nop 445 446 /* Save the multiplier state */ 447 v3mulu k0, $0, $0 448 v3mulu k1, $0, $0 449 sd k0, PT_MTP(sp) /* PT_MTP has P0 */ 450 v3mulu k0, $0, $0 451 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ 452 ori k1, $0, 1 453 v3mulu k1, k1, $0 454 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ 455 v3mulu k0, $0, $0 456 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ 457 v3mulu k1, $0, $0 458 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ 459 jr ra 460 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ 461 4621: /* Resume here if CvmCtl[NOMUL] */ 463 jr ra 464 END(octeon_mult_save) 465 .set pop 466 467/* 468 * void octeon_mult_restore() 469 * sp is assumed to point to a struct pt_regs 470 * 471 * NOTE: This is called in RESTORE_SOME in stackframe.h. 472 */ 473 .align 7 474 .set push 475 .set noreorder 476 LEAF(octeon_mult_restore) 477 dmfc0 k1, $9,7 /* CvmCtl register. */ 478 ld v0, PT_MPL(sp) /* MPL0 */ 479 ld v1, PT_MPL+8(sp) /* MPL1 */ 480 ld k0, PT_MPL+16(sp) /* MPL2 */ 481 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ 482 /* Normally falls through, so no time wasted here */ 483 nop 484 485 /* Restore the multiplier state */ 486 ld k1, PT_MTP+16(sp) /* P2 */ 487 MTM0 v0 /* MPL0 */ 488 ld v0, PT_MTP+8(sp) /* P1 */ 489 MTM1 v1 /* MPL1 */ 490 ld v1, PT_MTP(sp) /* P0 */ 491 MTM2 k0 /* MPL2 */ 492 MTP2 k1 /* P2 */ 493 MTP1 v0 /* P1 */ 494 jr ra 495 MTP0 v1 /* P0 */ 496 4971: /* Resume here if CvmCtl[NOMUL] */ 498 jr ra 499 nop 500 END(octeon_mult_restore) 501 .set pop 502