1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2014 Imagination Technologies Ltd. 7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> 8 * Author: Markos Chandras <markos.chandras@imgtec.com> 9 * 10 * MIPS R2 user space instruction emulator for MIPS R6 11 * 12 */ 13 #include <linux/bug.h> 14 #include <linux/compiler.h> 15 #include <linux/debugfs.h> 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/ptrace.h> 19 #include <linux/seq_file.h> 20 21 #include <asm/asm.h> 22 #include <asm/branch.h> 23 #include <asm/break.h> 24 #include <asm/debug.h> 25 #include <asm/fpu.h> 26 #include <asm/fpu_emulator.h> 27 #include <asm/inst.h> 28 #include <asm/mips-r2-to-r6-emul.h> 29 #include <asm/local.h> 30 #include <asm/mipsregs.h> 31 #include <asm/ptrace.h> 32 #include <linux/uaccess.h> 33 34 #ifdef CONFIG_64BIT 35 #define ADDIU "daddiu " 36 #define INS "dins " 37 #define EXT "dext " 38 #else 39 #define ADDIU "addiu " 40 #define INS "ins " 41 #define EXT "ext " 42 #endif /* CONFIG_64BIT */ 43 44 #define SB "sb " 45 #define LB "lb " 46 #define LL "ll " 47 #define SC "sc " 48 49 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats); 50 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats); 51 DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats); 52 53 extern const unsigned int fpucondbit[8]; 54 55 #define MIPS_R2_EMUL_TOTAL_PASS 10 56 57 int mipsr2_emulation = 0; 58 59 static int __init mipsr2emu_enable(char *s) 60 { 61 mipsr2_emulation = 1; 62 63 pr_info("MIPS R2-to-R6 Emulator Enabled!"); 64 65 return 1; 66 } 67 __setup("mipsr2emu", mipsr2emu_enable); 68 69 /** 70 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot 71 * for performance instead of the traditional way of using a stack trampoline 72 * which is rather slow. 73 * @regs: Process register set 74 * @ir: Instruction 75 */ 76 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) 77 { 78 switch (MIPSInst_OPCODE(ir)) { 79 case addiu_op: 80 if (MIPSInst_RT(ir)) 81 regs->regs[MIPSInst_RT(ir)] = 82 (s32)regs->regs[MIPSInst_RS(ir)] + 83 (s32)MIPSInst_SIMM(ir); 84 return 0; 85 case daddiu_op: 86 if (IS_ENABLED(CONFIG_32BIT)) 87 break; 88 89 if (MIPSInst_RT(ir)) 90 regs->regs[MIPSInst_RT(ir)] = 91 (s64)regs->regs[MIPSInst_RS(ir)] + 92 (s64)MIPSInst_SIMM(ir); 93 return 0; 94 case lwc1_op: 95 case swc1_op: 96 case cop1_op: 97 case cop1x_op: 98 /* FPU instructions in delay slot */ 99 return -SIGFPE; 100 case spec_op: 101 switch (MIPSInst_FUNC(ir)) { 102 case or_op: 103 if (MIPSInst_RD(ir)) 104 regs->regs[MIPSInst_RD(ir)] = 105 regs->regs[MIPSInst_RS(ir)] | 106 regs->regs[MIPSInst_RT(ir)]; 107 return 0; 108 case sll_op: 109 if (MIPSInst_RS(ir)) 110 break; 111 112 if (MIPSInst_RD(ir)) 113 regs->regs[MIPSInst_RD(ir)] = 114 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << 115 MIPSInst_FD(ir)); 116 return 0; 117 case srl_op: 118 if (MIPSInst_RS(ir)) 119 break; 120 121 if (MIPSInst_RD(ir)) 122 regs->regs[MIPSInst_RD(ir)] = 123 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> 124 MIPSInst_FD(ir)); 125 return 0; 126 case addu_op: 127 if (MIPSInst_FD(ir)) 128 break; 129 130 if (MIPSInst_RD(ir)) 131 regs->regs[MIPSInst_RD(ir)] = 132 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + 133 (u32)regs->regs[MIPSInst_RT(ir)]); 134 return 0; 135 case subu_op: 136 if (MIPSInst_FD(ir)) 137 break; 138 139 if (MIPSInst_RD(ir)) 140 regs->regs[MIPSInst_RD(ir)] = 141 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - 142 (u32)regs->regs[MIPSInst_RT(ir)]); 143 return 0; 144 case dsll_op: 145 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir)) 146 break; 147 148 if (MIPSInst_RD(ir)) 149 regs->regs[MIPSInst_RD(ir)] = 150 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << 151 MIPSInst_FD(ir)); 152 return 0; 153 case dsrl_op: 154 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir)) 155 break; 156 157 if (MIPSInst_RD(ir)) 158 regs->regs[MIPSInst_RD(ir)] = 159 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> 160 MIPSInst_FD(ir)); 161 return 0; 162 case daddu_op: 163 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir)) 164 break; 165 166 if (MIPSInst_RD(ir)) 167 regs->regs[MIPSInst_RD(ir)] = 168 (u64)regs->regs[MIPSInst_RS(ir)] + 169 (u64)regs->regs[MIPSInst_RT(ir)]; 170 return 0; 171 case dsubu_op: 172 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir)) 173 break; 174 175 if (MIPSInst_RD(ir)) 176 regs->regs[MIPSInst_RD(ir)] = 177 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - 178 (u64)regs->regs[MIPSInst_RT(ir)]); 179 return 0; 180 } 181 break; 182 default: 183 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n", 184 ir, MIPSInst_OPCODE(ir)); 185 } 186 187 return SIGILL; 188 } 189 190 /** 191 * movf_func - Emulate a MOVF instruction 192 * @regs: Process register set 193 * @ir: Instruction 194 * 195 * Returns 0 since it always succeeds. 196 */ 197 static int movf_func(struct pt_regs *regs, u32 ir) 198 { 199 u32 csr; 200 u32 cond; 201 202 csr = current->thread.fpu.fcr31; 203 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 204 205 if (((csr & cond) == 0) && MIPSInst_RD(ir)) 206 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 207 208 MIPS_R2_STATS(movs); 209 210 return 0; 211 } 212 213 /** 214 * movt_func - Emulate a MOVT instruction 215 * @regs: Process register set 216 * @ir: Instruction 217 * 218 * Returns 0 since it always succeeds. 219 */ 220 static int movt_func(struct pt_regs *regs, u32 ir) 221 { 222 u32 csr; 223 u32 cond; 224 225 csr = current->thread.fpu.fcr31; 226 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 227 228 if (((csr & cond) != 0) && MIPSInst_RD(ir)) 229 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 230 231 MIPS_R2_STATS(movs); 232 233 return 0; 234 } 235 236 /** 237 * jr_func - Emulate a JR instruction. 238 * @pt_regs: Process register set 239 * @ir: Instruction 240 * 241 * Returns SIGILL if JR was in delay slot, SIGEMT if we 242 * can't compute the EPC, SIGSEGV if we can't access the 243 * userland instruction or 0 on success. 244 */ 245 static int jr_func(struct pt_regs *regs, u32 ir) 246 { 247 int err; 248 unsigned long cepc, epc, nepc; 249 u32 nir; 250 251 if (delay_slot(regs)) 252 return SIGILL; 253 254 /* EPC after the RI/JR instruction */ 255 nepc = regs->cp0_epc; 256 /* Roll back to the reserved R2 JR instruction */ 257 regs->cp0_epc -= 4; 258 epc = regs->cp0_epc; 259 err = __compute_return_epc(regs); 260 261 if (err < 0) 262 return SIGEMT; 263 264 265 /* Computed EPC */ 266 cepc = regs->cp0_epc; 267 268 /* Get DS instruction */ 269 err = __get_user(nir, (u32 __user *)nepc); 270 if (err) 271 return SIGSEGV; 272 273 MIPS_R2BR_STATS(jrs); 274 275 /* If nir == 0(NOP), then nothing else to do */ 276 if (nir) { 277 /* 278 * Negative err means FPU instruction in BD-slot, 279 * Zero err means 'BD-slot emulation done' 280 * For anything else we go back to trampoline emulation. 281 */ 282 err = mipsr6_emul(regs, nir); 283 if (err > 0) { 284 regs->cp0_epc = nepc; 285 err = mips_dsemul(regs, nir, epc, cepc); 286 if (err == SIGILL) 287 err = SIGEMT; 288 MIPS_R2_STATS(dsemul); 289 } 290 } 291 292 return err; 293 } 294 295 /** 296 * movz_func - Emulate a MOVZ instruction 297 * @regs: Process register set 298 * @ir: Instruction 299 * 300 * Returns 0 since it always succeeds. 301 */ 302 static int movz_func(struct pt_regs *regs, u32 ir) 303 { 304 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) 305 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 306 MIPS_R2_STATS(movs); 307 308 return 0; 309 } 310 311 /** 312 * movn_func - Emulate a MOVZ instruction 313 * @regs: Process register set 314 * @ir: Instruction 315 * 316 * Returns 0 since it always succeeds. 317 */ 318 static int movn_func(struct pt_regs *regs, u32 ir) 319 { 320 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) 321 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 322 MIPS_R2_STATS(movs); 323 324 return 0; 325 } 326 327 /** 328 * mfhi_func - Emulate a MFHI instruction 329 * @regs: Process register set 330 * @ir: Instruction 331 * 332 * Returns 0 since it always succeeds. 333 */ 334 static int mfhi_func(struct pt_regs *regs, u32 ir) 335 { 336 if (MIPSInst_RD(ir)) 337 regs->regs[MIPSInst_RD(ir)] = regs->hi; 338 339 MIPS_R2_STATS(hilo); 340 341 return 0; 342 } 343 344 /** 345 * mthi_func - Emulate a MTHI instruction 346 * @regs: Process register set 347 * @ir: Instruction 348 * 349 * Returns 0 since it always succeeds. 350 */ 351 static int mthi_func(struct pt_regs *regs, u32 ir) 352 { 353 regs->hi = regs->regs[MIPSInst_RS(ir)]; 354 355 MIPS_R2_STATS(hilo); 356 357 return 0; 358 } 359 360 /** 361 * mflo_func - Emulate a MFLO instruction 362 * @regs: Process register set 363 * @ir: Instruction 364 * 365 * Returns 0 since it always succeeds. 366 */ 367 static int mflo_func(struct pt_regs *regs, u32 ir) 368 { 369 if (MIPSInst_RD(ir)) 370 regs->regs[MIPSInst_RD(ir)] = regs->lo; 371 372 MIPS_R2_STATS(hilo); 373 374 return 0; 375 } 376 377 /** 378 * mtlo_func - Emulate a MTLO instruction 379 * @regs: Process register set 380 * @ir: Instruction 381 * 382 * Returns 0 since it always succeeds. 383 */ 384 static int mtlo_func(struct pt_regs *regs, u32 ir) 385 { 386 regs->lo = regs->regs[MIPSInst_RS(ir)]; 387 388 MIPS_R2_STATS(hilo); 389 390 return 0; 391 } 392 393 /** 394 * mult_func - Emulate a MULT instruction 395 * @regs: Process register set 396 * @ir: Instruction 397 * 398 * Returns 0 since it always succeeds. 399 */ 400 static int mult_func(struct pt_regs *regs, u32 ir) 401 { 402 s64 res; 403 s32 rt, rs; 404 405 rt = regs->regs[MIPSInst_RT(ir)]; 406 rs = regs->regs[MIPSInst_RS(ir)]; 407 res = (s64)rt * (s64)rs; 408 409 rs = res; 410 regs->lo = (s64)rs; 411 rt = res >> 32; 412 res = (s64)rt; 413 regs->hi = res; 414 415 MIPS_R2_STATS(muls); 416 417 return 0; 418 } 419 420 /** 421 * multu_func - Emulate a MULTU instruction 422 * @regs: Process register set 423 * @ir: Instruction 424 * 425 * Returns 0 since it always succeeds. 426 */ 427 static int multu_func(struct pt_regs *regs, u32 ir) 428 { 429 u64 res; 430 u32 rt, rs; 431 432 rt = regs->regs[MIPSInst_RT(ir)]; 433 rs = regs->regs[MIPSInst_RS(ir)]; 434 res = (u64)rt * (u64)rs; 435 rt = res; 436 regs->lo = (s64)(s32)rt; 437 regs->hi = (s64)(s32)(res >> 32); 438 439 MIPS_R2_STATS(muls); 440 441 return 0; 442 } 443 444 /** 445 * div_func - Emulate a DIV instruction 446 * @regs: Process register set 447 * @ir: Instruction 448 * 449 * Returns 0 since it always succeeds. 450 */ 451 static int div_func(struct pt_regs *regs, u32 ir) 452 { 453 s32 rt, rs; 454 455 rt = regs->regs[MIPSInst_RT(ir)]; 456 rs = regs->regs[MIPSInst_RS(ir)]; 457 458 regs->lo = (s64)(rs / rt); 459 regs->hi = (s64)(rs % rt); 460 461 MIPS_R2_STATS(divs); 462 463 return 0; 464 } 465 466 /** 467 * divu_func - Emulate a DIVU instruction 468 * @regs: Process register set 469 * @ir: Instruction 470 * 471 * Returns 0 since it always succeeds. 472 */ 473 static int divu_func(struct pt_regs *regs, u32 ir) 474 { 475 u32 rt, rs; 476 477 rt = regs->regs[MIPSInst_RT(ir)]; 478 rs = regs->regs[MIPSInst_RS(ir)]; 479 480 regs->lo = (s64)(rs / rt); 481 regs->hi = (s64)(rs % rt); 482 483 MIPS_R2_STATS(divs); 484 485 return 0; 486 } 487 488 /** 489 * dmult_func - Emulate a DMULT instruction 490 * @regs: Process register set 491 * @ir: Instruction 492 * 493 * Returns 0 on success or SIGILL for 32-bit kernels. 494 */ 495 static int dmult_func(struct pt_regs *regs, u32 ir) 496 { 497 s64 res; 498 s64 rt, rs; 499 500 if (IS_ENABLED(CONFIG_32BIT)) 501 return SIGILL; 502 503 rt = regs->regs[MIPSInst_RT(ir)]; 504 rs = regs->regs[MIPSInst_RS(ir)]; 505 res = rt * rs; 506 507 regs->lo = res; 508 __asm__ __volatile__( 509 "dmuh %0, %1, %2\t\n" 510 : "=r"(res) 511 : "r"(rt), "r"(rs)); 512 513 regs->hi = res; 514 515 MIPS_R2_STATS(muls); 516 517 return 0; 518 } 519 520 /** 521 * dmultu_func - Emulate a DMULTU instruction 522 * @regs: Process register set 523 * @ir: Instruction 524 * 525 * Returns 0 on success or SIGILL for 32-bit kernels. 526 */ 527 static int dmultu_func(struct pt_regs *regs, u32 ir) 528 { 529 u64 res; 530 u64 rt, rs; 531 532 if (IS_ENABLED(CONFIG_32BIT)) 533 return SIGILL; 534 535 rt = regs->regs[MIPSInst_RT(ir)]; 536 rs = regs->regs[MIPSInst_RS(ir)]; 537 res = rt * rs; 538 539 regs->lo = res; 540 __asm__ __volatile__( 541 "dmuhu %0, %1, %2\t\n" 542 : "=r"(res) 543 : "r"(rt), "r"(rs)); 544 545 regs->hi = res; 546 547 MIPS_R2_STATS(muls); 548 549 return 0; 550 } 551 552 /** 553 * ddiv_func - Emulate a DDIV instruction 554 * @regs: Process register set 555 * @ir: Instruction 556 * 557 * Returns 0 on success or SIGILL for 32-bit kernels. 558 */ 559 static int ddiv_func(struct pt_regs *regs, u32 ir) 560 { 561 s64 rt, rs; 562 563 if (IS_ENABLED(CONFIG_32BIT)) 564 return SIGILL; 565 566 rt = regs->regs[MIPSInst_RT(ir)]; 567 rs = regs->regs[MIPSInst_RS(ir)]; 568 569 regs->lo = rs / rt; 570 regs->hi = rs % rt; 571 572 MIPS_R2_STATS(divs); 573 574 return 0; 575 } 576 577 /** 578 * ddivu_func - Emulate a DDIVU instruction 579 * @regs: Process register set 580 * @ir: Instruction 581 * 582 * Returns 0 on success or SIGILL for 32-bit kernels. 583 */ 584 static int ddivu_func(struct pt_regs *regs, u32 ir) 585 { 586 u64 rt, rs; 587 588 if (IS_ENABLED(CONFIG_32BIT)) 589 return SIGILL; 590 591 rt = regs->regs[MIPSInst_RT(ir)]; 592 rs = regs->regs[MIPSInst_RS(ir)]; 593 594 regs->lo = rs / rt; 595 regs->hi = rs % rt; 596 597 MIPS_R2_STATS(divs); 598 599 return 0; 600 } 601 602 /* R6 removed instructions for the SPECIAL opcode */ 603 static struct r2_decoder_table spec_op_table[] = { 604 { 0xfc1ff83f, 0x00000008, jr_func }, 605 { 0xfc00ffff, 0x00000018, mult_func }, 606 { 0xfc00ffff, 0x00000019, multu_func }, 607 { 0xfc00ffff, 0x0000001c, dmult_func }, 608 { 0xfc00ffff, 0x0000001d, dmultu_func }, 609 { 0xffff07ff, 0x00000010, mfhi_func }, 610 { 0xfc1fffff, 0x00000011, mthi_func }, 611 { 0xffff07ff, 0x00000012, mflo_func }, 612 { 0xfc1fffff, 0x00000013, mtlo_func }, 613 { 0xfc0307ff, 0x00000001, movf_func }, 614 { 0xfc0307ff, 0x00010001, movt_func }, 615 { 0xfc0007ff, 0x0000000a, movz_func }, 616 { 0xfc0007ff, 0x0000000b, movn_func }, 617 { 0xfc00ffff, 0x0000001a, div_func }, 618 { 0xfc00ffff, 0x0000001b, divu_func }, 619 { 0xfc00ffff, 0x0000001e, ddiv_func }, 620 { 0xfc00ffff, 0x0000001f, ddivu_func }, 621 {} 622 }; 623 624 /** 625 * madd_func - Emulate a MADD instruction 626 * @regs: Process register set 627 * @ir: Instruction 628 * 629 * Returns 0 since it always succeeds. 630 */ 631 static int madd_func(struct pt_regs *regs, u32 ir) 632 { 633 s64 res; 634 s32 rt, rs; 635 636 rt = regs->regs[MIPSInst_RT(ir)]; 637 rs = regs->regs[MIPSInst_RS(ir)]; 638 res = (s64)rt * (s64)rs; 639 rt = regs->hi; 640 rs = regs->lo; 641 res += ((((s64)rt) << 32) | (u32)rs); 642 643 rt = res; 644 regs->lo = (s64)rt; 645 rs = res >> 32; 646 regs->hi = (s64)rs; 647 648 MIPS_R2_STATS(dsps); 649 650 return 0; 651 } 652 653 /** 654 * maddu_func - Emulate a MADDU instruction 655 * @regs: Process register set 656 * @ir: Instruction 657 * 658 * Returns 0 since it always succeeds. 659 */ 660 static int maddu_func(struct pt_regs *regs, u32 ir) 661 { 662 u64 res; 663 u32 rt, rs; 664 665 rt = regs->regs[MIPSInst_RT(ir)]; 666 rs = regs->regs[MIPSInst_RS(ir)]; 667 res = (u64)rt * (u64)rs; 668 rt = regs->hi; 669 rs = regs->lo; 670 res += ((((s64)rt) << 32) | (u32)rs); 671 672 rt = res; 673 regs->lo = (s64)(s32)rt; 674 rs = res >> 32; 675 regs->hi = (s64)(s32)rs; 676 677 MIPS_R2_STATS(dsps); 678 679 return 0; 680 } 681 682 /** 683 * msub_func - Emulate a MSUB instruction 684 * @regs: Process register set 685 * @ir: Instruction 686 * 687 * Returns 0 since it always succeeds. 688 */ 689 static int msub_func(struct pt_regs *regs, u32 ir) 690 { 691 s64 res; 692 s32 rt, rs; 693 694 rt = regs->regs[MIPSInst_RT(ir)]; 695 rs = regs->regs[MIPSInst_RS(ir)]; 696 res = (s64)rt * (s64)rs; 697 rt = regs->hi; 698 rs = regs->lo; 699 res = ((((s64)rt) << 32) | (u32)rs) - res; 700 701 rt = res; 702 regs->lo = (s64)rt; 703 rs = res >> 32; 704 regs->hi = (s64)rs; 705 706 MIPS_R2_STATS(dsps); 707 708 return 0; 709 } 710 711 /** 712 * msubu_func - Emulate a MSUBU instruction 713 * @regs: Process register set 714 * @ir: Instruction 715 * 716 * Returns 0 since it always succeeds. 717 */ 718 static int msubu_func(struct pt_regs *regs, u32 ir) 719 { 720 u64 res; 721 u32 rt, rs; 722 723 rt = regs->regs[MIPSInst_RT(ir)]; 724 rs = regs->regs[MIPSInst_RS(ir)]; 725 res = (u64)rt * (u64)rs; 726 rt = regs->hi; 727 rs = regs->lo; 728 res = ((((s64)rt) << 32) | (u32)rs) - res; 729 730 rt = res; 731 regs->lo = (s64)(s32)rt; 732 rs = res >> 32; 733 regs->hi = (s64)(s32)rs; 734 735 MIPS_R2_STATS(dsps); 736 737 return 0; 738 } 739 740 /** 741 * mul_func - Emulate a MUL instruction 742 * @regs: Process register set 743 * @ir: Instruction 744 * 745 * Returns 0 since it always succeeds. 746 */ 747 static int mul_func(struct pt_regs *regs, u32 ir) 748 { 749 s64 res; 750 s32 rt, rs; 751 752 if (!MIPSInst_RD(ir)) 753 return 0; 754 rt = regs->regs[MIPSInst_RT(ir)]; 755 rs = regs->regs[MIPSInst_RS(ir)]; 756 res = (s64)rt * (s64)rs; 757 758 rs = res; 759 regs->regs[MIPSInst_RD(ir)] = (s64)rs; 760 761 MIPS_R2_STATS(muls); 762 763 return 0; 764 } 765 766 /** 767 * clz_func - Emulate a CLZ instruction 768 * @regs: Process register set 769 * @ir: Instruction 770 * 771 * Returns 0 since it always succeeds. 772 */ 773 static int clz_func(struct pt_regs *regs, u32 ir) 774 { 775 u32 res; 776 u32 rs; 777 778 if (!MIPSInst_RD(ir)) 779 return 0; 780 781 rs = regs->regs[MIPSInst_RS(ir)]; 782 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); 783 regs->regs[MIPSInst_RD(ir)] = res; 784 785 MIPS_R2_STATS(bops); 786 787 return 0; 788 } 789 790 /** 791 * clo_func - Emulate a CLO instruction 792 * @regs: Process register set 793 * @ir: Instruction 794 * 795 * Returns 0 since it always succeeds. 796 */ 797 798 static int clo_func(struct pt_regs *regs, u32 ir) 799 { 800 u32 res; 801 u32 rs; 802 803 if (!MIPSInst_RD(ir)) 804 return 0; 805 806 rs = regs->regs[MIPSInst_RS(ir)]; 807 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); 808 regs->regs[MIPSInst_RD(ir)] = res; 809 810 MIPS_R2_STATS(bops); 811 812 return 0; 813 } 814 815 /** 816 * dclz_func - Emulate a DCLZ instruction 817 * @regs: Process register set 818 * @ir: Instruction 819 * 820 * Returns 0 since it always succeeds. 821 */ 822 static int dclz_func(struct pt_regs *regs, u32 ir) 823 { 824 u64 res; 825 u64 rs; 826 827 if (IS_ENABLED(CONFIG_32BIT)) 828 return SIGILL; 829 830 if (!MIPSInst_RD(ir)) 831 return 0; 832 833 rs = regs->regs[MIPSInst_RS(ir)]; 834 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); 835 regs->regs[MIPSInst_RD(ir)] = res; 836 837 MIPS_R2_STATS(bops); 838 839 return 0; 840 } 841 842 /** 843 * dclo_func - Emulate a DCLO instruction 844 * @regs: Process register set 845 * @ir: Instruction 846 * 847 * Returns 0 since it always succeeds. 848 */ 849 static int dclo_func(struct pt_regs *regs, u32 ir) 850 { 851 u64 res; 852 u64 rs; 853 854 if (IS_ENABLED(CONFIG_32BIT)) 855 return SIGILL; 856 857 if (!MIPSInst_RD(ir)) 858 return 0; 859 860 rs = regs->regs[MIPSInst_RS(ir)]; 861 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); 862 regs->regs[MIPSInst_RD(ir)] = res; 863 864 MIPS_R2_STATS(bops); 865 866 return 0; 867 } 868 869 /* R6 removed instructions for the SPECIAL2 opcode */ 870 static struct r2_decoder_table spec2_op_table[] = { 871 { 0xfc00ffff, 0x70000000, madd_func }, 872 { 0xfc00ffff, 0x70000001, maddu_func }, 873 { 0xfc0007ff, 0x70000002, mul_func }, 874 { 0xfc00ffff, 0x70000004, msub_func }, 875 { 0xfc00ffff, 0x70000005, msubu_func }, 876 { 0xfc0007ff, 0x70000020, clz_func }, 877 { 0xfc0007ff, 0x70000021, clo_func }, 878 { 0xfc0007ff, 0x70000024, dclz_func }, 879 { 0xfc0007ff, 0x70000025, dclo_func }, 880 { } 881 }; 882 883 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst, 884 struct r2_decoder_table *table) 885 { 886 struct r2_decoder_table *p; 887 int err; 888 889 for (p = table; p->func; p++) { 890 if ((inst & p->mask) == p->code) { 891 err = (p->func)(regs, inst); 892 return err; 893 } 894 } 895 return SIGILL; 896 } 897 898 /** 899 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction 900 * @regs: Process register set 901 * @inst: Instruction to decode and emulate 902 * @fcr31: Floating Point Control and Status Register Cause bits returned 903 */ 904 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) 905 { 906 int err = 0; 907 unsigned long vaddr; 908 u32 nir; 909 unsigned long cpc, epc, nepc, r31, res, rs, rt; 910 911 void __user *fault_addr = NULL; 912 int pass = 0; 913 914 repeat: 915 r31 = regs->regs[31]; 916 epc = regs->cp0_epc; 917 err = compute_return_epc(regs); 918 if (err < 0) { 919 BUG(); 920 return SIGEMT; 921 } 922 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", 923 inst, epc, pass); 924 925 switch (MIPSInst_OPCODE(inst)) { 926 case spec_op: 927 err = mipsr2_find_op_func(regs, inst, spec_op_table); 928 if (err < 0) { 929 /* FPU instruction under JR */ 930 regs->cp0_cause |= CAUSEF_BD; 931 goto fpu_emul; 932 } 933 break; 934 case spec2_op: 935 err = mipsr2_find_op_func(regs, inst, spec2_op_table); 936 break; 937 case bcond_op: 938 rt = MIPSInst_RT(inst); 939 rs = MIPSInst_RS(inst); 940 switch (rt) { 941 case tgei_op: 942 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) 943 do_trap_or_bp(regs, 0, 0, "TGEI"); 944 945 MIPS_R2_STATS(traps); 946 947 break; 948 case tgeiu_op: 949 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) 950 do_trap_or_bp(regs, 0, 0, "TGEIU"); 951 952 MIPS_R2_STATS(traps); 953 954 break; 955 case tlti_op: 956 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) 957 do_trap_or_bp(regs, 0, 0, "TLTI"); 958 959 MIPS_R2_STATS(traps); 960 961 break; 962 case tltiu_op: 963 if (regs->regs[rs] < MIPSInst_UIMM(inst)) 964 do_trap_or_bp(regs, 0, 0, "TLTIU"); 965 966 MIPS_R2_STATS(traps); 967 968 break; 969 case teqi_op: 970 if (regs->regs[rs] == MIPSInst_SIMM(inst)) 971 do_trap_or_bp(regs, 0, 0, "TEQI"); 972 973 MIPS_R2_STATS(traps); 974 975 break; 976 case tnei_op: 977 if (regs->regs[rs] != MIPSInst_SIMM(inst)) 978 do_trap_or_bp(regs, 0, 0, "TNEI"); 979 980 MIPS_R2_STATS(traps); 981 982 break; 983 case bltzl_op: 984 case bgezl_op: 985 case bltzall_op: 986 case bgezall_op: 987 if (delay_slot(regs)) { 988 err = SIGILL; 989 break; 990 } 991 regs->regs[31] = r31; 992 regs->cp0_epc = epc; 993 err = __compute_return_epc(regs); 994 if (err < 0) 995 return SIGEMT; 996 if (err != BRANCH_LIKELY_TAKEN) 997 break; 998 cpc = regs->cp0_epc; 999 nepc = epc + 4; 1000 err = __get_user(nir, (u32 __user *)nepc); 1001 if (err) { 1002 err = SIGSEGV; 1003 break; 1004 } 1005 /* 1006 * This will probably be optimized away when 1007 * CONFIG_DEBUG_FS is not enabled 1008 */ 1009 switch (rt) { 1010 case bltzl_op: 1011 MIPS_R2BR_STATS(bltzl); 1012 break; 1013 case bgezl_op: 1014 MIPS_R2BR_STATS(bgezl); 1015 break; 1016 case bltzall_op: 1017 MIPS_R2BR_STATS(bltzall); 1018 break; 1019 case bgezall_op: 1020 MIPS_R2BR_STATS(bgezall); 1021 break; 1022 } 1023 1024 switch (MIPSInst_OPCODE(nir)) { 1025 case cop1_op: 1026 case cop1x_op: 1027 case lwc1_op: 1028 case swc1_op: 1029 regs->cp0_cause |= CAUSEF_BD; 1030 goto fpu_emul; 1031 } 1032 if (nir) { 1033 err = mipsr6_emul(regs, nir); 1034 if (err > 0) { 1035 err = mips_dsemul(regs, nir, epc, cpc); 1036 if (err == SIGILL) 1037 err = SIGEMT; 1038 MIPS_R2_STATS(dsemul); 1039 } 1040 } 1041 break; 1042 case bltzal_op: 1043 case bgezal_op: 1044 if (delay_slot(regs)) { 1045 err = SIGILL; 1046 break; 1047 } 1048 regs->regs[31] = r31; 1049 regs->cp0_epc = epc; 1050 err = __compute_return_epc(regs); 1051 if (err < 0) 1052 return SIGEMT; 1053 cpc = regs->cp0_epc; 1054 nepc = epc + 4; 1055 err = __get_user(nir, (u32 __user *)nepc); 1056 if (err) { 1057 err = SIGSEGV; 1058 break; 1059 } 1060 /* 1061 * This will probably be optimized away when 1062 * CONFIG_DEBUG_FS is not enabled 1063 */ 1064 switch (rt) { 1065 case bltzal_op: 1066 MIPS_R2BR_STATS(bltzal); 1067 break; 1068 case bgezal_op: 1069 MIPS_R2BR_STATS(bgezal); 1070 break; 1071 } 1072 1073 switch (MIPSInst_OPCODE(nir)) { 1074 case cop1_op: 1075 case cop1x_op: 1076 case lwc1_op: 1077 case swc1_op: 1078 regs->cp0_cause |= CAUSEF_BD; 1079 goto fpu_emul; 1080 } 1081 if (nir) { 1082 err = mipsr6_emul(regs, nir); 1083 if (err > 0) { 1084 err = mips_dsemul(regs, nir, epc, cpc); 1085 if (err == SIGILL) 1086 err = SIGEMT; 1087 MIPS_R2_STATS(dsemul); 1088 } 1089 } 1090 break; 1091 default: 1092 regs->regs[31] = r31; 1093 regs->cp0_epc = epc; 1094 err = SIGILL; 1095 break; 1096 } 1097 break; 1098 1099 case blezl_op: 1100 case bgtzl_op: 1101 /* 1102 * For BLEZL and BGTZL, rt field must be set to 0. If this 1103 * is not the case, this may be an encoding of a MIPS R6 1104 * instruction, so return to CPU execution if this occurs 1105 */ 1106 if (MIPSInst_RT(inst)) { 1107 err = SIGILL; 1108 break; 1109 } 1110 /* fall through */ 1111 case beql_op: 1112 case bnel_op: 1113 if (delay_slot(regs)) { 1114 err = SIGILL; 1115 break; 1116 } 1117 regs->regs[31] = r31; 1118 regs->cp0_epc = epc; 1119 err = __compute_return_epc(regs); 1120 if (err < 0) 1121 return SIGEMT; 1122 if (err != BRANCH_LIKELY_TAKEN) 1123 break; 1124 cpc = regs->cp0_epc; 1125 nepc = epc + 4; 1126 err = __get_user(nir, (u32 __user *)nepc); 1127 if (err) { 1128 err = SIGSEGV; 1129 break; 1130 } 1131 /* 1132 * This will probably be optimized away when 1133 * CONFIG_DEBUG_FS is not enabled 1134 */ 1135 switch (MIPSInst_OPCODE(inst)) { 1136 case beql_op: 1137 MIPS_R2BR_STATS(beql); 1138 break; 1139 case bnel_op: 1140 MIPS_R2BR_STATS(bnel); 1141 break; 1142 case blezl_op: 1143 MIPS_R2BR_STATS(blezl); 1144 break; 1145 case bgtzl_op: 1146 MIPS_R2BR_STATS(bgtzl); 1147 break; 1148 } 1149 1150 switch (MIPSInst_OPCODE(nir)) { 1151 case cop1_op: 1152 case cop1x_op: 1153 case lwc1_op: 1154 case swc1_op: 1155 regs->cp0_cause |= CAUSEF_BD; 1156 goto fpu_emul; 1157 } 1158 if (nir) { 1159 err = mipsr6_emul(regs, nir); 1160 if (err > 0) { 1161 err = mips_dsemul(regs, nir, epc, cpc); 1162 if (err == SIGILL) 1163 err = SIGEMT; 1164 MIPS_R2_STATS(dsemul); 1165 } 1166 } 1167 break; 1168 case lwc1_op: 1169 case swc1_op: 1170 case cop1_op: 1171 case cop1x_op: 1172 fpu_emul: 1173 regs->regs[31] = r31; 1174 regs->cp0_epc = epc; 1175 if (!used_math()) { /* First time FPU user. */ 1176 preempt_disable(); 1177 err = init_fpu(); 1178 preempt_enable(); 1179 set_used_math(); 1180 } 1181 lose_fpu(1); /* Save FPU state for the emulator. */ 1182 1183 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1184 &fault_addr); 1185 1186 /* 1187 * We can't allow the emulated instruction to leave any 1188 * enabled Cause bits set in $fcr31. 1189 */ 1190 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31); 1191 current->thread.fpu.fcr31 &= ~res; 1192 1193 /* 1194 * this is a tricky issue - lose_fpu() uses LL/SC atomics 1195 * if FPU is owned and effectively cancels user level LL/SC. 1196 * So, it could be logical to don't restore FPU ownership here. 1197 * But the sequence of multiple FPU instructions is much much 1198 * more often than LL-FPU-SC and I prefer loop here until 1199 * next scheduler cycle cancels FPU ownership 1200 */ 1201 own_fpu(1); /* Restore FPU state. */ 1202 1203 if (err) 1204 current->thread.cp0_baduaddr = (unsigned long)fault_addr; 1205 1206 MIPS_R2_STATS(fpus); 1207 1208 break; 1209 1210 case lwl_op: 1211 rt = regs->regs[MIPSInst_RT(inst)]; 1212 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1213 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) { 1214 current->thread.cp0_baduaddr = vaddr; 1215 err = SIGSEGV; 1216 break; 1217 } 1218 __asm__ __volatile__( 1219 " .set push\n" 1220 " .set reorder\n" 1221 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1222 "1:" LB "%1, 0(%2)\n" 1223 INS "%0, %1, 24, 8\n" 1224 " andi %1, %2, 0x3\n" 1225 " beq $0, %1, 9f\n" 1226 ADDIU "%2, %2, -1\n" 1227 "2:" LB "%1, 0(%2)\n" 1228 INS "%0, %1, 16, 8\n" 1229 " andi %1, %2, 0x3\n" 1230 " beq $0, %1, 9f\n" 1231 ADDIU "%2, %2, -1\n" 1232 "3:" LB "%1, 0(%2)\n" 1233 INS "%0, %1, 8, 8\n" 1234 " andi %1, %2, 0x3\n" 1235 " beq $0, %1, 9f\n" 1236 ADDIU "%2, %2, -1\n" 1237 "4:" LB "%1, 0(%2)\n" 1238 INS "%0, %1, 0, 8\n" 1239 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1240 "1:" LB "%1, 0(%2)\n" 1241 INS "%0, %1, 24, 8\n" 1242 ADDIU "%2, %2, 1\n" 1243 " andi %1, %2, 0x3\n" 1244 " beq $0, %1, 9f\n" 1245 "2:" LB "%1, 0(%2)\n" 1246 INS "%0, %1, 16, 8\n" 1247 ADDIU "%2, %2, 1\n" 1248 " andi %1, %2, 0x3\n" 1249 " beq $0, %1, 9f\n" 1250 "3:" LB "%1, 0(%2)\n" 1251 INS "%0, %1, 8, 8\n" 1252 ADDIU "%2, %2, 1\n" 1253 " andi %1, %2, 0x3\n" 1254 " beq $0, %1, 9f\n" 1255 "4:" LB "%1, 0(%2)\n" 1256 INS "%0, %1, 0, 8\n" 1257 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1258 "9: sll %0, %0, 0\n" 1259 "10:\n" 1260 " .insn\n" 1261 " .section .fixup,\"ax\"\n" 1262 "8: li %3,%4\n" 1263 " j 10b\n" 1264 " .previous\n" 1265 " .section __ex_table,\"a\"\n" 1266 STR(PTR) " 1b,8b\n" 1267 STR(PTR) " 2b,8b\n" 1268 STR(PTR) " 3b,8b\n" 1269 STR(PTR) " 4b,8b\n" 1270 " .previous\n" 1271 " .set pop\n" 1272 : "+&r"(rt), "=&r"(rs), 1273 "+&r"(vaddr), "+&r"(err) 1274 : "i"(SIGSEGV)); 1275 1276 if (MIPSInst_RT(inst) && !err) 1277 regs->regs[MIPSInst_RT(inst)] = rt; 1278 1279 MIPS_R2_STATS(loads); 1280 1281 break; 1282 1283 case lwr_op: 1284 rt = regs->regs[MIPSInst_RT(inst)]; 1285 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1286 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) { 1287 current->thread.cp0_baduaddr = vaddr; 1288 err = SIGSEGV; 1289 break; 1290 } 1291 __asm__ __volatile__( 1292 " .set push\n" 1293 " .set reorder\n" 1294 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1295 "1:" LB "%1, 0(%2)\n" 1296 INS "%0, %1, 0, 8\n" 1297 ADDIU "%2, %2, 1\n" 1298 " andi %1, %2, 0x3\n" 1299 " beq $0, %1, 9f\n" 1300 "2:" LB "%1, 0(%2)\n" 1301 INS "%0, %1, 8, 8\n" 1302 ADDIU "%2, %2, 1\n" 1303 " andi %1, %2, 0x3\n" 1304 " beq $0, %1, 9f\n" 1305 "3:" LB "%1, 0(%2)\n" 1306 INS "%0, %1, 16, 8\n" 1307 ADDIU "%2, %2, 1\n" 1308 " andi %1, %2, 0x3\n" 1309 " beq $0, %1, 9f\n" 1310 "4:" LB "%1, 0(%2)\n" 1311 INS "%0, %1, 24, 8\n" 1312 " sll %0, %0, 0\n" 1313 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1314 "1:" LB "%1, 0(%2)\n" 1315 INS "%0, %1, 0, 8\n" 1316 " andi %1, %2, 0x3\n" 1317 " beq $0, %1, 9f\n" 1318 ADDIU "%2, %2, -1\n" 1319 "2:" LB "%1, 0(%2)\n" 1320 INS "%0, %1, 8, 8\n" 1321 " andi %1, %2, 0x3\n" 1322 " beq $0, %1, 9f\n" 1323 ADDIU "%2, %2, -1\n" 1324 "3:" LB "%1, 0(%2)\n" 1325 INS "%0, %1, 16, 8\n" 1326 " andi %1, %2, 0x3\n" 1327 " beq $0, %1, 9f\n" 1328 ADDIU "%2, %2, -1\n" 1329 "4:" LB "%1, 0(%2)\n" 1330 INS "%0, %1, 24, 8\n" 1331 " sll %0, %0, 0\n" 1332 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1333 "9:\n" 1334 "10:\n" 1335 " .insn\n" 1336 " .section .fixup,\"ax\"\n" 1337 "8: li %3,%4\n" 1338 " j 10b\n" 1339 " .previous\n" 1340 " .section __ex_table,\"a\"\n" 1341 STR(PTR) " 1b,8b\n" 1342 STR(PTR) " 2b,8b\n" 1343 STR(PTR) " 3b,8b\n" 1344 STR(PTR) " 4b,8b\n" 1345 " .previous\n" 1346 " .set pop\n" 1347 : "+&r"(rt), "=&r"(rs), 1348 "+&r"(vaddr), "+&r"(err) 1349 : "i"(SIGSEGV)); 1350 if (MIPSInst_RT(inst) && !err) 1351 regs->regs[MIPSInst_RT(inst)] = rt; 1352 1353 MIPS_R2_STATS(loads); 1354 1355 break; 1356 1357 case swl_op: 1358 rt = regs->regs[MIPSInst_RT(inst)]; 1359 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1360 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) { 1361 current->thread.cp0_baduaddr = vaddr; 1362 err = SIGSEGV; 1363 break; 1364 } 1365 __asm__ __volatile__( 1366 " .set push\n" 1367 " .set reorder\n" 1368 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1369 EXT "%1, %0, 24, 8\n" 1370 "1:" SB "%1, 0(%2)\n" 1371 " andi %1, %2, 0x3\n" 1372 " beq $0, %1, 9f\n" 1373 ADDIU "%2, %2, -1\n" 1374 EXT "%1, %0, 16, 8\n" 1375 "2:" SB "%1, 0(%2)\n" 1376 " andi %1, %2, 0x3\n" 1377 " beq $0, %1, 9f\n" 1378 ADDIU "%2, %2, -1\n" 1379 EXT "%1, %0, 8, 8\n" 1380 "3:" SB "%1, 0(%2)\n" 1381 " andi %1, %2, 0x3\n" 1382 " beq $0, %1, 9f\n" 1383 ADDIU "%2, %2, -1\n" 1384 EXT "%1, %0, 0, 8\n" 1385 "4:" SB "%1, 0(%2)\n" 1386 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1387 EXT "%1, %0, 24, 8\n" 1388 "1:" SB "%1, 0(%2)\n" 1389 ADDIU "%2, %2, 1\n" 1390 " andi %1, %2, 0x3\n" 1391 " beq $0, %1, 9f\n" 1392 EXT "%1, %0, 16, 8\n" 1393 "2:" SB "%1, 0(%2)\n" 1394 ADDIU "%2, %2, 1\n" 1395 " andi %1, %2, 0x3\n" 1396 " beq $0, %1, 9f\n" 1397 EXT "%1, %0, 8, 8\n" 1398 "3:" SB "%1, 0(%2)\n" 1399 ADDIU "%2, %2, 1\n" 1400 " andi %1, %2, 0x3\n" 1401 " beq $0, %1, 9f\n" 1402 EXT "%1, %0, 0, 8\n" 1403 "4:" SB "%1, 0(%2)\n" 1404 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1405 "9:\n" 1406 " .insn\n" 1407 " .section .fixup,\"ax\"\n" 1408 "8: li %3,%4\n" 1409 " j 9b\n" 1410 " .previous\n" 1411 " .section __ex_table,\"a\"\n" 1412 STR(PTR) " 1b,8b\n" 1413 STR(PTR) " 2b,8b\n" 1414 STR(PTR) " 3b,8b\n" 1415 STR(PTR) " 4b,8b\n" 1416 " .previous\n" 1417 " .set pop\n" 1418 : "+&r"(rt), "=&r"(rs), 1419 "+&r"(vaddr), "+&r"(err) 1420 : "i"(SIGSEGV) 1421 : "memory"); 1422 1423 MIPS_R2_STATS(stores); 1424 1425 break; 1426 1427 case swr_op: 1428 rt = regs->regs[MIPSInst_RT(inst)]; 1429 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1430 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) { 1431 current->thread.cp0_baduaddr = vaddr; 1432 err = SIGSEGV; 1433 break; 1434 } 1435 __asm__ __volatile__( 1436 " .set push\n" 1437 " .set reorder\n" 1438 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1439 EXT "%1, %0, 0, 8\n" 1440 "1:" SB "%1, 0(%2)\n" 1441 ADDIU "%2, %2, 1\n" 1442 " andi %1, %2, 0x3\n" 1443 " beq $0, %1, 9f\n" 1444 EXT "%1, %0, 8, 8\n" 1445 "2:" SB "%1, 0(%2)\n" 1446 ADDIU "%2, %2, 1\n" 1447 " andi %1, %2, 0x3\n" 1448 " beq $0, %1, 9f\n" 1449 EXT "%1, %0, 16, 8\n" 1450 "3:" SB "%1, 0(%2)\n" 1451 ADDIU "%2, %2, 1\n" 1452 " andi %1, %2, 0x3\n" 1453 " beq $0, %1, 9f\n" 1454 EXT "%1, %0, 24, 8\n" 1455 "4:" SB "%1, 0(%2)\n" 1456 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1457 EXT "%1, %0, 0, 8\n" 1458 "1:" SB "%1, 0(%2)\n" 1459 " andi %1, %2, 0x3\n" 1460 " beq $0, %1, 9f\n" 1461 ADDIU "%2, %2, -1\n" 1462 EXT "%1, %0, 8, 8\n" 1463 "2:" SB "%1, 0(%2)\n" 1464 " andi %1, %2, 0x3\n" 1465 " beq $0, %1, 9f\n" 1466 ADDIU "%2, %2, -1\n" 1467 EXT "%1, %0, 16, 8\n" 1468 "3:" SB "%1, 0(%2)\n" 1469 " andi %1, %2, 0x3\n" 1470 " beq $0, %1, 9f\n" 1471 ADDIU "%2, %2, -1\n" 1472 EXT "%1, %0, 24, 8\n" 1473 "4:" SB "%1, 0(%2)\n" 1474 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1475 "9:\n" 1476 " .insn\n" 1477 " .section .fixup,\"ax\"\n" 1478 "8: li %3,%4\n" 1479 " j 9b\n" 1480 " .previous\n" 1481 " .section __ex_table,\"a\"\n" 1482 STR(PTR) " 1b,8b\n" 1483 STR(PTR) " 2b,8b\n" 1484 STR(PTR) " 3b,8b\n" 1485 STR(PTR) " 4b,8b\n" 1486 " .previous\n" 1487 " .set pop\n" 1488 : "+&r"(rt), "=&r"(rs), 1489 "+&r"(vaddr), "+&r"(err) 1490 : "i"(SIGSEGV) 1491 : "memory"); 1492 1493 MIPS_R2_STATS(stores); 1494 1495 break; 1496 1497 case ldl_op: 1498 if (IS_ENABLED(CONFIG_32BIT)) { 1499 err = SIGILL; 1500 break; 1501 } 1502 1503 rt = regs->regs[MIPSInst_RT(inst)]; 1504 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1505 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) { 1506 current->thread.cp0_baduaddr = vaddr; 1507 err = SIGSEGV; 1508 break; 1509 } 1510 __asm__ __volatile__( 1511 " .set push\n" 1512 " .set reorder\n" 1513 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1514 "1: lb %1, 0(%2)\n" 1515 " dinsu %0, %1, 56, 8\n" 1516 " andi %1, %2, 0x7\n" 1517 " beq $0, %1, 9f\n" 1518 " daddiu %2, %2, -1\n" 1519 "2: lb %1, 0(%2)\n" 1520 " dinsu %0, %1, 48, 8\n" 1521 " andi %1, %2, 0x7\n" 1522 " beq $0, %1, 9f\n" 1523 " daddiu %2, %2, -1\n" 1524 "3: lb %1, 0(%2)\n" 1525 " dinsu %0, %1, 40, 8\n" 1526 " andi %1, %2, 0x7\n" 1527 " beq $0, %1, 9f\n" 1528 " daddiu %2, %2, -1\n" 1529 "4: lb %1, 0(%2)\n" 1530 " dinsu %0, %1, 32, 8\n" 1531 " andi %1, %2, 0x7\n" 1532 " beq $0, %1, 9f\n" 1533 " daddiu %2, %2, -1\n" 1534 "5: lb %1, 0(%2)\n" 1535 " dins %0, %1, 24, 8\n" 1536 " andi %1, %2, 0x7\n" 1537 " beq $0, %1, 9f\n" 1538 " daddiu %2, %2, -1\n" 1539 "6: lb %1, 0(%2)\n" 1540 " dins %0, %1, 16, 8\n" 1541 " andi %1, %2, 0x7\n" 1542 " beq $0, %1, 9f\n" 1543 " daddiu %2, %2, -1\n" 1544 "7: lb %1, 0(%2)\n" 1545 " dins %0, %1, 8, 8\n" 1546 " andi %1, %2, 0x7\n" 1547 " beq $0, %1, 9f\n" 1548 " daddiu %2, %2, -1\n" 1549 "0: lb %1, 0(%2)\n" 1550 " dins %0, %1, 0, 8\n" 1551 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1552 "1: lb %1, 0(%2)\n" 1553 " dinsu %0, %1, 56, 8\n" 1554 " daddiu %2, %2, 1\n" 1555 " andi %1, %2, 0x7\n" 1556 " beq $0, %1, 9f\n" 1557 "2: lb %1, 0(%2)\n" 1558 " dinsu %0, %1, 48, 8\n" 1559 " daddiu %2, %2, 1\n" 1560 " andi %1, %2, 0x7\n" 1561 " beq $0, %1, 9f\n" 1562 "3: lb %1, 0(%2)\n" 1563 " dinsu %0, %1, 40, 8\n" 1564 " daddiu %2, %2, 1\n" 1565 " andi %1, %2, 0x7\n" 1566 " beq $0, %1, 9f\n" 1567 "4: lb %1, 0(%2)\n" 1568 " dinsu %0, %1, 32, 8\n" 1569 " daddiu %2, %2, 1\n" 1570 " andi %1, %2, 0x7\n" 1571 " beq $0, %1, 9f\n" 1572 "5: lb %1, 0(%2)\n" 1573 " dins %0, %1, 24, 8\n" 1574 " daddiu %2, %2, 1\n" 1575 " andi %1, %2, 0x7\n" 1576 " beq $0, %1, 9f\n" 1577 "6: lb %1, 0(%2)\n" 1578 " dins %0, %1, 16, 8\n" 1579 " daddiu %2, %2, 1\n" 1580 " andi %1, %2, 0x7\n" 1581 " beq $0, %1, 9f\n" 1582 "7: lb %1, 0(%2)\n" 1583 " dins %0, %1, 8, 8\n" 1584 " daddiu %2, %2, 1\n" 1585 " andi %1, %2, 0x7\n" 1586 " beq $0, %1, 9f\n" 1587 "0: lb %1, 0(%2)\n" 1588 " dins %0, %1, 0, 8\n" 1589 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1590 "9:\n" 1591 " .insn\n" 1592 " .section .fixup,\"ax\"\n" 1593 "8: li %3,%4\n" 1594 " j 9b\n" 1595 " .previous\n" 1596 " .section __ex_table,\"a\"\n" 1597 STR(PTR) " 1b,8b\n" 1598 STR(PTR) " 2b,8b\n" 1599 STR(PTR) " 3b,8b\n" 1600 STR(PTR) " 4b,8b\n" 1601 STR(PTR) " 5b,8b\n" 1602 STR(PTR) " 6b,8b\n" 1603 STR(PTR) " 7b,8b\n" 1604 STR(PTR) " 0b,8b\n" 1605 " .previous\n" 1606 " .set pop\n" 1607 : "+&r"(rt), "=&r"(rs), 1608 "+&r"(vaddr), "+&r"(err) 1609 : "i"(SIGSEGV)); 1610 if (MIPSInst_RT(inst) && !err) 1611 regs->regs[MIPSInst_RT(inst)] = rt; 1612 1613 MIPS_R2_STATS(loads); 1614 break; 1615 1616 case ldr_op: 1617 if (IS_ENABLED(CONFIG_32BIT)) { 1618 err = SIGILL; 1619 break; 1620 } 1621 1622 rt = regs->regs[MIPSInst_RT(inst)]; 1623 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1624 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) { 1625 current->thread.cp0_baduaddr = vaddr; 1626 err = SIGSEGV; 1627 break; 1628 } 1629 __asm__ __volatile__( 1630 " .set push\n" 1631 " .set reorder\n" 1632 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1633 "1: lb %1, 0(%2)\n" 1634 " dins %0, %1, 0, 8\n" 1635 " daddiu %2, %2, 1\n" 1636 " andi %1, %2, 0x7\n" 1637 " beq $0, %1, 9f\n" 1638 "2: lb %1, 0(%2)\n" 1639 " dins %0, %1, 8, 8\n" 1640 " daddiu %2, %2, 1\n" 1641 " andi %1, %2, 0x7\n" 1642 " beq $0, %1, 9f\n" 1643 "3: lb %1, 0(%2)\n" 1644 " dins %0, %1, 16, 8\n" 1645 " daddiu %2, %2, 1\n" 1646 " andi %1, %2, 0x7\n" 1647 " beq $0, %1, 9f\n" 1648 "4: lb %1, 0(%2)\n" 1649 " dins %0, %1, 24, 8\n" 1650 " daddiu %2, %2, 1\n" 1651 " andi %1, %2, 0x7\n" 1652 " beq $0, %1, 9f\n" 1653 "5: lb %1, 0(%2)\n" 1654 " dinsu %0, %1, 32, 8\n" 1655 " daddiu %2, %2, 1\n" 1656 " andi %1, %2, 0x7\n" 1657 " beq $0, %1, 9f\n" 1658 "6: lb %1, 0(%2)\n" 1659 " dinsu %0, %1, 40, 8\n" 1660 " daddiu %2, %2, 1\n" 1661 " andi %1, %2, 0x7\n" 1662 " beq $0, %1, 9f\n" 1663 "7: lb %1, 0(%2)\n" 1664 " dinsu %0, %1, 48, 8\n" 1665 " daddiu %2, %2, 1\n" 1666 " andi %1, %2, 0x7\n" 1667 " beq $0, %1, 9f\n" 1668 "0: lb %1, 0(%2)\n" 1669 " dinsu %0, %1, 56, 8\n" 1670 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1671 "1: lb %1, 0(%2)\n" 1672 " dins %0, %1, 0, 8\n" 1673 " andi %1, %2, 0x7\n" 1674 " beq $0, %1, 9f\n" 1675 " daddiu %2, %2, -1\n" 1676 "2: lb %1, 0(%2)\n" 1677 " dins %0, %1, 8, 8\n" 1678 " andi %1, %2, 0x7\n" 1679 " beq $0, %1, 9f\n" 1680 " daddiu %2, %2, -1\n" 1681 "3: lb %1, 0(%2)\n" 1682 " dins %0, %1, 16, 8\n" 1683 " andi %1, %2, 0x7\n" 1684 " beq $0, %1, 9f\n" 1685 " daddiu %2, %2, -1\n" 1686 "4: lb %1, 0(%2)\n" 1687 " dins %0, %1, 24, 8\n" 1688 " andi %1, %2, 0x7\n" 1689 " beq $0, %1, 9f\n" 1690 " daddiu %2, %2, -1\n" 1691 "5: lb %1, 0(%2)\n" 1692 " dinsu %0, %1, 32, 8\n" 1693 " andi %1, %2, 0x7\n" 1694 " beq $0, %1, 9f\n" 1695 " daddiu %2, %2, -1\n" 1696 "6: lb %1, 0(%2)\n" 1697 " dinsu %0, %1, 40, 8\n" 1698 " andi %1, %2, 0x7\n" 1699 " beq $0, %1, 9f\n" 1700 " daddiu %2, %2, -1\n" 1701 "7: lb %1, 0(%2)\n" 1702 " dinsu %0, %1, 48, 8\n" 1703 " andi %1, %2, 0x7\n" 1704 " beq $0, %1, 9f\n" 1705 " daddiu %2, %2, -1\n" 1706 "0: lb %1, 0(%2)\n" 1707 " dinsu %0, %1, 56, 8\n" 1708 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1709 "9:\n" 1710 " .insn\n" 1711 " .section .fixup,\"ax\"\n" 1712 "8: li %3,%4\n" 1713 " j 9b\n" 1714 " .previous\n" 1715 " .section __ex_table,\"a\"\n" 1716 STR(PTR) " 1b,8b\n" 1717 STR(PTR) " 2b,8b\n" 1718 STR(PTR) " 3b,8b\n" 1719 STR(PTR) " 4b,8b\n" 1720 STR(PTR) " 5b,8b\n" 1721 STR(PTR) " 6b,8b\n" 1722 STR(PTR) " 7b,8b\n" 1723 STR(PTR) " 0b,8b\n" 1724 " .previous\n" 1725 " .set pop\n" 1726 : "+&r"(rt), "=&r"(rs), 1727 "+&r"(vaddr), "+&r"(err) 1728 : "i"(SIGSEGV)); 1729 if (MIPSInst_RT(inst) && !err) 1730 regs->regs[MIPSInst_RT(inst)] = rt; 1731 1732 MIPS_R2_STATS(loads); 1733 break; 1734 1735 case sdl_op: 1736 if (IS_ENABLED(CONFIG_32BIT)) { 1737 err = SIGILL; 1738 break; 1739 } 1740 1741 rt = regs->regs[MIPSInst_RT(inst)]; 1742 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1743 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) { 1744 current->thread.cp0_baduaddr = vaddr; 1745 err = SIGSEGV; 1746 break; 1747 } 1748 __asm__ __volatile__( 1749 " .set push\n" 1750 " .set reorder\n" 1751 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1752 " dextu %1, %0, 56, 8\n" 1753 "1: sb %1, 0(%2)\n" 1754 " andi %1, %2, 0x7\n" 1755 " beq $0, %1, 9f\n" 1756 " daddiu %2, %2, -1\n" 1757 " dextu %1, %0, 48, 8\n" 1758 "2: sb %1, 0(%2)\n" 1759 " andi %1, %2, 0x7\n" 1760 " beq $0, %1, 9f\n" 1761 " daddiu %2, %2, -1\n" 1762 " dextu %1, %0, 40, 8\n" 1763 "3: sb %1, 0(%2)\n" 1764 " andi %1, %2, 0x7\n" 1765 " beq $0, %1, 9f\n" 1766 " daddiu %2, %2, -1\n" 1767 " dextu %1, %0, 32, 8\n" 1768 "4: sb %1, 0(%2)\n" 1769 " andi %1, %2, 0x7\n" 1770 " beq $0, %1, 9f\n" 1771 " daddiu %2, %2, -1\n" 1772 " dext %1, %0, 24, 8\n" 1773 "5: sb %1, 0(%2)\n" 1774 " andi %1, %2, 0x7\n" 1775 " beq $0, %1, 9f\n" 1776 " daddiu %2, %2, -1\n" 1777 " dext %1, %0, 16, 8\n" 1778 "6: sb %1, 0(%2)\n" 1779 " andi %1, %2, 0x7\n" 1780 " beq $0, %1, 9f\n" 1781 " daddiu %2, %2, -1\n" 1782 " dext %1, %0, 8, 8\n" 1783 "7: sb %1, 0(%2)\n" 1784 " andi %1, %2, 0x7\n" 1785 " beq $0, %1, 9f\n" 1786 " daddiu %2, %2, -1\n" 1787 " dext %1, %0, 0, 8\n" 1788 "0: sb %1, 0(%2)\n" 1789 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1790 " dextu %1, %0, 56, 8\n" 1791 "1: sb %1, 0(%2)\n" 1792 " daddiu %2, %2, 1\n" 1793 " andi %1, %2, 0x7\n" 1794 " beq $0, %1, 9f\n" 1795 " dextu %1, %0, 48, 8\n" 1796 "2: sb %1, 0(%2)\n" 1797 " daddiu %2, %2, 1\n" 1798 " andi %1, %2, 0x7\n" 1799 " beq $0, %1, 9f\n" 1800 " dextu %1, %0, 40, 8\n" 1801 "3: sb %1, 0(%2)\n" 1802 " daddiu %2, %2, 1\n" 1803 " andi %1, %2, 0x7\n" 1804 " beq $0, %1, 9f\n" 1805 " dextu %1, %0, 32, 8\n" 1806 "4: sb %1, 0(%2)\n" 1807 " daddiu %2, %2, 1\n" 1808 " andi %1, %2, 0x7\n" 1809 " beq $0, %1, 9f\n" 1810 " dext %1, %0, 24, 8\n" 1811 "5: sb %1, 0(%2)\n" 1812 " daddiu %2, %2, 1\n" 1813 " andi %1, %2, 0x7\n" 1814 " beq $0, %1, 9f\n" 1815 " dext %1, %0, 16, 8\n" 1816 "6: sb %1, 0(%2)\n" 1817 " daddiu %2, %2, 1\n" 1818 " andi %1, %2, 0x7\n" 1819 " beq $0, %1, 9f\n" 1820 " dext %1, %0, 8, 8\n" 1821 "7: sb %1, 0(%2)\n" 1822 " daddiu %2, %2, 1\n" 1823 " andi %1, %2, 0x7\n" 1824 " beq $0, %1, 9f\n" 1825 " dext %1, %0, 0, 8\n" 1826 "0: sb %1, 0(%2)\n" 1827 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1828 "9:\n" 1829 " .insn\n" 1830 " .section .fixup,\"ax\"\n" 1831 "8: li %3,%4\n" 1832 " j 9b\n" 1833 " .previous\n" 1834 " .section __ex_table,\"a\"\n" 1835 STR(PTR) " 1b,8b\n" 1836 STR(PTR) " 2b,8b\n" 1837 STR(PTR) " 3b,8b\n" 1838 STR(PTR) " 4b,8b\n" 1839 STR(PTR) " 5b,8b\n" 1840 STR(PTR) " 6b,8b\n" 1841 STR(PTR) " 7b,8b\n" 1842 STR(PTR) " 0b,8b\n" 1843 " .previous\n" 1844 " .set pop\n" 1845 : "+&r"(rt), "=&r"(rs), 1846 "+&r"(vaddr), "+&r"(err) 1847 : "i"(SIGSEGV) 1848 : "memory"); 1849 1850 MIPS_R2_STATS(stores); 1851 break; 1852 1853 case sdr_op: 1854 if (IS_ENABLED(CONFIG_32BIT)) { 1855 err = SIGILL; 1856 break; 1857 } 1858 1859 rt = regs->regs[MIPSInst_RT(inst)]; 1860 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1861 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) { 1862 current->thread.cp0_baduaddr = vaddr; 1863 err = SIGSEGV; 1864 break; 1865 } 1866 __asm__ __volatile__( 1867 " .set push\n" 1868 " .set reorder\n" 1869 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1870 " dext %1, %0, 0, 8\n" 1871 "1: sb %1, 0(%2)\n" 1872 " daddiu %2, %2, 1\n" 1873 " andi %1, %2, 0x7\n" 1874 " beq $0, %1, 9f\n" 1875 " dext %1, %0, 8, 8\n" 1876 "2: sb %1, 0(%2)\n" 1877 " daddiu %2, %2, 1\n" 1878 " andi %1, %2, 0x7\n" 1879 " beq $0, %1, 9f\n" 1880 " dext %1, %0, 16, 8\n" 1881 "3: sb %1, 0(%2)\n" 1882 " daddiu %2, %2, 1\n" 1883 " andi %1, %2, 0x7\n" 1884 " beq $0, %1, 9f\n" 1885 " dext %1, %0, 24, 8\n" 1886 "4: sb %1, 0(%2)\n" 1887 " daddiu %2, %2, 1\n" 1888 " andi %1, %2, 0x7\n" 1889 " beq $0, %1, 9f\n" 1890 " dextu %1, %0, 32, 8\n" 1891 "5: sb %1, 0(%2)\n" 1892 " daddiu %2, %2, 1\n" 1893 " andi %1, %2, 0x7\n" 1894 " beq $0, %1, 9f\n" 1895 " dextu %1, %0, 40, 8\n" 1896 "6: sb %1, 0(%2)\n" 1897 " daddiu %2, %2, 1\n" 1898 " andi %1, %2, 0x7\n" 1899 " beq $0, %1, 9f\n" 1900 " dextu %1, %0, 48, 8\n" 1901 "7: sb %1, 0(%2)\n" 1902 " daddiu %2, %2, 1\n" 1903 " andi %1, %2, 0x7\n" 1904 " beq $0, %1, 9f\n" 1905 " dextu %1, %0, 56, 8\n" 1906 "0: sb %1, 0(%2)\n" 1907 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1908 " dext %1, %0, 0, 8\n" 1909 "1: sb %1, 0(%2)\n" 1910 " andi %1, %2, 0x7\n" 1911 " beq $0, %1, 9f\n" 1912 " daddiu %2, %2, -1\n" 1913 " dext %1, %0, 8, 8\n" 1914 "2: sb %1, 0(%2)\n" 1915 " andi %1, %2, 0x7\n" 1916 " beq $0, %1, 9f\n" 1917 " daddiu %2, %2, -1\n" 1918 " dext %1, %0, 16, 8\n" 1919 "3: sb %1, 0(%2)\n" 1920 " andi %1, %2, 0x7\n" 1921 " beq $0, %1, 9f\n" 1922 " daddiu %2, %2, -1\n" 1923 " dext %1, %0, 24, 8\n" 1924 "4: sb %1, 0(%2)\n" 1925 " andi %1, %2, 0x7\n" 1926 " beq $0, %1, 9f\n" 1927 " daddiu %2, %2, -1\n" 1928 " dextu %1, %0, 32, 8\n" 1929 "5: sb %1, 0(%2)\n" 1930 " andi %1, %2, 0x7\n" 1931 " beq $0, %1, 9f\n" 1932 " daddiu %2, %2, -1\n" 1933 " dextu %1, %0, 40, 8\n" 1934 "6: sb %1, 0(%2)\n" 1935 " andi %1, %2, 0x7\n" 1936 " beq $0, %1, 9f\n" 1937 " daddiu %2, %2, -1\n" 1938 " dextu %1, %0, 48, 8\n" 1939 "7: sb %1, 0(%2)\n" 1940 " andi %1, %2, 0x7\n" 1941 " beq $0, %1, 9f\n" 1942 " daddiu %2, %2, -1\n" 1943 " dextu %1, %0, 56, 8\n" 1944 "0: sb %1, 0(%2)\n" 1945 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1946 "9:\n" 1947 " .insn\n" 1948 " .section .fixup,\"ax\"\n" 1949 "8: li %3,%4\n" 1950 " j 9b\n" 1951 " .previous\n" 1952 " .section __ex_table,\"a\"\n" 1953 STR(PTR) " 1b,8b\n" 1954 STR(PTR) " 2b,8b\n" 1955 STR(PTR) " 3b,8b\n" 1956 STR(PTR) " 4b,8b\n" 1957 STR(PTR) " 5b,8b\n" 1958 STR(PTR) " 6b,8b\n" 1959 STR(PTR) " 7b,8b\n" 1960 STR(PTR) " 0b,8b\n" 1961 " .previous\n" 1962 " .set pop\n" 1963 : "+&r"(rt), "=&r"(rs), 1964 "+&r"(vaddr), "+&r"(err) 1965 : "i"(SIGSEGV) 1966 : "memory"); 1967 1968 MIPS_R2_STATS(stores); 1969 1970 break; 1971 case ll_op: 1972 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1973 if (vaddr & 0x3) { 1974 current->thread.cp0_baduaddr = vaddr; 1975 err = SIGBUS; 1976 break; 1977 } 1978 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) { 1979 current->thread.cp0_baduaddr = vaddr; 1980 err = SIGBUS; 1981 break; 1982 } 1983 1984 if (!cpu_has_rw_llb) { 1985 /* 1986 * An LL/SC block can't be safely emulated without 1987 * a Config5/LLB availability. So it's probably time to 1988 * kill our process before things get any worse. This is 1989 * because Config5/LLB allows us to use ERETNC so that 1990 * the LLAddr/LLB bit is not cleared when we return from 1991 * an exception. MIPS R2 LL/SC instructions trap with an 1992 * RI exception so once we emulate them here, we return 1993 * back to userland with ERETNC. That preserves the 1994 * LLAddr/LLB so the subsequent SC instruction will 1995 * succeed preserving the atomic semantics of the LL/SC 1996 * block. Without that, there is no safe way to emulate 1997 * an LL/SC block in MIPSR2 userland. 1998 */ 1999 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2000 err = SIGKILL; 2001 break; 2002 } 2003 2004 __asm__ __volatile__( 2005 "1:\n" 2006 "ll %0, 0(%2)\n" 2007 "2:\n" 2008 ".insn\n" 2009 ".section .fixup,\"ax\"\n" 2010 "3:\n" 2011 "li %1, %3\n" 2012 "j 2b\n" 2013 ".previous\n" 2014 ".section __ex_table,\"a\"\n" 2015 STR(PTR) " 1b,3b\n" 2016 ".previous\n" 2017 : "=&r"(res), "+&r"(err) 2018 : "r"(vaddr), "i"(SIGSEGV) 2019 : "memory"); 2020 2021 if (MIPSInst_RT(inst) && !err) 2022 regs->regs[MIPSInst_RT(inst)] = res; 2023 MIPS_R2_STATS(llsc); 2024 2025 break; 2026 2027 case sc_op: 2028 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2029 if (vaddr & 0x3) { 2030 current->thread.cp0_baduaddr = vaddr; 2031 err = SIGBUS; 2032 break; 2033 } 2034 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) { 2035 current->thread.cp0_baduaddr = vaddr; 2036 err = SIGBUS; 2037 break; 2038 } 2039 2040 if (!cpu_has_rw_llb) { 2041 /* 2042 * An LL/SC block can't be safely emulated without 2043 * a Config5/LLB availability. So it's probably time to 2044 * kill our process before things get any worse. This is 2045 * because Config5/LLB allows us to use ERETNC so that 2046 * the LLAddr/LLB bit is not cleared when we return from 2047 * an exception. MIPS R2 LL/SC instructions trap with an 2048 * RI exception so once we emulate them here, we return 2049 * back to userland with ERETNC. That preserves the 2050 * LLAddr/LLB so the subsequent SC instruction will 2051 * succeed preserving the atomic semantics of the LL/SC 2052 * block. Without that, there is no safe way to emulate 2053 * an LL/SC block in MIPSR2 userland. 2054 */ 2055 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2056 err = SIGKILL; 2057 break; 2058 } 2059 2060 res = regs->regs[MIPSInst_RT(inst)]; 2061 2062 __asm__ __volatile__( 2063 "1:\n" 2064 "sc %0, 0(%2)\n" 2065 "2:\n" 2066 ".insn\n" 2067 ".section .fixup,\"ax\"\n" 2068 "3:\n" 2069 "li %1, %3\n" 2070 "j 2b\n" 2071 ".previous\n" 2072 ".section __ex_table,\"a\"\n" 2073 STR(PTR) " 1b,3b\n" 2074 ".previous\n" 2075 : "+&r"(res), "+&r"(err) 2076 : "r"(vaddr), "i"(SIGSEGV)); 2077 2078 if (MIPSInst_RT(inst) && !err) 2079 regs->regs[MIPSInst_RT(inst)] = res; 2080 2081 MIPS_R2_STATS(llsc); 2082 2083 break; 2084 2085 case lld_op: 2086 if (IS_ENABLED(CONFIG_32BIT)) { 2087 err = SIGILL; 2088 break; 2089 } 2090 2091 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2092 if (vaddr & 0x7) { 2093 current->thread.cp0_baduaddr = vaddr; 2094 err = SIGBUS; 2095 break; 2096 } 2097 if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) { 2098 current->thread.cp0_baduaddr = vaddr; 2099 err = SIGBUS; 2100 break; 2101 } 2102 2103 if (!cpu_has_rw_llb) { 2104 /* 2105 * An LL/SC block can't be safely emulated without 2106 * a Config5/LLB availability. So it's probably time to 2107 * kill our process before things get any worse. This is 2108 * because Config5/LLB allows us to use ERETNC so that 2109 * the LLAddr/LLB bit is not cleared when we return from 2110 * an exception. MIPS R2 LL/SC instructions trap with an 2111 * RI exception so once we emulate them here, we return 2112 * back to userland with ERETNC. That preserves the 2113 * LLAddr/LLB so the subsequent SC instruction will 2114 * succeed preserving the atomic semantics of the LL/SC 2115 * block. Without that, there is no safe way to emulate 2116 * an LL/SC block in MIPSR2 userland. 2117 */ 2118 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2119 err = SIGKILL; 2120 break; 2121 } 2122 2123 __asm__ __volatile__( 2124 "1:\n" 2125 "lld %0, 0(%2)\n" 2126 "2:\n" 2127 ".insn\n" 2128 ".section .fixup,\"ax\"\n" 2129 "3:\n" 2130 "li %1, %3\n" 2131 "j 2b\n" 2132 ".previous\n" 2133 ".section __ex_table,\"a\"\n" 2134 STR(PTR) " 1b,3b\n" 2135 ".previous\n" 2136 : "=&r"(res), "+&r"(err) 2137 : "r"(vaddr), "i"(SIGSEGV) 2138 : "memory"); 2139 if (MIPSInst_RT(inst) && !err) 2140 regs->regs[MIPSInst_RT(inst)] = res; 2141 2142 MIPS_R2_STATS(llsc); 2143 2144 break; 2145 2146 case scd_op: 2147 if (IS_ENABLED(CONFIG_32BIT)) { 2148 err = SIGILL; 2149 break; 2150 } 2151 2152 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2153 if (vaddr & 0x7) { 2154 current->thread.cp0_baduaddr = vaddr; 2155 err = SIGBUS; 2156 break; 2157 } 2158 if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) { 2159 current->thread.cp0_baduaddr = vaddr; 2160 err = SIGBUS; 2161 break; 2162 } 2163 2164 if (!cpu_has_rw_llb) { 2165 /* 2166 * An LL/SC block can't be safely emulated without 2167 * a Config5/LLB availability. So it's probably time to 2168 * kill our process before things get any worse. This is 2169 * because Config5/LLB allows us to use ERETNC so that 2170 * the LLAddr/LLB bit is not cleared when we return from 2171 * an exception. MIPS R2 LL/SC instructions trap with an 2172 * RI exception so once we emulate them here, we return 2173 * back to userland with ERETNC. That preserves the 2174 * LLAddr/LLB so the subsequent SC instruction will 2175 * succeed preserving the atomic semantics of the LL/SC 2176 * block. Without that, there is no safe way to emulate 2177 * an LL/SC block in MIPSR2 userland. 2178 */ 2179 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2180 err = SIGKILL; 2181 break; 2182 } 2183 2184 res = regs->regs[MIPSInst_RT(inst)]; 2185 2186 __asm__ __volatile__( 2187 "1:\n" 2188 "scd %0, 0(%2)\n" 2189 "2:\n" 2190 ".insn\n" 2191 ".section .fixup,\"ax\"\n" 2192 "3:\n" 2193 "li %1, %3\n" 2194 "j 2b\n" 2195 ".previous\n" 2196 ".section __ex_table,\"a\"\n" 2197 STR(PTR) " 1b,3b\n" 2198 ".previous\n" 2199 : "+&r"(res), "+&r"(err) 2200 : "r"(vaddr), "i"(SIGSEGV)); 2201 2202 if (MIPSInst_RT(inst) && !err) 2203 regs->regs[MIPSInst_RT(inst)] = res; 2204 2205 MIPS_R2_STATS(llsc); 2206 2207 break; 2208 case pref_op: 2209 /* skip it */ 2210 break; 2211 default: 2212 err = SIGILL; 2213 } 2214 2215 /* 2216 * Let's not return to userland just yet. It's costly and 2217 * it's likely we have more R2 instructions to emulate 2218 */ 2219 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { 2220 regs->cp0_cause &= ~CAUSEF_BD; 2221 err = get_user(inst, (u32 __user *)regs->cp0_epc); 2222 if (!err) 2223 goto repeat; 2224 2225 if (err < 0) 2226 err = SIGSEGV; 2227 } 2228 2229 if (err && (err != SIGEMT)) { 2230 regs->regs[31] = r31; 2231 regs->cp0_epc = epc; 2232 } 2233 2234 /* Likely a MIPS R6 compatible instruction */ 2235 if (pass && (err == SIGILL)) 2236 err = 0; 2237 2238 return err; 2239 } 2240 2241 #ifdef CONFIG_DEBUG_FS 2242 2243 static int mipsr2_stats_show(struct seq_file *s, void *unused) 2244 { 2245 2246 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); 2247 seq_printf(s, "movs\t\t%ld\t%ld\n", 2248 (unsigned long)__this_cpu_read(mipsr2emustats.movs), 2249 (unsigned long)__this_cpu_read(mipsr2bdemustats.movs)); 2250 seq_printf(s, "hilo\t\t%ld\t%ld\n", 2251 (unsigned long)__this_cpu_read(mipsr2emustats.hilo), 2252 (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo)); 2253 seq_printf(s, "muls\t\t%ld\t%ld\n", 2254 (unsigned long)__this_cpu_read(mipsr2emustats.muls), 2255 (unsigned long)__this_cpu_read(mipsr2bdemustats.muls)); 2256 seq_printf(s, "divs\t\t%ld\t%ld\n", 2257 (unsigned long)__this_cpu_read(mipsr2emustats.divs), 2258 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); 2259 seq_printf(s, "dsps\t\t%ld\t%ld\n", 2260 (unsigned long)__this_cpu_read(mipsr2emustats.dsps), 2261 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps)); 2262 seq_printf(s, "bops\t\t%ld\t%ld\n", 2263 (unsigned long)__this_cpu_read(mipsr2emustats.bops), 2264 (unsigned long)__this_cpu_read(mipsr2bdemustats.bops)); 2265 seq_printf(s, "traps\t\t%ld\t%ld\n", 2266 (unsigned long)__this_cpu_read(mipsr2emustats.traps), 2267 (unsigned long)__this_cpu_read(mipsr2bdemustats.traps)); 2268 seq_printf(s, "fpus\t\t%ld\t%ld\n", 2269 (unsigned long)__this_cpu_read(mipsr2emustats.fpus), 2270 (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus)); 2271 seq_printf(s, "loads\t\t%ld\t%ld\n", 2272 (unsigned long)__this_cpu_read(mipsr2emustats.loads), 2273 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); 2274 seq_printf(s, "stores\t\t%ld\t%ld\n", 2275 (unsigned long)__this_cpu_read(mipsr2emustats.stores), 2276 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); 2277 seq_printf(s, "llsc\t\t%ld\t%ld\n", 2278 (unsigned long)__this_cpu_read(mipsr2emustats.llsc), 2279 (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc)); 2280 seq_printf(s, "dsemul\t\t%ld\t%ld\n", 2281 (unsigned long)__this_cpu_read(mipsr2emustats.dsemul), 2282 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul)); 2283 seq_printf(s, "jr\t\t%ld\n", 2284 (unsigned long)__this_cpu_read(mipsr2bremustats.jrs)); 2285 seq_printf(s, "bltzl\t\t%ld\n", 2286 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl)); 2287 seq_printf(s, "bgezl\t\t%ld\n", 2288 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl)); 2289 seq_printf(s, "bltzll\t\t%ld\n", 2290 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll)); 2291 seq_printf(s, "bgezll\t\t%ld\n", 2292 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll)); 2293 seq_printf(s, "bltzal\t\t%ld\n", 2294 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal)); 2295 seq_printf(s, "bgezal\t\t%ld\n", 2296 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal)); 2297 seq_printf(s, "beql\t\t%ld\n", 2298 (unsigned long)__this_cpu_read(mipsr2bremustats.beql)); 2299 seq_printf(s, "bnel\t\t%ld\n", 2300 (unsigned long)__this_cpu_read(mipsr2bremustats.bnel)); 2301 seq_printf(s, "blezl\t\t%ld\n", 2302 (unsigned long)__this_cpu_read(mipsr2bremustats.blezl)); 2303 seq_printf(s, "bgtzl\t\t%ld\n", 2304 (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl)); 2305 2306 return 0; 2307 } 2308 2309 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused) 2310 { 2311 mipsr2_stats_show(s, unused); 2312 2313 __this_cpu_write((mipsr2emustats).movs, 0); 2314 __this_cpu_write((mipsr2bdemustats).movs, 0); 2315 __this_cpu_write((mipsr2emustats).hilo, 0); 2316 __this_cpu_write((mipsr2bdemustats).hilo, 0); 2317 __this_cpu_write((mipsr2emustats).muls, 0); 2318 __this_cpu_write((mipsr2bdemustats).muls, 0); 2319 __this_cpu_write((mipsr2emustats).divs, 0); 2320 __this_cpu_write((mipsr2bdemustats).divs, 0); 2321 __this_cpu_write((mipsr2emustats).dsps, 0); 2322 __this_cpu_write((mipsr2bdemustats).dsps, 0); 2323 __this_cpu_write((mipsr2emustats).bops, 0); 2324 __this_cpu_write((mipsr2bdemustats).bops, 0); 2325 __this_cpu_write((mipsr2emustats).traps, 0); 2326 __this_cpu_write((mipsr2bdemustats).traps, 0); 2327 __this_cpu_write((mipsr2emustats).fpus, 0); 2328 __this_cpu_write((mipsr2bdemustats).fpus, 0); 2329 __this_cpu_write((mipsr2emustats).loads, 0); 2330 __this_cpu_write((mipsr2bdemustats).loads, 0); 2331 __this_cpu_write((mipsr2emustats).stores, 0); 2332 __this_cpu_write((mipsr2bdemustats).stores, 0); 2333 __this_cpu_write((mipsr2emustats).llsc, 0); 2334 __this_cpu_write((mipsr2bdemustats).llsc, 0); 2335 __this_cpu_write((mipsr2emustats).dsemul, 0); 2336 __this_cpu_write((mipsr2bdemustats).dsemul, 0); 2337 __this_cpu_write((mipsr2bremustats).jrs, 0); 2338 __this_cpu_write((mipsr2bremustats).bltzl, 0); 2339 __this_cpu_write((mipsr2bremustats).bgezl, 0); 2340 __this_cpu_write((mipsr2bremustats).bltzll, 0); 2341 __this_cpu_write((mipsr2bremustats).bgezll, 0); 2342 __this_cpu_write((mipsr2bremustats).bltzall, 0); 2343 __this_cpu_write((mipsr2bremustats).bgezall, 0); 2344 __this_cpu_write((mipsr2bremustats).bltzal, 0); 2345 __this_cpu_write((mipsr2bremustats).bgezal, 0); 2346 __this_cpu_write((mipsr2bremustats).beql, 0); 2347 __this_cpu_write((mipsr2bremustats).bnel, 0); 2348 __this_cpu_write((mipsr2bremustats).blezl, 0); 2349 __this_cpu_write((mipsr2bremustats).bgtzl, 0); 2350 2351 return 0; 2352 } 2353 2354 static int mipsr2_stats_open(struct inode *inode, struct file *file) 2355 { 2356 return single_open(file, mipsr2_stats_show, inode->i_private); 2357 } 2358 2359 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file) 2360 { 2361 return single_open(file, mipsr2_stats_clear_show, inode->i_private); 2362 } 2363 2364 static const struct file_operations mipsr2_emul_fops = { 2365 .open = mipsr2_stats_open, 2366 .read = seq_read, 2367 .llseek = seq_lseek, 2368 .release = single_release, 2369 }; 2370 2371 static const struct file_operations mipsr2_clear_fops = { 2372 .open = mipsr2_stats_clear_open, 2373 .read = seq_read, 2374 .llseek = seq_lseek, 2375 .release = single_release, 2376 }; 2377 2378 2379 static int __init mipsr2_init_debugfs(void) 2380 { 2381 struct dentry *mipsr2_emul; 2382 2383 if (!mips_debugfs_dir) 2384 return -ENODEV; 2385 2386 mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO, 2387 mips_debugfs_dir, NULL, 2388 &mipsr2_emul_fops); 2389 if (!mipsr2_emul) 2390 return -ENOMEM; 2391 2392 mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO, 2393 mips_debugfs_dir, NULL, 2394 &mipsr2_clear_fops); 2395 if (!mipsr2_emul) 2396 return -ENOMEM; 2397 2398 return 0; 2399 } 2400 2401 device_initcall(mipsr2_init_debugfs); 2402 2403 #endif /* CONFIG_DEBUG_FS */ 2404