1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2014 Imagination Technologies Ltd. 7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> 8 * Author: Markos Chandras <markos.chandras@imgtec.com> 9 * 10 * MIPS R2 user space instruction emulator for MIPS R6 11 * 12 */ 13 #include <linux/bug.h> 14 #include <linux/compiler.h> 15 #include <linux/debugfs.h> 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/ptrace.h> 19 #include <linux/seq_file.h> 20 21 #include <asm/asm.h> 22 #include <asm/branch.h> 23 #include <asm/break.h> 24 #include <asm/debug.h> 25 #include <asm/fpu.h> 26 #include <asm/fpu_emulator.h> 27 #include <asm/inst.h> 28 #include <asm/mips-r2-to-r6-emul.h> 29 #include <asm/local.h> 30 #include <asm/mipsregs.h> 31 #include <asm/ptrace.h> 32 #include <linux/uaccess.h> 33 34 #ifdef CONFIG_64BIT 35 #define ADDIU "daddiu " 36 #define INS "dins " 37 #define EXT "dext " 38 #else 39 #define ADDIU "addiu " 40 #define INS "ins " 41 #define EXT "ext " 42 #endif /* CONFIG_64BIT */ 43 44 #define SB "sb " 45 #define LB "lb " 46 #define LL "ll " 47 #define SC "sc " 48 49 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats); 50 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats); 51 DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats); 52 53 extern const unsigned int fpucondbit[8]; 54 55 #define MIPS_R2_EMUL_TOTAL_PASS 10 56 57 int mipsr2_emulation = 0; 58 59 static int __init mipsr2emu_enable(char *s) 60 { 61 mipsr2_emulation = 1; 62 63 pr_info("MIPS R2-to-R6 Emulator Enabled!"); 64 65 return 1; 66 } 67 __setup("mipsr2emu", mipsr2emu_enable); 68 69 /** 70 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot 71 * for performance instead of the traditional way of using a stack trampoline 72 * which is rather slow. 73 * @regs: Process register set 74 * @ir: Instruction 75 */ 76 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) 77 { 78 switch (MIPSInst_OPCODE(ir)) { 79 case addiu_op: 80 if (MIPSInst_RT(ir)) 81 regs->regs[MIPSInst_RT(ir)] = 82 (s32)regs->regs[MIPSInst_RS(ir)] + 83 (s32)MIPSInst_SIMM(ir); 84 return 0; 85 case daddiu_op: 86 if (IS_ENABLED(CONFIG_32BIT)) 87 break; 88 89 if (MIPSInst_RT(ir)) 90 regs->regs[MIPSInst_RT(ir)] = 91 (s64)regs->regs[MIPSInst_RS(ir)] + 92 (s64)MIPSInst_SIMM(ir); 93 return 0; 94 case lwc1_op: 95 case swc1_op: 96 case cop1_op: 97 case cop1x_op: 98 /* FPU instructions in delay slot */ 99 return -SIGFPE; 100 case spec_op: 101 switch (MIPSInst_FUNC(ir)) { 102 case or_op: 103 if (MIPSInst_RD(ir)) 104 regs->regs[MIPSInst_RD(ir)] = 105 regs->regs[MIPSInst_RS(ir)] | 106 regs->regs[MIPSInst_RT(ir)]; 107 return 0; 108 case sll_op: 109 if (MIPSInst_RS(ir)) 110 break; 111 112 if (MIPSInst_RD(ir)) 113 regs->regs[MIPSInst_RD(ir)] = 114 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << 115 MIPSInst_FD(ir)); 116 return 0; 117 case srl_op: 118 if (MIPSInst_RS(ir)) 119 break; 120 121 if (MIPSInst_RD(ir)) 122 regs->regs[MIPSInst_RD(ir)] = 123 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> 124 MIPSInst_FD(ir)); 125 return 0; 126 case addu_op: 127 if (MIPSInst_FD(ir)) 128 break; 129 130 if (MIPSInst_RD(ir)) 131 regs->regs[MIPSInst_RD(ir)] = 132 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + 133 (u32)regs->regs[MIPSInst_RT(ir)]); 134 return 0; 135 case subu_op: 136 if (MIPSInst_FD(ir)) 137 break; 138 139 if (MIPSInst_RD(ir)) 140 regs->regs[MIPSInst_RD(ir)] = 141 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - 142 (u32)regs->regs[MIPSInst_RT(ir)]); 143 return 0; 144 case dsll_op: 145 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir)) 146 break; 147 148 if (MIPSInst_RD(ir)) 149 regs->regs[MIPSInst_RD(ir)] = 150 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << 151 MIPSInst_FD(ir)); 152 return 0; 153 case dsrl_op: 154 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_RS(ir)) 155 break; 156 157 if (MIPSInst_RD(ir)) 158 regs->regs[MIPSInst_RD(ir)] = 159 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> 160 MIPSInst_FD(ir)); 161 return 0; 162 case daddu_op: 163 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir)) 164 break; 165 166 if (MIPSInst_RD(ir)) 167 regs->regs[MIPSInst_RD(ir)] = 168 (u64)regs->regs[MIPSInst_RS(ir)] + 169 (u64)regs->regs[MIPSInst_RT(ir)]; 170 return 0; 171 case dsubu_op: 172 if (IS_ENABLED(CONFIG_32BIT) || MIPSInst_FD(ir)) 173 break; 174 175 if (MIPSInst_RD(ir)) 176 regs->regs[MIPSInst_RD(ir)] = 177 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - 178 (u64)regs->regs[MIPSInst_RT(ir)]); 179 return 0; 180 } 181 break; 182 default: 183 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n", 184 ir, MIPSInst_OPCODE(ir)); 185 } 186 187 return SIGILL; 188 } 189 190 /** 191 * movf_func - Emulate a MOVF instruction 192 * @regs: Process register set 193 * @ir: Instruction 194 * 195 * Returns 0 since it always succeeds. 196 */ 197 static int movf_func(struct pt_regs *regs, u32 ir) 198 { 199 u32 csr; 200 u32 cond; 201 202 csr = current->thread.fpu.fcr31; 203 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 204 205 if (((csr & cond) == 0) && MIPSInst_RD(ir)) 206 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 207 208 MIPS_R2_STATS(movs); 209 210 return 0; 211 } 212 213 /** 214 * movt_func - Emulate a MOVT instruction 215 * @regs: Process register set 216 * @ir: Instruction 217 * 218 * Returns 0 since it always succeeds. 219 */ 220 static int movt_func(struct pt_regs *regs, u32 ir) 221 { 222 u32 csr; 223 u32 cond; 224 225 csr = current->thread.fpu.fcr31; 226 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 227 228 if (((csr & cond) != 0) && MIPSInst_RD(ir)) 229 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 230 231 MIPS_R2_STATS(movs); 232 233 return 0; 234 } 235 236 /** 237 * jr_func - Emulate a JR instruction. 238 * @pt_regs: Process register set 239 * @ir: Instruction 240 * 241 * Returns SIGILL if JR was in delay slot, SIGEMT if we 242 * can't compute the EPC, SIGSEGV if we can't access the 243 * userland instruction or 0 on success. 244 */ 245 static int jr_func(struct pt_regs *regs, u32 ir) 246 { 247 int err; 248 unsigned long cepc, epc, nepc; 249 u32 nir; 250 251 if (delay_slot(regs)) 252 return SIGILL; 253 254 /* EPC after the RI/JR instruction */ 255 nepc = regs->cp0_epc; 256 /* Roll back to the reserved R2 JR instruction */ 257 regs->cp0_epc -= 4; 258 epc = regs->cp0_epc; 259 err = __compute_return_epc(regs); 260 261 if (err < 0) 262 return SIGEMT; 263 264 265 /* Computed EPC */ 266 cepc = regs->cp0_epc; 267 268 /* Get DS instruction */ 269 err = __get_user(nir, (u32 __user *)nepc); 270 if (err) 271 return SIGSEGV; 272 273 MIPS_R2BR_STATS(jrs); 274 275 /* If nir == 0(NOP), then nothing else to do */ 276 if (nir) { 277 /* 278 * Negative err means FPU instruction in BD-slot, 279 * Zero err means 'BD-slot emulation done' 280 * For anything else we go back to trampoline emulation. 281 */ 282 err = mipsr6_emul(regs, nir); 283 if (err > 0) { 284 regs->cp0_epc = nepc; 285 err = mips_dsemul(regs, nir, epc, cepc); 286 if (err == SIGILL) 287 err = SIGEMT; 288 MIPS_R2_STATS(dsemul); 289 } 290 } 291 292 return err; 293 } 294 295 /** 296 * movz_func - Emulate a MOVZ instruction 297 * @regs: Process register set 298 * @ir: Instruction 299 * 300 * Returns 0 since it always succeeds. 301 */ 302 static int movz_func(struct pt_regs *regs, u32 ir) 303 { 304 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) 305 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 306 MIPS_R2_STATS(movs); 307 308 return 0; 309 } 310 311 /** 312 * movn_func - Emulate a MOVZ instruction 313 * @regs: Process register set 314 * @ir: Instruction 315 * 316 * Returns 0 since it always succeeds. 317 */ 318 static int movn_func(struct pt_regs *regs, u32 ir) 319 { 320 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) 321 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 322 MIPS_R2_STATS(movs); 323 324 return 0; 325 } 326 327 /** 328 * mfhi_func - Emulate a MFHI instruction 329 * @regs: Process register set 330 * @ir: Instruction 331 * 332 * Returns 0 since it always succeeds. 333 */ 334 static int mfhi_func(struct pt_regs *regs, u32 ir) 335 { 336 if (MIPSInst_RD(ir)) 337 regs->regs[MIPSInst_RD(ir)] = regs->hi; 338 339 MIPS_R2_STATS(hilo); 340 341 return 0; 342 } 343 344 /** 345 * mthi_func - Emulate a MTHI instruction 346 * @regs: Process register set 347 * @ir: Instruction 348 * 349 * Returns 0 since it always succeeds. 350 */ 351 static int mthi_func(struct pt_regs *regs, u32 ir) 352 { 353 regs->hi = regs->regs[MIPSInst_RS(ir)]; 354 355 MIPS_R2_STATS(hilo); 356 357 return 0; 358 } 359 360 /** 361 * mflo_func - Emulate a MFLO instruction 362 * @regs: Process register set 363 * @ir: Instruction 364 * 365 * Returns 0 since it always succeeds. 366 */ 367 static int mflo_func(struct pt_regs *regs, u32 ir) 368 { 369 if (MIPSInst_RD(ir)) 370 regs->regs[MIPSInst_RD(ir)] = regs->lo; 371 372 MIPS_R2_STATS(hilo); 373 374 return 0; 375 } 376 377 /** 378 * mtlo_func - Emulate a MTLO instruction 379 * @regs: Process register set 380 * @ir: Instruction 381 * 382 * Returns 0 since it always succeeds. 383 */ 384 static int mtlo_func(struct pt_regs *regs, u32 ir) 385 { 386 regs->lo = regs->regs[MIPSInst_RS(ir)]; 387 388 MIPS_R2_STATS(hilo); 389 390 return 0; 391 } 392 393 /** 394 * mult_func - Emulate a MULT instruction 395 * @regs: Process register set 396 * @ir: Instruction 397 * 398 * Returns 0 since it always succeeds. 399 */ 400 static int mult_func(struct pt_regs *regs, u32 ir) 401 { 402 s64 res; 403 s32 rt, rs; 404 405 rt = regs->regs[MIPSInst_RT(ir)]; 406 rs = regs->regs[MIPSInst_RS(ir)]; 407 res = (s64)rt * (s64)rs; 408 409 rs = res; 410 regs->lo = (s64)rs; 411 rt = res >> 32; 412 res = (s64)rt; 413 regs->hi = res; 414 415 MIPS_R2_STATS(muls); 416 417 return 0; 418 } 419 420 /** 421 * multu_func - Emulate a MULTU instruction 422 * @regs: Process register set 423 * @ir: Instruction 424 * 425 * Returns 0 since it always succeeds. 426 */ 427 static int multu_func(struct pt_regs *regs, u32 ir) 428 { 429 u64 res; 430 u32 rt, rs; 431 432 rt = regs->regs[MIPSInst_RT(ir)]; 433 rs = regs->regs[MIPSInst_RS(ir)]; 434 res = (u64)rt * (u64)rs; 435 rt = res; 436 regs->lo = (s64)rt; 437 regs->hi = (s64)(res >> 32); 438 439 MIPS_R2_STATS(muls); 440 441 return 0; 442 } 443 444 /** 445 * div_func - Emulate a DIV instruction 446 * @regs: Process register set 447 * @ir: Instruction 448 * 449 * Returns 0 since it always succeeds. 450 */ 451 static int div_func(struct pt_regs *regs, u32 ir) 452 { 453 s32 rt, rs; 454 455 rt = regs->regs[MIPSInst_RT(ir)]; 456 rs = regs->regs[MIPSInst_RS(ir)]; 457 458 regs->lo = (s64)(rs / rt); 459 regs->hi = (s64)(rs % rt); 460 461 MIPS_R2_STATS(divs); 462 463 return 0; 464 } 465 466 /** 467 * divu_func - Emulate a DIVU instruction 468 * @regs: Process register set 469 * @ir: Instruction 470 * 471 * Returns 0 since it always succeeds. 472 */ 473 static int divu_func(struct pt_regs *regs, u32 ir) 474 { 475 u32 rt, rs; 476 477 rt = regs->regs[MIPSInst_RT(ir)]; 478 rs = regs->regs[MIPSInst_RS(ir)]; 479 480 regs->lo = (s64)(rs / rt); 481 regs->hi = (s64)(rs % rt); 482 483 MIPS_R2_STATS(divs); 484 485 return 0; 486 } 487 488 /** 489 * dmult_func - Emulate a DMULT instruction 490 * @regs: Process register set 491 * @ir: Instruction 492 * 493 * Returns 0 on success or SIGILL for 32-bit kernels. 494 */ 495 static int dmult_func(struct pt_regs *regs, u32 ir) 496 { 497 s64 res; 498 s64 rt, rs; 499 500 if (IS_ENABLED(CONFIG_32BIT)) 501 return SIGILL; 502 503 rt = regs->regs[MIPSInst_RT(ir)]; 504 rs = regs->regs[MIPSInst_RS(ir)]; 505 res = rt * rs; 506 507 regs->lo = res; 508 __asm__ __volatile__( 509 "dmuh %0, %1, %2\t\n" 510 : "=r"(res) 511 : "r"(rt), "r"(rs)); 512 513 regs->hi = res; 514 515 MIPS_R2_STATS(muls); 516 517 return 0; 518 } 519 520 /** 521 * dmultu_func - Emulate a DMULTU instruction 522 * @regs: Process register set 523 * @ir: Instruction 524 * 525 * Returns 0 on success or SIGILL for 32-bit kernels. 526 */ 527 static int dmultu_func(struct pt_regs *regs, u32 ir) 528 { 529 u64 res; 530 u64 rt, rs; 531 532 if (IS_ENABLED(CONFIG_32BIT)) 533 return SIGILL; 534 535 rt = regs->regs[MIPSInst_RT(ir)]; 536 rs = regs->regs[MIPSInst_RS(ir)]; 537 res = rt * rs; 538 539 regs->lo = res; 540 __asm__ __volatile__( 541 "dmuhu %0, %1, %2\t\n" 542 : "=r"(res) 543 : "r"(rt), "r"(rs)); 544 545 regs->hi = res; 546 547 MIPS_R2_STATS(muls); 548 549 return 0; 550 } 551 552 /** 553 * ddiv_func - Emulate a DDIV instruction 554 * @regs: Process register set 555 * @ir: Instruction 556 * 557 * Returns 0 on success or SIGILL for 32-bit kernels. 558 */ 559 static int ddiv_func(struct pt_regs *regs, u32 ir) 560 { 561 s64 rt, rs; 562 563 if (IS_ENABLED(CONFIG_32BIT)) 564 return SIGILL; 565 566 rt = regs->regs[MIPSInst_RT(ir)]; 567 rs = regs->regs[MIPSInst_RS(ir)]; 568 569 regs->lo = rs / rt; 570 regs->hi = rs % rt; 571 572 MIPS_R2_STATS(divs); 573 574 return 0; 575 } 576 577 /** 578 * ddivu_func - Emulate a DDIVU instruction 579 * @regs: Process register set 580 * @ir: Instruction 581 * 582 * Returns 0 on success or SIGILL for 32-bit kernels. 583 */ 584 static int ddivu_func(struct pt_regs *regs, u32 ir) 585 { 586 u64 rt, rs; 587 588 if (IS_ENABLED(CONFIG_32BIT)) 589 return SIGILL; 590 591 rt = regs->regs[MIPSInst_RT(ir)]; 592 rs = regs->regs[MIPSInst_RS(ir)]; 593 594 regs->lo = rs / rt; 595 regs->hi = rs % rt; 596 597 MIPS_R2_STATS(divs); 598 599 return 0; 600 } 601 602 /* R6 removed instructions for the SPECIAL opcode */ 603 static struct r2_decoder_table spec_op_table[] = { 604 { 0xfc1ff83f, 0x00000008, jr_func }, 605 { 0xfc00ffff, 0x00000018, mult_func }, 606 { 0xfc00ffff, 0x00000019, multu_func }, 607 { 0xfc00ffff, 0x0000001c, dmult_func }, 608 { 0xfc00ffff, 0x0000001d, dmultu_func }, 609 { 0xffff07ff, 0x00000010, mfhi_func }, 610 { 0xfc1fffff, 0x00000011, mthi_func }, 611 { 0xffff07ff, 0x00000012, mflo_func }, 612 { 0xfc1fffff, 0x00000013, mtlo_func }, 613 { 0xfc0307ff, 0x00000001, movf_func }, 614 { 0xfc0307ff, 0x00010001, movt_func }, 615 { 0xfc0007ff, 0x0000000a, movz_func }, 616 { 0xfc0007ff, 0x0000000b, movn_func }, 617 { 0xfc00ffff, 0x0000001a, div_func }, 618 { 0xfc00ffff, 0x0000001b, divu_func }, 619 { 0xfc00ffff, 0x0000001e, ddiv_func }, 620 { 0xfc00ffff, 0x0000001f, ddivu_func }, 621 {} 622 }; 623 624 /** 625 * madd_func - Emulate a MADD instruction 626 * @regs: Process register set 627 * @ir: Instruction 628 * 629 * Returns 0 since it always succeeds. 630 */ 631 static int madd_func(struct pt_regs *regs, u32 ir) 632 { 633 s64 res; 634 s32 rt, rs; 635 636 rt = regs->regs[MIPSInst_RT(ir)]; 637 rs = regs->regs[MIPSInst_RS(ir)]; 638 res = (s64)rt * (s64)rs; 639 rt = regs->hi; 640 rs = regs->lo; 641 res += ((((s64)rt) << 32) | (u32)rs); 642 643 rt = res; 644 regs->lo = (s64)rt; 645 rs = res >> 32; 646 regs->hi = (s64)rs; 647 648 MIPS_R2_STATS(dsps); 649 650 return 0; 651 } 652 653 /** 654 * maddu_func - Emulate a MADDU instruction 655 * @regs: Process register set 656 * @ir: Instruction 657 * 658 * Returns 0 since it always succeeds. 659 */ 660 static int maddu_func(struct pt_regs *regs, u32 ir) 661 { 662 u64 res; 663 u32 rt, rs; 664 665 rt = regs->regs[MIPSInst_RT(ir)]; 666 rs = regs->regs[MIPSInst_RS(ir)]; 667 res = (u64)rt * (u64)rs; 668 rt = regs->hi; 669 rs = regs->lo; 670 res += ((((s64)rt) << 32) | (u32)rs); 671 672 rt = res; 673 regs->lo = (s64)rt; 674 rs = res >> 32; 675 regs->hi = (s64)rs; 676 677 MIPS_R2_STATS(dsps); 678 679 return 0; 680 } 681 682 /** 683 * msub_func - Emulate a MSUB instruction 684 * @regs: Process register set 685 * @ir: Instruction 686 * 687 * Returns 0 since it always succeeds. 688 */ 689 static int msub_func(struct pt_regs *regs, u32 ir) 690 { 691 s64 res; 692 s32 rt, rs; 693 694 rt = regs->regs[MIPSInst_RT(ir)]; 695 rs = regs->regs[MIPSInst_RS(ir)]; 696 res = (s64)rt * (s64)rs; 697 rt = regs->hi; 698 rs = regs->lo; 699 res = ((((s64)rt) << 32) | (u32)rs) - res; 700 701 rt = res; 702 regs->lo = (s64)rt; 703 rs = res >> 32; 704 regs->hi = (s64)rs; 705 706 MIPS_R2_STATS(dsps); 707 708 return 0; 709 } 710 711 /** 712 * msubu_func - Emulate a MSUBU instruction 713 * @regs: Process register set 714 * @ir: Instruction 715 * 716 * Returns 0 since it always succeeds. 717 */ 718 static int msubu_func(struct pt_regs *regs, u32 ir) 719 { 720 u64 res; 721 u32 rt, rs; 722 723 rt = regs->regs[MIPSInst_RT(ir)]; 724 rs = regs->regs[MIPSInst_RS(ir)]; 725 res = (u64)rt * (u64)rs; 726 rt = regs->hi; 727 rs = regs->lo; 728 res = ((((s64)rt) << 32) | (u32)rs) - res; 729 730 rt = res; 731 regs->lo = (s64)rt; 732 rs = res >> 32; 733 regs->hi = (s64)rs; 734 735 MIPS_R2_STATS(dsps); 736 737 return 0; 738 } 739 740 /** 741 * mul_func - Emulate a MUL instruction 742 * @regs: Process register set 743 * @ir: Instruction 744 * 745 * Returns 0 since it always succeeds. 746 */ 747 static int mul_func(struct pt_regs *regs, u32 ir) 748 { 749 s64 res; 750 s32 rt, rs; 751 752 if (!MIPSInst_RD(ir)) 753 return 0; 754 rt = regs->regs[MIPSInst_RT(ir)]; 755 rs = regs->regs[MIPSInst_RS(ir)]; 756 res = (s64)rt * (s64)rs; 757 758 rs = res; 759 regs->regs[MIPSInst_RD(ir)] = (s64)rs; 760 761 MIPS_R2_STATS(muls); 762 763 return 0; 764 } 765 766 /** 767 * clz_func - Emulate a CLZ instruction 768 * @regs: Process register set 769 * @ir: Instruction 770 * 771 * Returns 0 since it always succeeds. 772 */ 773 static int clz_func(struct pt_regs *regs, u32 ir) 774 { 775 u32 res; 776 u32 rs; 777 778 if (!MIPSInst_RD(ir)) 779 return 0; 780 781 rs = regs->regs[MIPSInst_RS(ir)]; 782 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); 783 regs->regs[MIPSInst_RD(ir)] = res; 784 785 MIPS_R2_STATS(bops); 786 787 return 0; 788 } 789 790 /** 791 * clo_func - Emulate a CLO instruction 792 * @regs: Process register set 793 * @ir: Instruction 794 * 795 * Returns 0 since it always succeeds. 796 */ 797 798 static int clo_func(struct pt_regs *regs, u32 ir) 799 { 800 u32 res; 801 u32 rs; 802 803 if (!MIPSInst_RD(ir)) 804 return 0; 805 806 rs = regs->regs[MIPSInst_RS(ir)]; 807 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); 808 regs->regs[MIPSInst_RD(ir)] = res; 809 810 MIPS_R2_STATS(bops); 811 812 return 0; 813 } 814 815 /** 816 * dclz_func - Emulate a DCLZ instruction 817 * @regs: Process register set 818 * @ir: Instruction 819 * 820 * Returns 0 since it always succeeds. 821 */ 822 static int dclz_func(struct pt_regs *regs, u32 ir) 823 { 824 u64 res; 825 u64 rs; 826 827 if (IS_ENABLED(CONFIG_32BIT)) 828 return SIGILL; 829 830 if (!MIPSInst_RD(ir)) 831 return 0; 832 833 rs = regs->regs[MIPSInst_RS(ir)]; 834 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); 835 regs->regs[MIPSInst_RD(ir)] = res; 836 837 MIPS_R2_STATS(bops); 838 839 return 0; 840 } 841 842 /** 843 * dclo_func - Emulate a DCLO instruction 844 * @regs: Process register set 845 * @ir: Instruction 846 * 847 * Returns 0 since it always succeeds. 848 */ 849 static int dclo_func(struct pt_regs *regs, u32 ir) 850 { 851 u64 res; 852 u64 rs; 853 854 if (IS_ENABLED(CONFIG_32BIT)) 855 return SIGILL; 856 857 if (!MIPSInst_RD(ir)) 858 return 0; 859 860 rs = regs->regs[MIPSInst_RS(ir)]; 861 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); 862 regs->regs[MIPSInst_RD(ir)] = res; 863 864 MIPS_R2_STATS(bops); 865 866 return 0; 867 } 868 869 /* R6 removed instructions for the SPECIAL2 opcode */ 870 static struct r2_decoder_table spec2_op_table[] = { 871 { 0xfc00ffff, 0x70000000, madd_func }, 872 { 0xfc00ffff, 0x70000001, maddu_func }, 873 { 0xfc0007ff, 0x70000002, mul_func }, 874 { 0xfc00ffff, 0x70000004, msub_func }, 875 { 0xfc00ffff, 0x70000005, msubu_func }, 876 { 0xfc0007ff, 0x70000020, clz_func }, 877 { 0xfc0007ff, 0x70000021, clo_func }, 878 { 0xfc0007ff, 0x70000024, dclz_func }, 879 { 0xfc0007ff, 0x70000025, dclo_func }, 880 { } 881 }; 882 883 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst, 884 struct r2_decoder_table *table) 885 { 886 struct r2_decoder_table *p; 887 int err; 888 889 for (p = table; p->func; p++) { 890 if ((inst & p->mask) == p->code) { 891 err = (p->func)(regs, inst); 892 return err; 893 } 894 } 895 return SIGILL; 896 } 897 898 /** 899 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction 900 * @regs: Process register set 901 * @inst: Instruction to decode and emulate 902 * @fcr31: Floating Point Control and Status Register Cause bits returned 903 */ 904 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) 905 { 906 int err = 0; 907 unsigned long vaddr; 908 u32 nir; 909 unsigned long cpc, epc, nepc, r31, res, rs, rt; 910 911 void __user *fault_addr = NULL; 912 int pass = 0; 913 914 repeat: 915 r31 = regs->regs[31]; 916 epc = regs->cp0_epc; 917 err = compute_return_epc(regs); 918 if (err < 0) { 919 BUG(); 920 return SIGEMT; 921 } 922 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", 923 inst, epc, pass); 924 925 switch (MIPSInst_OPCODE(inst)) { 926 case spec_op: 927 err = mipsr2_find_op_func(regs, inst, spec_op_table); 928 if (err < 0) { 929 /* FPU instruction under JR */ 930 regs->cp0_cause |= CAUSEF_BD; 931 goto fpu_emul; 932 } 933 break; 934 case spec2_op: 935 err = mipsr2_find_op_func(regs, inst, spec2_op_table); 936 break; 937 case bcond_op: 938 rt = MIPSInst_RT(inst); 939 rs = MIPSInst_RS(inst); 940 switch (rt) { 941 case tgei_op: 942 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) 943 do_trap_or_bp(regs, 0, 0, "TGEI"); 944 945 MIPS_R2_STATS(traps); 946 947 break; 948 case tgeiu_op: 949 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) 950 do_trap_or_bp(regs, 0, 0, "TGEIU"); 951 952 MIPS_R2_STATS(traps); 953 954 break; 955 case tlti_op: 956 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) 957 do_trap_or_bp(regs, 0, 0, "TLTI"); 958 959 MIPS_R2_STATS(traps); 960 961 break; 962 case tltiu_op: 963 if (regs->regs[rs] < MIPSInst_UIMM(inst)) 964 do_trap_or_bp(regs, 0, 0, "TLTIU"); 965 966 MIPS_R2_STATS(traps); 967 968 break; 969 case teqi_op: 970 if (regs->regs[rs] == MIPSInst_SIMM(inst)) 971 do_trap_or_bp(regs, 0, 0, "TEQI"); 972 973 MIPS_R2_STATS(traps); 974 975 break; 976 case tnei_op: 977 if (regs->regs[rs] != MIPSInst_SIMM(inst)) 978 do_trap_or_bp(regs, 0, 0, "TNEI"); 979 980 MIPS_R2_STATS(traps); 981 982 break; 983 case bltzl_op: 984 case bgezl_op: 985 case bltzall_op: 986 case bgezall_op: 987 if (delay_slot(regs)) { 988 err = SIGILL; 989 break; 990 } 991 regs->regs[31] = r31; 992 regs->cp0_epc = epc; 993 err = __compute_return_epc(regs); 994 if (err < 0) 995 return SIGEMT; 996 if (err != BRANCH_LIKELY_TAKEN) 997 break; 998 cpc = regs->cp0_epc; 999 nepc = epc + 4; 1000 err = __get_user(nir, (u32 __user *)nepc); 1001 if (err) { 1002 err = SIGSEGV; 1003 break; 1004 } 1005 /* 1006 * This will probably be optimized away when 1007 * CONFIG_DEBUG_FS is not enabled 1008 */ 1009 switch (rt) { 1010 case bltzl_op: 1011 MIPS_R2BR_STATS(bltzl); 1012 break; 1013 case bgezl_op: 1014 MIPS_R2BR_STATS(bgezl); 1015 break; 1016 case bltzall_op: 1017 MIPS_R2BR_STATS(bltzall); 1018 break; 1019 case bgezall_op: 1020 MIPS_R2BR_STATS(bgezall); 1021 break; 1022 } 1023 1024 switch (MIPSInst_OPCODE(nir)) { 1025 case cop1_op: 1026 case cop1x_op: 1027 case lwc1_op: 1028 case swc1_op: 1029 regs->cp0_cause |= CAUSEF_BD; 1030 goto fpu_emul; 1031 } 1032 if (nir) { 1033 err = mipsr6_emul(regs, nir); 1034 if (err > 0) { 1035 err = mips_dsemul(regs, nir, epc, cpc); 1036 if (err == SIGILL) 1037 err = SIGEMT; 1038 MIPS_R2_STATS(dsemul); 1039 } 1040 } 1041 break; 1042 case bltzal_op: 1043 case bgezal_op: 1044 if (delay_slot(regs)) { 1045 err = SIGILL; 1046 break; 1047 } 1048 regs->regs[31] = r31; 1049 regs->cp0_epc = epc; 1050 err = __compute_return_epc(regs); 1051 if (err < 0) 1052 return SIGEMT; 1053 cpc = regs->cp0_epc; 1054 nepc = epc + 4; 1055 err = __get_user(nir, (u32 __user *)nepc); 1056 if (err) { 1057 err = SIGSEGV; 1058 break; 1059 } 1060 /* 1061 * This will probably be optimized away when 1062 * CONFIG_DEBUG_FS is not enabled 1063 */ 1064 switch (rt) { 1065 case bltzal_op: 1066 MIPS_R2BR_STATS(bltzal); 1067 break; 1068 case bgezal_op: 1069 MIPS_R2BR_STATS(bgezal); 1070 break; 1071 } 1072 1073 switch (MIPSInst_OPCODE(nir)) { 1074 case cop1_op: 1075 case cop1x_op: 1076 case lwc1_op: 1077 case swc1_op: 1078 regs->cp0_cause |= CAUSEF_BD; 1079 goto fpu_emul; 1080 } 1081 if (nir) { 1082 err = mipsr6_emul(regs, nir); 1083 if (err > 0) { 1084 err = mips_dsemul(regs, nir, epc, cpc); 1085 if (err == SIGILL) 1086 err = SIGEMT; 1087 MIPS_R2_STATS(dsemul); 1088 } 1089 } 1090 break; 1091 default: 1092 regs->regs[31] = r31; 1093 regs->cp0_epc = epc; 1094 err = SIGILL; 1095 break; 1096 } 1097 break; 1098 1099 case beql_op: 1100 case bnel_op: 1101 case blezl_op: 1102 case bgtzl_op: 1103 if (delay_slot(regs)) { 1104 err = SIGILL; 1105 break; 1106 } 1107 regs->regs[31] = r31; 1108 regs->cp0_epc = epc; 1109 err = __compute_return_epc(regs); 1110 if (err < 0) 1111 return SIGEMT; 1112 if (err != BRANCH_LIKELY_TAKEN) 1113 break; 1114 cpc = regs->cp0_epc; 1115 nepc = epc + 4; 1116 err = __get_user(nir, (u32 __user *)nepc); 1117 if (err) { 1118 err = SIGSEGV; 1119 break; 1120 } 1121 /* 1122 * This will probably be optimized away when 1123 * CONFIG_DEBUG_FS is not enabled 1124 */ 1125 switch (MIPSInst_OPCODE(inst)) { 1126 case beql_op: 1127 MIPS_R2BR_STATS(beql); 1128 break; 1129 case bnel_op: 1130 MIPS_R2BR_STATS(bnel); 1131 break; 1132 case blezl_op: 1133 MIPS_R2BR_STATS(blezl); 1134 break; 1135 case bgtzl_op: 1136 MIPS_R2BR_STATS(bgtzl); 1137 break; 1138 } 1139 1140 switch (MIPSInst_OPCODE(nir)) { 1141 case cop1_op: 1142 case cop1x_op: 1143 case lwc1_op: 1144 case swc1_op: 1145 regs->cp0_cause |= CAUSEF_BD; 1146 goto fpu_emul; 1147 } 1148 if (nir) { 1149 err = mipsr6_emul(regs, nir); 1150 if (err > 0) { 1151 err = mips_dsemul(regs, nir, epc, cpc); 1152 if (err == SIGILL) 1153 err = SIGEMT; 1154 MIPS_R2_STATS(dsemul); 1155 } 1156 } 1157 break; 1158 case lwc1_op: 1159 case swc1_op: 1160 case cop1_op: 1161 case cop1x_op: 1162 fpu_emul: 1163 regs->regs[31] = r31; 1164 regs->cp0_epc = epc; 1165 if (!used_math()) { /* First time FPU user. */ 1166 preempt_disable(); 1167 err = init_fpu(); 1168 preempt_enable(); 1169 set_used_math(); 1170 } 1171 lose_fpu(1); /* Save FPU state for the emulator. */ 1172 1173 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1174 &fault_addr); 1175 1176 /* 1177 * We can't allow the emulated instruction to leave any 1178 * enabled Cause bits set in $fcr31. 1179 */ 1180 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31); 1181 current->thread.fpu.fcr31 &= ~res; 1182 1183 /* 1184 * this is a tricky issue - lose_fpu() uses LL/SC atomics 1185 * if FPU is owned and effectively cancels user level LL/SC. 1186 * So, it could be logical to don't restore FPU ownership here. 1187 * But the sequence of multiple FPU instructions is much much 1188 * more often than LL-FPU-SC and I prefer loop here until 1189 * next scheduler cycle cancels FPU ownership 1190 */ 1191 own_fpu(1); /* Restore FPU state. */ 1192 1193 if (err) 1194 current->thread.cp0_baduaddr = (unsigned long)fault_addr; 1195 1196 MIPS_R2_STATS(fpus); 1197 1198 break; 1199 1200 case lwl_op: 1201 rt = regs->regs[MIPSInst_RT(inst)]; 1202 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1203 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1204 current->thread.cp0_baduaddr = vaddr; 1205 err = SIGSEGV; 1206 break; 1207 } 1208 __asm__ __volatile__( 1209 " .set push\n" 1210 " .set reorder\n" 1211 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1212 "1:" LB "%1, 0(%2)\n" 1213 INS "%0, %1, 24, 8\n" 1214 " andi %1, %2, 0x3\n" 1215 " beq $0, %1, 9f\n" 1216 ADDIU "%2, %2, -1\n" 1217 "2:" LB "%1, 0(%2)\n" 1218 INS "%0, %1, 16, 8\n" 1219 " andi %1, %2, 0x3\n" 1220 " beq $0, %1, 9f\n" 1221 ADDIU "%2, %2, -1\n" 1222 "3:" LB "%1, 0(%2)\n" 1223 INS "%0, %1, 8, 8\n" 1224 " andi %1, %2, 0x3\n" 1225 " beq $0, %1, 9f\n" 1226 ADDIU "%2, %2, -1\n" 1227 "4:" LB "%1, 0(%2)\n" 1228 INS "%0, %1, 0, 8\n" 1229 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1230 "1:" LB "%1, 0(%2)\n" 1231 INS "%0, %1, 24, 8\n" 1232 ADDIU "%2, %2, 1\n" 1233 " andi %1, %2, 0x3\n" 1234 " beq $0, %1, 9f\n" 1235 "2:" LB "%1, 0(%2)\n" 1236 INS "%0, %1, 16, 8\n" 1237 ADDIU "%2, %2, 1\n" 1238 " andi %1, %2, 0x3\n" 1239 " beq $0, %1, 9f\n" 1240 "3:" LB "%1, 0(%2)\n" 1241 INS "%0, %1, 8, 8\n" 1242 ADDIU "%2, %2, 1\n" 1243 " andi %1, %2, 0x3\n" 1244 " beq $0, %1, 9f\n" 1245 "4:" LB "%1, 0(%2)\n" 1246 INS "%0, %1, 0, 8\n" 1247 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1248 "9: sll %0, %0, 0\n" 1249 "10:\n" 1250 " .insn\n" 1251 " .section .fixup,\"ax\"\n" 1252 "8: li %3,%4\n" 1253 " j 10b\n" 1254 " .previous\n" 1255 " .section __ex_table,\"a\"\n" 1256 STR(PTR) " 1b,8b\n" 1257 STR(PTR) " 2b,8b\n" 1258 STR(PTR) " 3b,8b\n" 1259 STR(PTR) " 4b,8b\n" 1260 " .previous\n" 1261 " .set pop\n" 1262 : "+&r"(rt), "=&r"(rs), 1263 "+&r"(vaddr), "+&r"(err) 1264 : "i"(SIGSEGV)); 1265 1266 if (MIPSInst_RT(inst) && !err) 1267 regs->regs[MIPSInst_RT(inst)] = rt; 1268 1269 MIPS_R2_STATS(loads); 1270 1271 break; 1272 1273 case lwr_op: 1274 rt = regs->regs[MIPSInst_RT(inst)]; 1275 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1276 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1277 current->thread.cp0_baduaddr = vaddr; 1278 err = SIGSEGV; 1279 break; 1280 } 1281 __asm__ __volatile__( 1282 " .set push\n" 1283 " .set reorder\n" 1284 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1285 "1:" LB "%1, 0(%2)\n" 1286 INS "%0, %1, 0, 8\n" 1287 ADDIU "%2, %2, 1\n" 1288 " andi %1, %2, 0x3\n" 1289 " beq $0, %1, 9f\n" 1290 "2:" LB "%1, 0(%2)\n" 1291 INS "%0, %1, 8, 8\n" 1292 ADDIU "%2, %2, 1\n" 1293 " andi %1, %2, 0x3\n" 1294 " beq $0, %1, 9f\n" 1295 "3:" LB "%1, 0(%2)\n" 1296 INS "%0, %1, 16, 8\n" 1297 ADDIU "%2, %2, 1\n" 1298 " andi %1, %2, 0x3\n" 1299 " beq $0, %1, 9f\n" 1300 "4:" LB "%1, 0(%2)\n" 1301 INS "%0, %1, 24, 8\n" 1302 " sll %0, %0, 0\n" 1303 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1304 "1:" LB "%1, 0(%2)\n" 1305 INS "%0, %1, 0, 8\n" 1306 " andi %1, %2, 0x3\n" 1307 " beq $0, %1, 9f\n" 1308 ADDIU "%2, %2, -1\n" 1309 "2:" LB "%1, 0(%2)\n" 1310 INS "%0, %1, 8, 8\n" 1311 " andi %1, %2, 0x3\n" 1312 " beq $0, %1, 9f\n" 1313 ADDIU "%2, %2, -1\n" 1314 "3:" LB "%1, 0(%2)\n" 1315 INS "%0, %1, 16, 8\n" 1316 " andi %1, %2, 0x3\n" 1317 " beq $0, %1, 9f\n" 1318 ADDIU "%2, %2, -1\n" 1319 "4:" LB "%1, 0(%2)\n" 1320 INS "%0, %1, 24, 8\n" 1321 " sll %0, %0, 0\n" 1322 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1323 "9:\n" 1324 "10:\n" 1325 " .insn\n" 1326 " .section .fixup,\"ax\"\n" 1327 "8: li %3,%4\n" 1328 " j 10b\n" 1329 " .previous\n" 1330 " .section __ex_table,\"a\"\n" 1331 STR(PTR) " 1b,8b\n" 1332 STR(PTR) " 2b,8b\n" 1333 STR(PTR) " 3b,8b\n" 1334 STR(PTR) " 4b,8b\n" 1335 " .previous\n" 1336 " .set pop\n" 1337 : "+&r"(rt), "=&r"(rs), 1338 "+&r"(vaddr), "+&r"(err) 1339 : "i"(SIGSEGV)); 1340 if (MIPSInst_RT(inst) && !err) 1341 regs->regs[MIPSInst_RT(inst)] = rt; 1342 1343 MIPS_R2_STATS(loads); 1344 1345 break; 1346 1347 case swl_op: 1348 rt = regs->regs[MIPSInst_RT(inst)]; 1349 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1350 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 1351 current->thread.cp0_baduaddr = vaddr; 1352 err = SIGSEGV; 1353 break; 1354 } 1355 __asm__ __volatile__( 1356 " .set push\n" 1357 " .set reorder\n" 1358 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1359 EXT "%1, %0, 24, 8\n" 1360 "1:" SB "%1, 0(%2)\n" 1361 " andi %1, %2, 0x3\n" 1362 " beq $0, %1, 9f\n" 1363 ADDIU "%2, %2, -1\n" 1364 EXT "%1, %0, 16, 8\n" 1365 "2:" SB "%1, 0(%2)\n" 1366 " andi %1, %2, 0x3\n" 1367 " beq $0, %1, 9f\n" 1368 ADDIU "%2, %2, -1\n" 1369 EXT "%1, %0, 8, 8\n" 1370 "3:" SB "%1, 0(%2)\n" 1371 " andi %1, %2, 0x3\n" 1372 " beq $0, %1, 9f\n" 1373 ADDIU "%2, %2, -1\n" 1374 EXT "%1, %0, 0, 8\n" 1375 "4:" SB "%1, 0(%2)\n" 1376 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1377 EXT "%1, %0, 24, 8\n" 1378 "1:" SB "%1, 0(%2)\n" 1379 ADDIU "%2, %2, 1\n" 1380 " andi %1, %2, 0x3\n" 1381 " beq $0, %1, 9f\n" 1382 EXT "%1, %0, 16, 8\n" 1383 "2:" SB "%1, 0(%2)\n" 1384 ADDIU "%2, %2, 1\n" 1385 " andi %1, %2, 0x3\n" 1386 " beq $0, %1, 9f\n" 1387 EXT "%1, %0, 8, 8\n" 1388 "3:" SB "%1, 0(%2)\n" 1389 ADDIU "%2, %2, 1\n" 1390 " andi %1, %2, 0x3\n" 1391 " beq $0, %1, 9f\n" 1392 EXT "%1, %0, 0, 8\n" 1393 "4:" SB "%1, 0(%2)\n" 1394 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1395 "9:\n" 1396 " .insn\n" 1397 " .section .fixup,\"ax\"\n" 1398 "8: li %3,%4\n" 1399 " j 9b\n" 1400 " .previous\n" 1401 " .section __ex_table,\"a\"\n" 1402 STR(PTR) " 1b,8b\n" 1403 STR(PTR) " 2b,8b\n" 1404 STR(PTR) " 3b,8b\n" 1405 STR(PTR) " 4b,8b\n" 1406 " .previous\n" 1407 " .set pop\n" 1408 : "+&r"(rt), "=&r"(rs), 1409 "+&r"(vaddr), "+&r"(err) 1410 : "i"(SIGSEGV) 1411 : "memory"); 1412 1413 MIPS_R2_STATS(stores); 1414 1415 break; 1416 1417 case swr_op: 1418 rt = regs->regs[MIPSInst_RT(inst)]; 1419 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1420 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 1421 current->thread.cp0_baduaddr = vaddr; 1422 err = SIGSEGV; 1423 break; 1424 } 1425 __asm__ __volatile__( 1426 " .set push\n" 1427 " .set reorder\n" 1428 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1429 EXT "%1, %0, 0, 8\n" 1430 "1:" SB "%1, 0(%2)\n" 1431 ADDIU "%2, %2, 1\n" 1432 " andi %1, %2, 0x3\n" 1433 " beq $0, %1, 9f\n" 1434 EXT "%1, %0, 8, 8\n" 1435 "2:" SB "%1, 0(%2)\n" 1436 ADDIU "%2, %2, 1\n" 1437 " andi %1, %2, 0x3\n" 1438 " beq $0, %1, 9f\n" 1439 EXT "%1, %0, 16, 8\n" 1440 "3:" SB "%1, 0(%2)\n" 1441 ADDIU "%2, %2, 1\n" 1442 " andi %1, %2, 0x3\n" 1443 " beq $0, %1, 9f\n" 1444 EXT "%1, %0, 24, 8\n" 1445 "4:" SB "%1, 0(%2)\n" 1446 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1447 EXT "%1, %0, 0, 8\n" 1448 "1:" SB "%1, 0(%2)\n" 1449 " andi %1, %2, 0x3\n" 1450 " beq $0, %1, 9f\n" 1451 ADDIU "%2, %2, -1\n" 1452 EXT "%1, %0, 8, 8\n" 1453 "2:" SB "%1, 0(%2)\n" 1454 " andi %1, %2, 0x3\n" 1455 " beq $0, %1, 9f\n" 1456 ADDIU "%2, %2, -1\n" 1457 EXT "%1, %0, 16, 8\n" 1458 "3:" SB "%1, 0(%2)\n" 1459 " andi %1, %2, 0x3\n" 1460 " beq $0, %1, 9f\n" 1461 ADDIU "%2, %2, -1\n" 1462 EXT "%1, %0, 24, 8\n" 1463 "4:" SB "%1, 0(%2)\n" 1464 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1465 "9:\n" 1466 " .insn\n" 1467 " .section .fixup,\"ax\"\n" 1468 "8: li %3,%4\n" 1469 " j 9b\n" 1470 " .previous\n" 1471 " .section __ex_table,\"a\"\n" 1472 STR(PTR) " 1b,8b\n" 1473 STR(PTR) " 2b,8b\n" 1474 STR(PTR) " 3b,8b\n" 1475 STR(PTR) " 4b,8b\n" 1476 " .previous\n" 1477 " .set pop\n" 1478 : "+&r"(rt), "=&r"(rs), 1479 "+&r"(vaddr), "+&r"(err) 1480 : "i"(SIGSEGV) 1481 : "memory"); 1482 1483 MIPS_R2_STATS(stores); 1484 1485 break; 1486 1487 case ldl_op: 1488 if (IS_ENABLED(CONFIG_32BIT)) { 1489 err = SIGILL; 1490 break; 1491 } 1492 1493 rt = regs->regs[MIPSInst_RT(inst)]; 1494 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1495 if (!access_ok(VERIFY_READ, vaddr, 8)) { 1496 current->thread.cp0_baduaddr = vaddr; 1497 err = SIGSEGV; 1498 break; 1499 } 1500 __asm__ __volatile__( 1501 " .set push\n" 1502 " .set reorder\n" 1503 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1504 "1: lb %1, 0(%2)\n" 1505 " dinsu %0, %1, 56, 8\n" 1506 " andi %1, %2, 0x7\n" 1507 " beq $0, %1, 9f\n" 1508 " daddiu %2, %2, -1\n" 1509 "2: lb %1, 0(%2)\n" 1510 " dinsu %0, %1, 48, 8\n" 1511 " andi %1, %2, 0x7\n" 1512 " beq $0, %1, 9f\n" 1513 " daddiu %2, %2, -1\n" 1514 "3: lb %1, 0(%2)\n" 1515 " dinsu %0, %1, 40, 8\n" 1516 " andi %1, %2, 0x7\n" 1517 " beq $0, %1, 9f\n" 1518 " daddiu %2, %2, -1\n" 1519 "4: lb %1, 0(%2)\n" 1520 " dinsu %0, %1, 32, 8\n" 1521 " andi %1, %2, 0x7\n" 1522 " beq $0, %1, 9f\n" 1523 " daddiu %2, %2, -1\n" 1524 "5: lb %1, 0(%2)\n" 1525 " dins %0, %1, 24, 8\n" 1526 " andi %1, %2, 0x7\n" 1527 " beq $0, %1, 9f\n" 1528 " daddiu %2, %2, -1\n" 1529 "6: lb %1, 0(%2)\n" 1530 " dins %0, %1, 16, 8\n" 1531 " andi %1, %2, 0x7\n" 1532 " beq $0, %1, 9f\n" 1533 " daddiu %2, %2, -1\n" 1534 "7: lb %1, 0(%2)\n" 1535 " dins %0, %1, 8, 8\n" 1536 " andi %1, %2, 0x7\n" 1537 " beq $0, %1, 9f\n" 1538 " daddiu %2, %2, -1\n" 1539 "0: lb %1, 0(%2)\n" 1540 " dins %0, %1, 0, 8\n" 1541 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1542 "1: lb %1, 0(%2)\n" 1543 " dinsu %0, %1, 56, 8\n" 1544 " daddiu %2, %2, 1\n" 1545 " andi %1, %2, 0x7\n" 1546 " beq $0, %1, 9f\n" 1547 "2: lb %1, 0(%2)\n" 1548 " dinsu %0, %1, 48, 8\n" 1549 " daddiu %2, %2, 1\n" 1550 " andi %1, %2, 0x7\n" 1551 " beq $0, %1, 9f\n" 1552 "3: lb %1, 0(%2)\n" 1553 " dinsu %0, %1, 40, 8\n" 1554 " daddiu %2, %2, 1\n" 1555 " andi %1, %2, 0x7\n" 1556 " beq $0, %1, 9f\n" 1557 "4: lb %1, 0(%2)\n" 1558 " dinsu %0, %1, 32, 8\n" 1559 " daddiu %2, %2, 1\n" 1560 " andi %1, %2, 0x7\n" 1561 " beq $0, %1, 9f\n" 1562 "5: lb %1, 0(%2)\n" 1563 " dins %0, %1, 24, 8\n" 1564 " daddiu %2, %2, 1\n" 1565 " andi %1, %2, 0x7\n" 1566 " beq $0, %1, 9f\n" 1567 "6: lb %1, 0(%2)\n" 1568 " dins %0, %1, 16, 8\n" 1569 " daddiu %2, %2, 1\n" 1570 " andi %1, %2, 0x7\n" 1571 " beq $0, %1, 9f\n" 1572 "7: lb %1, 0(%2)\n" 1573 " dins %0, %1, 8, 8\n" 1574 " daddiu %2, %2, 1\n" 1575 " andi %1, %2, 0x7\n" 1576 " beq $0, %1, 9f\n" 1577 "0: lb %1, 0(%2)\n" 1578 " dins %0, %1, 0, 8\n" 1579 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1580 "9:\n" 1581 " .insn\n" 1582 " .section .fixup,\"ax\"\n" 1583 "8: li %3,%4\n" 1584 " j 9b\n" 1585 " .previous\n" 1586 " .section __ex_table,\"a\"\n" 1587 STR(PTR) " 1b,8b\n" 1588 STR(PTR) " 2b,8b\n" 1589 STR(PTR) " 3b,8b\n" 1590 STR(PTR) " 4b,8b\n" 1591 STR(PTR) " 5b,8b\n" 1592 STR(PTR) " 6b,8b\n" 1593 STR(PTR) " 7b,8b\n" 1594 STR(PTR) " 0b,8b\n" 1595 " .previous\n" 1596 " .set pop\n" 1597 : "+&r"(rt), "=&r"(rs), 1598 "+&r"(vaddr), "+&r"(err) 1599 : "i"(SIGSEGV)); 1600 if (MIPSInst_RT(inst) && !err) 1601 regs->regs[MIPSInst_RT(inst)] = rt; 1602 1603 MIPS_R2_STATS(loads); 1604 break; 1605 1606 case ldr_op: 1607 if (IS_ENABLED(CONFIG_32BIT)) { 1608 err = SIGILL; 1609 break; 1610 } 1611 1612 rt = regs->regs[MIPSInst_RT(inst)]; 1613 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1614 if (!access_ok(VERIFY_READ, vaddr, 8)) { 1615 current->thread.cp0_baduaddr = vaddr; 1616 err = SIGSEGV; 1617 break; 1618 } 1619 __asm__ __volatile__( 1620 " .set push\n" 1621 " .set reorder\n" 1622 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1623 "1: lb %1, 0(%2)\n" 1624 " dins %0, %1, 0, 8\n" 1625 " daddiu %2, %2, 1\n" 1626 " andi %1, %2, 0x7\n" 1627 " beq $0, %1, 9f\n" 1628 "2: lb %1, 0(%2)\n" 1629 " dins %0, %1, 8, 8\n" 1630 " daddiu %2, %2, 1\n" 1631 " andi %1, %2, 0x7\n" 1632 " beq $0, %1, 9f\n" 1633 "3: lb %1, 0(%2)\n" 1634 " dins %0, %1, 16, 8\n" 1635 " daddiu %2, %2, 1\n" 1636 " andi %1, %2, 0x7\n" 1637 " beq $0, %1, 9f\n" 1638 "4: lb %1, 0(%2)\n" 1639 " dins %0, %1, 24, 8\n" 1640 " daddiu %2, %2, 1\n" 1641 " andi %1, %2, 0x7\n" 1642 " beq $0, %1, 9f\n" 1643 "5: lb %1, 0(%2)\n" 1644 " dinsu %0, %1, 32, 8\n" 1645 " daddiu %2, %2, 1\n" 1646 " andi %1, %2, 0x7\n" 1647 " beq $0, %1, 9f\n" 1648 "6: lb %1, 0(%2)\n" 1649 " dinsu %0, %1, 40, 8\n" 1650 " daddiu %2, %2, 1\n" 1651 " andi %1, %2, 0x7\n" 1652 " beq $0, %1, 9f\n" 1653 "7: lb %1, 0(%2)\n" 1654 " dinsu %0, %1, 48, 8\n" 1655 " daddiu %2, %2, 1\n" 1656 " andi %1, %2, 0x7\n" 1657 " beq $0, %1, 9f\n" 1658 "0: lb %1, 0(%2)\n" 1659 " dinsu %0, %1, 56, 8\n" 1660 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1661 "1: lb %1, 0(%2)\n" 1662 " dins %0, %1, 0, 8\n" 1663 " andi %1, %2, 0x7\n" 1664 " beq $0, %1, 9f\n" 1665 " daddiu %2, %2, -1\n" 1666 "2: lb %1, 0(%2)\n" 1667 " dins %0, %1, 8, 8\n" 1668 " andi %1, %2, 0x7\n" 1669 " beq $0, %1, 9f\n" 1670 " daddiu %2, %2, -1\n" 1671 "3: lb %1, 0(%2)\n" 1672 " dins %0, %1, 16, 8\n" 1673 " andi %1, %2, 0x7\n" 1674 " beq $0, %1, 9f\n" 1675 " daddiu %2, %2, -1\n" 1676 "4: lb %1, 0(%2)\n" 1677 " dins %0, %1, 24, 8\n" 1678 " andi %1, %2, 0x7\n" 1679 " beq $0, %1, 9f\n" 1680 " daddiu %2, %2, -1\n" 1681 "5: lb %1, 0(%2)\n" 1682 " dinsu %0, %1, 32, 8\n" 1683 " andi %1, %2, 0x7\n" 1684 " beq $0, %1, 9f\n" 1685 " daddiu %2, %2, -1\n" 1686 "6: lb %1, 0(%2)\n" 1687 " dinsu %0, %1, 40, 8\n" 1688 " andi %1, %2, 0x7\n" 1689 " beq $0, %1, 9f\n" 1690 " daddiu %2, %2, -1\n" 1691 "7: lb %1, 0(%2)\n" 1692 " dinsu %0, %1, 48, 8\n" 1693 " andi %1, %2, 0x7\n" 1694 " beq $0, %1, 9f\n" 1695 " daddiu %2, %2, -1\n" 1696 "0: lb %1, 0(%2)\n" 1697 " dinsu %0, %1, 56, 8\n" 1698 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1699 "9:\n" 1700 " .insn\n" 1701 " .section .fixup,\"ax\"\n" 1702 "8: li %3,%4\n" 1703 " j 9b\n" 1704 " .previous\n" 1705 " .section __ex_table,\"a\"\n" 1706 STR(PTR) " 1b,8b\n" 1707 STR(PTR) " 2b,8b\n" 1708 STR(PTR) " 3b,8b\n" 1709 STR(PTR) " 4b,8b\n" 1710 STR(PTR) " 5b,8b\n" 1711 STR(PTR) " 6b,8b\n" 1712 STR(PTR) " 7b,8b\n" 1713 STR(PTR) " 0b,8b\n" 1714 " .previous\n" 1715 " .set pop\n" 1716 : "+&r"(rt), "=&r"(rs), 1717 "+&r"(vaddr), "+&r"(err) 1718 : "i"(SIGSEGV)); 1719 if (MIPSInst_RT(inst) && !err) 1720 regs->regs[MIPSInst_RT(inst)] = rt; 1721 1722 MIPS_R2_STATS(loads); 1723 break; 1724 1725 case sdl_op: 1726 if (IS_ENABLED(CONFIG_32BIT)) { 1727 err = SIGILL; 1728 break; 1729 } 1730 1731 rt = regs->regs[MIPSInst_RT(inst)]; 1732 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1733 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 1734 current->thread.cp0_baduaddr = vaddr; 1735 err = SIGSEGV; 1736 break; 1737 } 1738 __asm__ __volatile__( 1739 " .set push\n" 1740 " .set reorder\n" 1741 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1742 " dextu %1, %0, 56, 8\n" 1743 "1: sb %1, 0(%2)\n" 1744 " andi %1, %2, 0x7\n" 1745 " beq $0, %1, 9f\n" 1746 " daddiu %2, %2, -1\n" 1747 " dextu %1, %0, 48, 8\n" 1748 "2: sb %1, 0(%2)\n" 1749 " andi %1, %2, 0x7\n" 1750 " beq $0, %1, 9f\n" 1751 " daddiu %2, %2, -1\n" 1752 " dextu %1, %0, 40, 8\n" 1753 "3: sb %1, 0(%2)\n" 1754 " andi %1, %2, 0x7\n" 1755 " beq $0, %1, 9f\n" 1756 " daddiu %2, %2, -1\n" 1757 " dextu %1, %0, 32, 8\n" 1758 "4: sb %1, 0(%2)\n" 1759 " andi %1, %2, 0x7\n" 1760 " beq $0, %1, 9f\n" 1761 " daddiu %2, %2, -1\n" 1762 " dext %1, %0, 24, 8\n" 1763 "5: sb %1, 0(%2)\n" 1764 " andi %1, %2, 0x7\n" 1765 " beq $0, %1, 9f\n" 1766 " daddiu %2, %2, -1\n" 1767 " dext %1, %0, 16, 8\n" 1768 "6: sb %1, 0(%2)\n" 1769 " andi %1, %2, 0x7\n" 1770 " beq $0, %1, 9f\n" 1771 " daddiu %2, %2, -1\n" 1772 " dext %1, %0, 8, 8\n" 1773 "7: sb %1, 0(%2)\n" 1774 " andi %1, %2, 0x7\n" 1775 " beq $0, %1, 9f\n" 1776 " daddiu %2, %2, -1\n" 1777 " dext %1, %0, 0, 8\n" 1778 "0: sb %1, 0(%2)\n" 1779 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1780 " dextu %1, %0, 56, 8\n" 1781 "1: sb %1, 0(%2)\n" 1782 " daddiu %2, %2, 1\n" 1783 " andi %1, %2, 0x7\n" 1784 " beq $0, %1, 9f\n" 1785 " dextu %1, %0, 48, 8\n" 1786 "2: sb %1, 0(%2)\n" 1787 " daddiu %2, %2, 1\n" 1788 " andi %1, %2, 0x7\n" 1789 " beq $0, %1, 9f\n" 1790 " dextu %1, %0, 40, 8\n" 1791 "3: sb %1, 0(%2)\n" 1792 " daddiu %2, %2, 1\n" 1793 " andi %1, %2, 0x7\n" 1794 " beq $0, %1, 9f\n" 1795 " dextu %1, %0, 32, 8\n" 1796 "4: sb %1, 0(%2)\n" 1797 " daddiu %2, %2, 1\n" 1798 " andi %1, %2, 0x7\n" 1799 " beq $0, %1, 9f\n" 1800 " dext %1, %0, 24, 8\n" 1801 "5: sb %1, 0(%2)\n" 1802 " daddiu %2, %2, 1\n" 1803 " andi %1, %2, 0x7\n" 1804 " beq $0, %1, 9f\n" 1805 " dext %1, %0, 16, 8\n" 1806 "6: sb %1, 0(%2)\n" 1807 " daddiu %2, %2, 1\n" 1808 " andi %1, %2, 0x7\n" 1809 " beq $0, %1, 9f\n" 1810 " dext %1, %0, 8, 8\n" 1811 "7: sb %1, 0(%2)\n" 1812 " daddiu %2, %2, 1\n" 1813 " andi %1, %2, 0x7\n" 1814 " beq $0, %1, 9f\n" 1815 " dext %1, %0, 0, 8\n" 1816 "0: sb %1, 0(%2)\n" 1817 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1818 "9:\n" 1819 " .insn\n" 1820 " .section .fixup,\"ax\"\n" 1821 "8: li %3,%4\n" 1822 " j 9b\n" 1823 " .previous\n" 1824 " .section __ex_table,\"a\"\n" 1825 STR(PTR) " 1b,8b\n" 1826 STR(PTR) " 2b,8b\n" 1827 STR(PTR) " 3b,8b\n" 1828 STR(PTR) " 4b,8b\n" 1829 STR(PTR) " 5b,8b\n" 1830 STR(PTR) " 6b,8b\n" 1831 STR(PTR) " 7b,8b\n" 1832 STR(PTR) " 0b,8b\n" 1833 " .previous\n" 1834 " .set pop\n" 1835 : "+&r"(rt), "=&r"(rs), 1836 "+&r"(vaddr), "+&r"(err) 1837 : "i"(SIGSEGV) 1838 : "memory"); 1839 1840 MIPS_R2_STATS(stores); 1841 break; 1842 1843 case sdr_op: 1844 if (IS_ENABLED(CONFIG_32BIT)) { 1845 err = SIGILL; 1846 break; 1847 } 1848 1849 rt = regs->regs[MIPSInst_RT(inst)]; 1850 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1851 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 1852 current->thread.cp0_baduaddr = vaddr; 1853 err = SIGSEGV; 1854 break; 1855 } 1856 __asm__ __volatile__( 1857 " .set push\n" 1858 " .set reorder\n" 1859 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1860 " dext %1, %0, 0, 8\n" 1861 "1: sb %1, 0(%2)\n" 1862 " daddiu %2, %2, 1\n" 1863 " andi %1, %2, 0x7\n" 1864 " beq $0, %1, 9f\n" 1865 " dext %1, %0, 8, 8\n" 1866 "2: sb %1, 0(%2)\n" 1867 " daddiu %2, %2, 1\n" 1868 " andi %1, %2, 0x7\n" 1869 " beq $0, %1, 9f\n" 1870 " dext %1, %0, 16, 8\n" 1871 "3: sb %1, 0(%2)\n" 1872 " daddiu %2, %2, 1\n" 1873 " andi %1, %2, 0x7\n" 1874 " beq $0, %1, 9f\n" 1875 " dext %1, %0, 24, 8\n" 1876 "4: sb %1, 0(%2)\n" 1877 " daddiu %2, %2, 1\n" 1878 " andi %1, %2, 0x7\n" 1879 " beq $0, %1, 9f\n" 1880 " dextu %1, %0, 32, 8\n" 1881 "5: sb %1, 0(%2)\n" 1882 " daddiu %2, %2, 1\n" 1883 " andi %1, %2, 0x7\n" 1884 " beq $0, %1, 9f\n" 1885 " dextu %1, %0, 40, 8\n" 1886 "6: sb %1, 0(%2)\n" 1887 " daddiu %2, %2, 1\n" 1888 " andi %1, %2, 0x7\n" 1889 " beq $0, %1, 9f\n" 1890 " dextu %1, %0, 48, 8\n" 1891 "7: sb %1, 0(%2)\n" 1892 " daddiu %2, %2, 1\n" 1893 " andi %1, %2, 0x7\n" 1894 " beq $0, %1, 9f\n" 1895 " dextu %1, %0, 56, 8\n" 1896 "0: sb %1, 0(%2)\n" 1897 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1898 " dext %1, %0, 0, 8\n" 1899 "1: sb %1, 0(%2)\n" 1900 " andi %1, %2, 0x7\n" 1901 " beq $0, %1, 9f\n" 1902 " daddiu %2, %2, -1\n" 1903 " dext %1, %0, 8, 8\n" 1904 "2: sb %1, 0(%2)\n" 1905 " andi %1, %2, 0x7\n" 1906 " beq $0, %1, 9f\n" 1907 " daddiu %2, %2, -1\n" 1908 " dext %1, %0, 16, 8\n" 1909 "3: sb %1, 0(%2)\n" 1910 " andi %1, %2, 0x7\n" 1911 " beq $0, %1, 9f\n" 1912 " daddiu %2, %2, -1\n" 1913 " dext %1, %0, 24, 8\n" 1914 "4: sb %1, 0(%2)\n" 1915 " andi %1, %2, 0x7\n" 1916 " beq $0, %1, 9f\n" 1917 " daddiu %2, %2, -1\n" 1918 " dextu %1, %0, 32, 8\n" 1919 "5: sb %1, 0(%2)\n" 1920 " andi %1, %2, 0x7\n" 1921 " beq $0, %1, 9f\n" 1922 " daddiu %2, %2, -1\n" 1923 " dextu %1, %0, 40, 8\n" 1924 "6: sb %1, 0(%2)\n" 1925 " andi %1, %2, 0x7\n" 1926 " beq $0, %1, 9f\n" 1927 " daddiu %2, %2, -1\n" 1928 " dextu %1, %0, 48, 8\n" 1929 "7: sb %1, 0(%2)\n" 1930 " andi %1, %2, 0x7\n" 1931 " beq $0, %1, 9f\n" 1932 " daddiu %2, %2, -1\n" 1933 " dextu %1, %0, 56, 8\n" 1934 "0: sb %1, 0(%2)\n" 1935 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1936 "9:\n" 1937 " .insn\n" 1938 " .section .fixup,\"ax\"\n" 1939 "8: li %3,%4\n" 1940 " j 9b\n" 1941 " .previous\n" 1942 " .section __ex_table,\"a\"\n" 1943 STR(PTR) " 1b,8b\n" 1944 STR(PTR) " 2b,8b\n" 1945 STR(PTR) " 3b,8b\n" 1946 STR(PTR) " 4b,8b\n" 1947 STR(PTR) " 5b,8b\n" 1948 STR(PTR) " 6b,8b\n" 1949 STR(PTR) " 7b,8b\n" 1950 STR(PTR) " 0b,8b\n" 1951 " .previous\n" 1952 " .set pop\n" 1953 : "+&r"(rt), "=&r"(rs), 1954 "+&r"(vaddr), "+&r"(err) 1955 : "i"(SIGSEGV) 1956 : "memory"); 1957 1958 MIPS_R2_STATS(stores); 1959 1960 break; 1961 case ll_op: 1962 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1963 if (vaddr & 0x3) { 1964 current->thread.cp0_baduaddr = vaddr; 1965 err = SIGBUS; 1966 break; 1967 } 1968 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1969 current->thread.cp0_baduaddr = vaddr; 1970 err = SIGBUS; 1971 break; 1972 } 1973 1974 if (!cpu_has_rw_llb) { 1975 /* 1976 * An LL/SC block can't be safely emulated without 1977 * a Config5/LLB availability. So it's probably time to 1978 * kill our process before things get any worse. This is 1979 * because Config5/LLB allows us to use ERETNC so that 1980 * the LLAddr/LLB bit is not cleared when we return from 1981 * an exception. MIPS R2 LL/SC instructions trap with an 1982 * RI exception so once we emulate them here, we return 1983 * back to userland with ERETNC. That preserves the 1984 * LLAddr/LLB so the subsequent SC instruction will 1985 * succeed preserving the atomic semantics of the LL/SC 1986 * block. Without that, there is no safe way to emulate 1987 * an LL/SC block in MIPSR2 userland. 1988 */ 1989 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 1990 err = SIGKILL; 1991 break; 1992 } 1993 1994 __asm__ __volatile__( 1995 "1:\n" 1996 "ll %0, 0(%2)\n" 1997 "2:\n" 1998 ".insn\n" 1999 ".section .fixup,\"ax\"\n" 2000 "3:\n" 2001 "li %1, %3\n" 2002 "j 2b\n" 2003 ".previous\n" 2004 ".section __ex_table,\"a\"\n" 2005 STR(PTR) " 1b,3b\n" 2006 ".previous\n" 2007 : "=&r"(res), "+&r"(err) 2008 : "r"(vaddr), "i"(SIGSEGV) 2009 : "memory"); 2010 2011 if (MIPSInst_RT(inst) && !err) 2012 regs->regs[MIPSInst_RT(inst)] = res; 2013 MIPS_R2_STATS(llsc); 2014 2015 break; 2016 2017 case sc_op: 2018 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2019 if (vaddr & 0x3) { 2020 current->thread.cp0_baduaddr = vaddr; 2021 err = SIGBUS; 2022 break; 2023 } 2024 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 2025 current->thread.cp0_baduaddr = vaddr; 2026 err = SIGBUS; 2027 break; 2028 } 2029 2030 if (!cpu_has_rw_llb) { 2031 /* 2032 * An LL/SC block can't be safely emulated without 2033 * a Config5/LLB availability. So it's probably time to 2034 * kill our process before things get any worse. This is 2035 * because Config5/LLB allows us to use ERETNC so that 2036 * the LLAddr/LLB bit is not cleared when we return from 2037 * an exception. MIPS R2 LL/SC instructions trap with an 2038 * RI exception so once we emulate them here, we return 2039 * back to userland with ERETNC. That preserves the 2040 * LLAddr/LLB so the subsequent SC instruction will 2041 * succeed preserving the atomic semantics of the LL/SC 2042 * block. Without that, there is no safe way to emulate 2043 * an LL/SC block in MIPSR2 userland. 2044 */ 2045 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2046 err = SIGKILL; 2047 break; 2048 } 2049 2050 res = regs->regs[MIPSInst_RT(inst)]; 2051 2052 __asm__ __volatile__( 2053 "1:\n" 2054 "sc %0, 0(%2)\n" 2055 "2:\n" 2056 ".insn\n" 2057 ".section .fixup,\"ax\"\n" 2058 "3:\n" 2059 "li %1, %3\n" 2060 "j 2b\n" 2061 ".previous\n" 2062 ".section __ex_table,\"a\"\n" 2063 STR(PTR) " 1b,3b\n" 2064 ".previous\n" 2065 : "+&r"(res), "+&r"(err) 2066 : "r"(vaddr), "i"(SIGSEGV)); 2067 2068 if (MIPSInst_RT(inst) && !err) 2069 regs->regs[MIPSInst_RT(inst)] = res; 2070 2071 MIPS_R2_STATS(llsc); 2072 2073 break; 2074 2075 case lld_op: 2076 if (IS_ENABLED(CONFIG_32BIT)) { 2077 err = SIGILL; 2078 break; 2079 } 2080 2081 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2082 if (vaddr & 0x7) { 2083 current->thread.cp0_baduaddr = vaddr; 2084 err = SIGBUS; 2085 break; 2086 } 2087 if (!access_ok(VERIFY_READ, vaddr, 8)) { 2088 current->thread.cp0_baduaddr = vaddr; 2089 err = SIGBUS; 2090 break; 2091 } 2092 2093 if (!cpu_has_rw_llb) { 2094 /* 2095 * An LL/SC block can't be safely emulated without 2096 * a Config5/LLB availability. So it's probably time to 2097 * kill our process before things get any worse. This is 2098 * because Config5/LLB allows us to use ERETNC so that 2099 * the LLAddr/LLB bit is not cleared when we return from 2100 * an exception. MIPS R2 LL/SC instructions trap with an 2101 * RI exception so once we emulate them here, we return 2102 * back to userland with ERETNC. That preserves the 2103 * LLAddr/LLB so the subsequent SC instruction will 2104 * succeed preserving the atomic semantics of the LL/SC 2105 * block. Without that, there is no safe way to emulate 2106 * an LL/SC block in MIPSR2 userland. 2107 */ 2108 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2109 err = SIGKILL; 2110 break; 2111 } 2112 2113 __asm__ __volatile__( 2114 "1:\n" 2115 "lld %0, 0(%2)\n" 2116 "2:\n" 2117 ".insn\n" 2118 ".section .fixup,\"ax\"\n" 2119 "3:\n" 2120 "li %1, %3\n" 2121 "j 2b\n" 2122 ".previous\n" 2123 ".section __ex_table,\"a\"\n" 2124 STR(PTR) " 1b,3b\n" 2125 ".previous\n" 2126 : "=&r"(res), "+&r"(err) 2127 : "r"(vaddr), "i"(SIGSEGV) 2128 : "memory"); 2129 if (MIPSInst_RT(inst) && !err) 2130 regs->regs[MIPSInst_RT(inst)] = res; 2131 2132 MIPS_R2_STATS(llsc); 2133 2134 break; 2135 2136 case scd_op: 2137 if (IS_ENABLED(CONFIG_32BIT)) { 2138 err = SIGILL; 2139 break; 2140 } 2141 2142 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2143 if (vaddr & 0x7) { 2144 current->thread.cp0_baduaddr = vaddr; 2145 err = SIGBUS; 2146 break; 2147 } 2148 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 2149 current->thread.cp0_baduaddr = vaddr; 2150 err = SIGBUS; 2151 break; 2152 } 2153 2154 if (!cpu_has_rw_llb) { 2155 /* 2156 * An LL/SC block can't be safely emulated without 2157 * a Config5/LLB availability. So it's probably time to 2158 * kill our process before things get any worse. This is 2159 * because Config5/LLB allows us to use ERETNC so that 2160 * the LLAddr/LLB bit is not cleared when we return from 2161 * an exception. MIPS R2 LL/SC instructions trap with an 2162 * RI exception so once we emulate them here, we return 2163 * back to userland with ERETNC. That preserves the 2164 * LLAddr/LLB so the subsequent SC instruction will 2165 * succeed preserving the atomic semantics of the LL/SC 2166 * block. Without that, there is no safe way to emulate 2167 * an LL/SC block in MIPSR2 userland. 2168 */ 2169 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2170 err = SIGKILL; 2171 break; 2172 } 2173 2174 res = regs->regs[MIPSInst_RT(inst)]; 2175 2176 __asm__ __volatile__( 2177 "1:\n" 2178 "scd %0, 0(%2)\n" 2179 "2:\n" 2180 ".insn\n" 2181 ".section .fixup,\"ax\"\n" 2182 "3:\n" 2183 "li %1, %3\n" 2184 "j 2b\n" 2185 ".previous\n" 2186 ".section __ex_table,\"a\"\n" 2187 STR(PTR) " 1b,3b\n" 2188 ".previous\n" 2189 : "+&r"(res), "+&r"(err) 2190 : "r"(vaddr), "i"(SIGSEGV)); 2191 2192 if (MIPSInst_RT(inst) && !err) 2193 regs->regs[MIPSInst_RT(inst)] = res; 2194 2195 MIPS_R2_STATS(llsc); 2196 2197 break; 2198 case pref_op: 2199 /* skip it */ 2200 break; 2201 default: 2202 err = SIGILL; 2203 } 2204 2205 /* 2206 * Let's not return to userland just yet. It's costly and 2207 * it's likely we have more R2 instructions to emulate 2208 */ 2209 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { 2210 regs->cp0_cause &= ~CAUSEF_BD; 2211 err = get_user(inst, (u32 __user *)regs->cp0_epc); 2212 if (!err) 2213 goto repeat; 2214 2215 if (err < 0) 2216 err = SIGSEGV; 2217 } 2218 2219 if (err && (err != SIGEMT)) { 2220 regs->regs[31] = r31; 2221 regs->cp0_epc = epc; 2222 } 2223 2224 /* Likely a MIPS R6 compatible instruction */ 2225 if (pass && (err == SIGILL)) 2226 err = 0; 2227 2228 return err; 2229 } 2230 2231 #ifdef CONFIG_DEBUG_FS 2232 2233 static int mipsr2_stats_show(struct seq_file *s, void *unused) 2234 { 2235 2236 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); 2237 seq_printf(s, "movs\t\t%ld\t%ld\n", 2238 (unsigned long)__this_cpu_read(mipsr2emustats.movs), 2239 (unsigned long)__this_cpu_read(mipsr2bdemustats.movs)); 2240 seq_printf(s, "hilo\t\t%ld\t%ld\n", 2241 (unsigned long)__this_cpu_read(mipsr2emustats.hilo), 2242 (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo)); 2243 seq_printf(s, "muls\t\t%ld\t%ld\n", 2244 (unsigned long)__this_cpu_read(mipsr2emustats.muls), 2245 (unsigned long)__this_cpu_read(mipsr2bdemustats.muls)); 2246 seq_printf(s, "divs\t\t%ld\t%ld\n", 2247 (unsigned long)__this_cpu_read(mipsr2emustats.divs), 2248 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); 2249 seq_printf(s, "dsps\t\t%ld\t%ld\n", 2250 (unsigned long)__this_cpu_read(mipsr2emustats.dsps), 2251 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps)); 2252 seq_printf(s, "bops\t\t%ld\t%ld\n", 2253 (unsigned long)__this_cpu_read(mipsr2emustats.bops), 2254 (unsigned long)__this_cpu_read(mipsr2bdemustats.bops)); 2255 seq_printf(s, "traps\t\t%ld\t%ld\n", 2256 (unsigned long)__this_cpu_read(mipsr2emustats.traps), 2257 (unsigned long)__this_cpu_read(mipsr2bdemustats.traps)); 2258 seq_printf(s, "fpus\t\t%ld\t%ld\n", 2259 (unsigned long)__this_cpu_read(mipsr2emustats.fpus), 2260 (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus)); 2261 seq_printf(s, "loads\t\t%ld\t%ld\n", 2262 (unsigned long)__this_cpu_read(mipsr2emustats.loads), 2263 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); 2264 seq_printf(s, "stores\t\t%ld\t%ld\n", 2265 (unsigned long)__this_cpu_read(mipsr2emustats.stores), 2266 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); 2267 seq_printf(s, "llsc\t\t%ld\t%ld\n", 2268 (unsigned long)__this_cpu_read(mipsr2emustats.llsc), 2269 (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc)); 2270 seq_printf(s, "dsemul\t\t%ld\t%ld\n", 2271 (unsigned long)__this_cpu_read(mipsr2emustats.dsemul), 2272 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul)); 2273 seq_printf(s, "jr\t\t%ld\n", 2274 (unsigned long)__this_cpu_read(mipsr2bremustats.jrs)); 2275 seq_printf(s, "bltzl\t\t%ld\n", 2276 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl)); 2277 seq_printf(s, "bgezl\t\t%ld\n", 2278 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl)); 2279 seq_printf(s, "bltzll\t\t%ld\n", 2280 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll)); 2281 seq_printf(s, "bgezll\t\t%ld\n", 2282 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll)); 2283 seq_printf(s, "bltzal\t\t%ld\n", 2284 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal)); 2285 seq_printf(s, "bgezal\t\t%ld\n", 2286 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal)); 2287 seq_printf(s, "beql\t\t%ld\n", 2288 (unsigned long)__this_cpu_read(mipsr2bremustats.beql)); 2289 seq_printf(s, "bnel\t\t%ld\n", 2290 (unsigned long)__this_cpu_read(mipsr2bremustats.bnel)); 2291 seq_printf(s, "blezl\t\t%ld\n", 2292 (unsigned long)__this_cpu_read(mipsr2bremustats.blezl)); 2293 seq_printf(s, "bgtzl\t\t%ld\n", 2294 (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl)); 2295 2296 return 0; 2297 } 2298 2299 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused) 2300 { 2301 mipsr2_stats_show(s, unused); 2302 2303 __this_cpu_write((mipsr2emustats).movs, 0); 2304 __this_cpu_write((mipsr2bdemustats).movs, 0); 2305 __this_cpu_write((mipsr2emustats).hilo, 0); 2306 __this_cpu_write((mipsr2bdemustats).hilo, 0); 2307 __this_cpu_write((mipsr2emustats).muls, 0); 2308 __this_cpu_write((mipsr2bdemustats).muls, 0); 2309 __this_cpu_write((mipsr2emustats).divs, 0); 2310 __this_cpu_write((mipsr2bdemustats).divs, 0); 2311 __this_cpu_write((mipsr2emustats).dsps, 0); 2312 __this_cpu_write((mipsr2bdemustats).dsps, 0); 2313 __this_cpu_write((mipsr2emustats).bops, 0); 2314 __this_cpu_write((mipsr2bdemustats).bops, 0); 2315 __this_cpu_write((mipsr2emustats).traps, 0); 2316 __this_cpu_write((mipsr2bdemustats).traps, 0); 2317 __this_cpu_write((mipsr2emustats).fpus, 0); 2318 __this_cpu_write((mipsr2bdemustats).fpus, 0); 2319 __this_cpu_write((mipsr2emustats).loads, 0); 2320 __this_cpu_write((mipsr2bdemustats).loads, 0); 2321 __this_cpu_write((mipsr2emustats).stores, 0); 2322 __this_cpu_write((mipsr2bdemustats).stores, 0); 2323 __this_cpu_write((mipsr2emustats).llsc, 0); 2324 __this_cpu_write((mipsr2bdemustats).llsc, 0); 2325 __this_cpu_write((mipsr2emustats).dsemul, 0); 2326 __this_cpu_write((mipsr2bdemustats).dsemul, 0); 2327 __this_cpu_write((mipsr2bremustats).jrs, 0); 2328 __this_cpu_write((mipsr2bremustats).bltzl, 0); 2329 __this_cpu_write((mipsr2bremustats).bgezl, 0); 2330 __this_cpu_write((mipsr2bremustats).bltzll, 0); 2331 __this_cpu_write((mipsr2bremustats).bgezll, 0); 2332 __this_cpu_write((mipsr2bremustats).bltzal, 0); 2333 __this_cpu_write((mipsr2bremustats).bgezal, 0); 2334 __this_cpu_write((mipsr2bremustats).beql, 0); 2335 __this_cpu_write((mipsr2bremustats).bnel, 0); 2336 __this_cpu_write((mipsr2bremustats).blezl, 0); 2337 __this_cpu_write((mipsr2bremustats).bgtzl, 0); 2338 2339 return 0; 2340 } 2341 2342 static int mipsr2_stats_open(struct inode *inode, struct file *file) 2343 { 2344 return single_open(file, mipsr2_stats_show, inode->i_private); 2345 } 2346 2347 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file) 2348 { 2349 return single_open(file, mipsr2_stats_clear_show, inode->i_private); 2350 } 2351 2352 static const struct file_operations mipsr2_emul_fops = { 2353 .open = mipsr2_stats_open, 2354 .read = seq_read, 2355 .llseek = seq_lseek, 2356 .release = single_release, 2357 }; 2358 2359 static const struct file_operations mipsr2_clear_fops = { 2360 .open = mipsr2_stats_clear_open, 2361 .read = seq_read, 2362 .llseek = seq_lseek, 2363 .release = single_release, 2364 }; 2365 2366 2367 static int __init mipsr2_init_debugfs(void) 2368 { 2369 struct dentry *mipsr2_emul; 2370 2371 if (!mips_debugfs_dir) 2372 return -ENODEV; 2373 2374 mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO, 2375 mips_debugfs_dir, NULL, 2376 &mipsr2_emul_fops); 2377 if (!mipsr2_emul) 2378 return -ENOMEM; 2379 2380 mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO, 2381 mips_debugfs_dir, NULL, 2382 &mipsr2_clear_fops); 2383 if (!mipsr2_emul) 2384 return -ENOMEM; 2385 2386 return 0; 2387 } 2388 2389 device_initcall(mipsr2_init_debugfs); 2390 2391 #endif /* CONFIG_DEBUG_FS */ 2392