1 /* 2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels 3 * Copyright (C) 2005 Mips Technologies, Inc 4 */ 5 6 #include <linux/device.h> 7 #include <linux/kernel.h> 8 #include <linux/sched.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/security.h> 12 13 #include <asm/cpu.h> 14 #include <asm/processor.h> 15 #include <asm/atomic.h> 16 #include <asm/system.h> 17 #include <asm/hardirq.h> 18 #include <asm/mmu_context.h> 19 #include <asm/smp.h> 20 #include <asm/mipsmtregs.h> 21 #include <asm/r4kcache.h> 22 #include <asm/cacheflush.h> 23 24 /* 25 * Dump new MIPS MT state for the core. Does not leave TCs halted. 26 * Takes an argument which taken to be a pre-call MVPControl value. 27 */ 28 29 void mips_mt_regdump(unsigned long mvpctl) 30 { 31 unsigned long flags; 32 unsigned long vpflags; 33 unsigned long mvpconf0; 34 int nvpe; 35 int ntc; 36 int i; 37 int tc; 38 unsigned long haltval; 39 unsigned long tcstatval; 40 #ifdef CONFIG_MIPS_MT_SMTC 41 void smtc_soft_dump(void); 42 #endif /* CONFIG_MIPT_MT_SMTC */ 43 44 local_irq_save(flags); 45 vpflags = dvpe(); 46 printk("=== MIPS MT State Dump ===\n"); 47 printk("-- Global State --\n"); 48 printk(" MVPControl Passed: %08lx\n", mvpctl); 49 printk(" MVPControl Read: %08lx\n", vpflags); 50 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0())); 51 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 52 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 53 printk("-- per-VPE State --\n"); 54 for (i = 0; i < nvpe; i++) { 55 for (tc = 0; tc < ntc; tc++) { 56 settc(tc); 57 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 58 printk(" VPE %d\n", i); 59 printk(" VPEControl : %08lx\n", 60 read_vpe_c0_vpecontrol()); 61 printk(" VPEConf0 : %08lx\n", 62 read_vpe_c0_vpeconf0()); 63 printk(" VPE%d.Status : %08lx\n", 64 i, read_vpe_c0_status()); 65 printk(" VPE%d.EPC : %08lx\n", 66 i, read_vpe_c0_epc()); 67 printk(" VPE%d.Cause : %08lx\n", 68 i, read_vpe_c0_cause()); 69 printk(" VPE%d.Config7 : %08lx\n", 70 i, read_vpe_c0_config7()); 71 break; /* Next VPE */ 72 } 73 } 74 } 75 printk("-- per-TC State --\n"); 76 for (tc = 0; tc < ntc; tc++) { 77 settc(tc); 78 if (read_tc_c0_tcbind() == read_c0_tcbind()) { 79 /* Are we dumping ourself? */ 80 haltval = 0; /* Then we're not halted, and mustn't be */ 81 tcstatval = flags; /* And pre-dump TCStatus is flags */ 82 printk(" TC %d (current TC with VPE EPC above)\n", tc); 83 } else { 84 haltval = read_tc_c0_tchalt(); 85 write_tc_c0_tchalt(1); 86 tcstatval = read_tc_c0_tcstatus(); 87 printk(" TC %d\n", tc); 88 } 89 printk(" TCStatus : %08lx\n", tcstatval); 90 printk(" TCBind : %08lx\n", read_tc_c0_tcbind()); 91 printk(" TCRestart : %08lx\n", read_tc_c0_tcrestart()); 92 printk(" TCHalt : %08lx\n", haltval); 93 printk(" TCContext : %08lx\n", read_tc_c0_tccontext()); 94 if (!haltval) 95 write_tc_c0_tchalt(0); 96 } 97 #ifdef CONFIG_MIPS_MT_SMTC 98 smtc_soft_dump(); 99 #endif /* CONFIG_MIPT_MT_SMTC */ 100 printk("===========================\n"); 101 evpe(vpflags); 102 local_irq_restore(flags); 103 } 104 105 static int mt_opt_norps = 0; 106 static int mt_opt_rpsctl = -1; 107 static int mt_opt_nblsu = -1; 108 static int mt_opt_forceconfig7 = 0; 109 static int mt_opt_config7 = -1; 110 111 static int __init rps_disable(char *s) 112 { 113 mt_opt_norps = 1; 114 return 1; 115 } 116 __setup("norps", rps_disable); 117 118 static int __init rpsctl_set(char *str) 119 { 120 get_option(&str, &mt_opt_rpsctl); 121 return 1; 122 } 123 __setup("rpsctl=", rpsctl_set); 124 125 static int __init nblsu_set(char *str) 126 { 127 get_option(&str, &mt_opt_nblsu); 128 return 1; 129 } 130 __setup("nblsu=", nblsu_set); 131 132 static int __init config7_set(char *str) 133 { 134 get_option(&str, &mt_opt_config7); 135 mt_opt_forceconfig7 = 1; 136 return 1; 137 } 138 __setup("config7=", config7_set); 139 140 /* Experimental cache flush control parameters that should go away some day */ 141 int mt_protiflush = 0; 142 int mt_protdflush = 0; 143 int mt_n_iflushes = 1; 144 int mt_n_dflushes = 1; 145 146 static int __init set_protiflush(char *s) 147 { 148 mt_protiflush = 1; 149 return 1; 150 } 151 __setup("protiflush", set_protiflush); 152 153 static int __init set_protdflush(char *s) 154 { 155 mt_protdflush = 1; 156 return 1; 157 } 158 __setup("protdflush", set_protdflush); 159 160 static int __init niflush(char *s) 161 { 162 get_option(&s, &mt_n_iflushes); 163 return 1; 164 } 165 __setup("niflush=", niflush); 166 167 static int __init ndflush(char *s) 168 { 169 get_option(&s, &mt_n_dflushes); 170 return 1; 171 } 172 __setup("ndflush=", ndflush); 173 174 static unsigned int itc_base = 0; 175 176 static int __init set_itc_base(char *str) 177 { 178 get_option(&str, &itc_base); 179 return 1; 180 } 181 182 __setup("itcbase=", set_itc_base); 183 184 void mips_mt_set_cpuoptions(void) 185 { 186 unsigned int oconfig7 = read_c0_config7(); 187 unsigned int nconfig7 = oconfig7; 188 189 if (mt_opt_norps) { 190 printk("\"norps\" option deprectated: use \"rpsctl=\"\n"); 191 } 192 if (mt_opt_rpsctl >= 0) { 193 printk("34K return prediction stack override set to %d.\n", 194 mt_opt_rpsctl); 195 if (mt_opt_rpsctl) 196 nconfig7 |= (1 << 2); 197 else 198 nconfig7 &= ~(1 << 2); 199 } 200 if (mt_opt_nblsu >= 0) { 201 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu); 202 if (mt_opt_nblsu) 203 nconfig7 |= (1 << 5); 204 else 205 nconfig7 &= ~(1 << 5); 206 } 207 if (mt_opt_forceconfig7) { 208 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7); 209 nconfig7 = mt_opt_config7; 210 } 211 if (oconfig7 != nconfig7) { 212 __asm__ __volatile("sync"); 213 write_c0_config7(nconfig7); 214 ehb (); 215 printk("Config7: 0x%08x\n", read_c0_config7()); 216 } 217 218 /* Report Cache management debug options */ 219 if (mt_protiflush) 220 printk("I-cache flushes single-threaded\n"); 221 if (mt_protdflush) 222 printk("D-cache flushes single-threaded\n"); 223 if (mt_n_iflushes != 1) 224 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes); 225 if (mt_n_dflushes != 1) 226 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes); 227 228 if (itc_base != 0) { 229 /* 230 * Configure ITC mapping. This code is very 231 * specific to the 34K core family, which uses 232 * a special mode bit ("ITC") in the ErrCtl 233 * register to enable access to ITC control 234 * registers via cache "tag" operations. 235 */ 236 unsigned long ectlval; 237 unsigned long itcblkgrn; 238 239 /* ErrCtl register is known as "ecc" to Linux */ 240 ectlval = read_c0_ecc(); 241 write_c0_ecc(ectlval | (0x1 << 26)); 242 ehb(); 243 #define INDEX_0 (0x80000000) 244 #define INDEX_8 (0x80000008) 245 /* Read "cache tag" for Dcache pseudo-index 8 */ 246 cache_op(Index_Load_Tag_D, INDEX_8); 247 ehb(); 248 itcblkgrn = read_c0_dtaglo(); 249 itcblkgrn &= 0xfffe0000; 250 /* Set for 128 byte pitch of ITC cells */ 251 itcblkgrn |= 0x00000c00; 252 /* Stage in Tag register */ 253 write_c0_dtaglo(itcblkgrn); 254 ehb(); 255 /* Write out to ITU with CACHE op */ 256 cache_op(Index_Store_Tag_D, INDEX_8); 257 /* Now set base address, and turn ITC on with 0x1 bit */ 258 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 ); 259 ehb(); 260 /* Write out to ITU with CACHE op */ 261 cache_op(Index_Store_Tag_D, INDEX_0); 262 write_c0_ecc(ectlval); 263 ehb(); 264 printk("Mapped %ld ITC cells starting at 0x%08x\n", 265 ((itcblkgrn & 0x7fe00000) >> 20), itc_base); 266 } 267 } 268 269 /* 270 * Function to protect cache flushes from concurrent execution 271 * depends on MP software model chosen. 272 */ 273 274 void mt_cflush_lockdown(void) 275 { 276 #ifdef CONFIG_MIPS_MT_SMTC 277 void smtc_cflush_lockdown(void); 278 279 smtc_cflush_lockdown(); 280 #endif /* CONFIG_MIPS_MT_SMTC */ 281 /* FILL IN VSMP and AP/SP VERSIONS HERE */ 282 } 283 284 void mt_cflush_release(void) 285 { 286 #ifdef CONFIG_MIPS_MT_SMTC 287 void smtc_cflush_release(void); 288 289 smtc_cflush_release(); 290 #endif /* CONFIG_MIPS_MT_SMTC */ 291 /* FILL IN VSMP and AP/SP VERSIONS HERE */ 292 } 293 294 struct class *mt_class; 295 296 static int __init mt_init(void) 297 { 298 struct class *mtc; 299 300 mtc = class_create(THIS_MODULE, "mt"); 301 if (IS_ERR(mtc)) 302 return PTR_ERR(mtc); 303 304 mt_class = mtc; 305 306 return 0; 307 } 308 309 subsys_initcall(mt_init); 310