1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * General MIPS MT support routines, usable in AP/SP and SMVP. 4 * Copyright (C) 2005 Mips Technologies, Inc 5 */ 6 7 #include <linux/device.h> 8 #include <linux/kernel.h> 9 #include <linux/sched.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 12 #include <linux/security.h> 13 14 #include <asm/cpu.h> 15 #include <asm/processor.h> 16 #include <linux/atomic.h> 17 #include <asm/hardirq.h> 18 #include <asm/mmu_context.h> 19 #include <asm/mipsmtregs.h> 20 #include <asm/r4kcache.h> 21 #include <asm/cacheflush.h> 22 23 int vpelimit; 24 25 static int __init maxvpes(char *str) 26 { 27 get_option(&str, &vpelimit); 28 29 return 1; 30 } 31 32 __setup("maxvpes=", maxvpes); 33 34 int tclimit; 35 36 static int __init maxtcs(char *str) 37 { 38 get_option(&str, &tclimit); 39 40 return 1; 41 } 42 43 __setup("maxtcs=", maxtcs); 44 45 /* 46 * Dump new MIPS MT state for the core. Does not leave TCs halted. 47 * Takes an argument which taken to be a pre-call MVPControl value. 48 */ 49 50 void mips_mt_regdump(unsigned long mvpctl) 51 { 52 unsigned long flags; 53 unsigned long vpflags; 54 unsigned long mvpconf0; 55 int nvpe; 56 int ntc; 57 int i; 58 int tc; 59 unsigned long haltval; 60 unsigned long tcstatval; 61 62 local_irq_save(flags); 63 vpflags = dvpe(); 64 printk("=== MIPS MT State Dump ===\n"); 65 printk("-- Global State --\n"); 66 printk(" MVPControl Passed: %08lx\n", mvpctl); 67 printk(" MVPControl Read: %08lx\n", vpflags); 68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0())); 69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 71 printk("-- per-VPE State --\n"); 72 for (i = 0; i < nvpe; i++) { 73 for (tc = 0; tc < ntc; tc++) { 74 settc(tc); 75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 76 printk(" VPE %d\n", i); 77 printk(" VPEControl : %08lx\n", 78 read_vpe_c0_vpecontrol()); 79 printk(" VPEConf0 : %08lx\n", 80 read_vpe_c0_vpeconf0()); 81 printk(" VPE%d.Status : %08lx\n", 82 i, read_vpe_c0_status()); 83 printk(" VPE%d.EPC : %08lx %pS\n", 84 i, read_vpe_c0_epc(), 85 (void *) read_vpe_c0_epc()); 86 printk(" VPE%d.Cause : %08lx\n", 87 i, read_vpe_c0_cause()); 88 printk(" VPE%d.Config7 : %08lx\n", 89 i, read_vpe_c0_config7()); 90 break; /* Next VPE */ 91 } 92 } 93 } 94 printk("-- per-TC State --\n"); 95 for (tc = 0; tc < ntc; tc++) { 96 settc(tc); 97 if (read_tc_c0_tcbind() == read_c0_tcbind()) { 98 /* Are we dumping ourself? */ 99 haltval = 0; /* Then we're not halted, and mustn't be */ 100 tcstatval = flags; /* And pre-dump TCStatus is flags */ 101 printk(" TC %d (current TC with VPE EPC above)\n", tc); 102 } else { 103 haltval = read_tc_c0_tchalt(); 104 write_tc_c0_tchalt(1); 105 tcstatval = read_tc_c0_tcstatus(); 106 printk(" TC %d\n", tc); 107 } 108 printk(" TCStatus : %08lx\n", tcstatval); 109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind()); 110 printk(" TCRestart : %08lx %pS\n", 111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart()); 112 printk(" TCHalt : %08lx\n", haltval); 113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext()); 114 if (!haltval) 115 write_tc_c0_tchalt(0); 116 } 117 printk("===========================\n"); 118 evpe(vpflags); 119 local_irq_restore(flags); 120 } 121 122 static int mt_opt_norps; 123 static int mt_opt_rpsctl = -1; 124 static int mt_opt_nblsu = -1; 125 static int mt_opt_forceconfig7; 126 static int mt_opt_config7 = -1; 127 128 static int __init rps_disable(char *s) 129 { 130 mt_opt_norps = 1; 131 return 1; 132 } 133 __setup("norps", rps_disable); 134 135 static int __init rpsctl_set(char *str) 136 { 137 get_option(&str, &mt_opt_rpsctl); 138 return 1; 139 } 140 __setup("rpsctl=", rpsctl_set); 141 142 static int __init nblsu_set(char *str) 143 { 144 get_option(&str, &mt_opt_nblsu); 145 return 1; 146 } 147 __setup("nblsu=", nblsu_set); 148 149 static int __init config7_set(char *str) 150 { 151 get_option(&str, &mt_opt_config7); 152 mt_opt_forceconfig7 = 1; 153 return 1; 154 } 155 __setup("config7=", config7_set); 156 157 static unsigned int itc_base; 158 159 static int __init set_itc_base(char *str) 160 { 161 get_option(&str, &itc_base); 162 return 1; 163 } 164 165 __setup("itcbase=", set_itc_base); 166 167 void mips_mt_set_cpuoptions(void) 168 { 169 unsigned int oconfig7 = read_c0_config7(); 170 unsigned int nconfig7 = oconfig7; 171 172 if (mt_opt_norps) { 173 printk("\"norps\" option deprecated: use \"rpsctl=\"\n"); 174 } 175 if (mt_opt_rpsctl >= 0) { 176 printk("34K return prediction stack override set to %d.\n", 177 mt_opt_rpsctl); 178 if (mt_opt_rpsctl) 179 nconfig7 |= (1 << 2); 180 else 181 nconfig7 &= ~(1 << 2); 182 } 183 if (mt_opt_nblsu >= 0) { 184 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu); 185 if (mt_opt_nblsu) 186 nconfig7 |= (1 << 5); 187 else 188 nconfig7 &= ~(1 << 5); 189 } 190 if (mt_opt_forceconfig7) { 191 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7); 192 nconfig7 = mt_opt_config7; 193 } 194 if (oconfig7 != nconfig7) { 195 __asm__ __volatile("sync"); 196 write_c0_config7(nconfig7); 197 ehb(); 198 printk("Config7: 0x%08x\n", read_c0_config7()); 199 } 200 201 if (itc_base != 0) { 202 /* 203 * Configure ITC mapping. This code is very 204 * specific to the 34K core family, which uses 205 * a special mode bit ("ITC") in the ErrCtl 206 * register to enable access to ITC control 207 * registers via cache "tag" operations. 208 */ 209 unsigned long ectlval; 210 unsigned long itcblkgrn; 211 212 /* ErrCtl register is known as "ecc" to Linux */ 213 ectlval = read_c0_ecc(); 214 write_c0_ecc(ectlval | (0x1 << 26)); 215 ehb(); 216 #define INDEX_0 (0x80000000) 217 #define INDEX_8 (0x80000008) 218 /* Read "cache tag" for Dcache pseudo-index 8 */ 219 cache_op(Index_Load_Tag_D, INDEX_8); 220 ehb(); 221 itcblkgrn = read_c0_dtaglo(); 222 itcblkgrn &= 0xfffe0000; 223 /* Set for 128 byte pitch of ITC cells */ 224 itcblkgrn |= 0x00000c00; 225 /* Stage in Tag register */ 226 write_c0_dtaglo(itcblkgrn); 227 ehb(); 228 /* Write out to ITU with CACHE op */ 229 cache_op(Index_Store_Tag_D, INDEX_8); 230 /* Now set base address, and turn ITC on with 0x1 bit */ 231 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 ); 232 ehb(); 233 /* Write out to ITU with CACHE op */ 234 cache_op(Index_Store_Tag_D, INDEX_0); 235 write_c0_ecc(ectlval); 236 ehb(); 237 printk("Mapped %ld ITC cells starting at 0x%08x\n", 238 ((itcblkgrn & 0x7fe00000) >> 20), itc_base); 239 } 240 } 241 242 struct class *mt_class; 243 244 static int __init mt_init(void) 245 { 246 struct class *mtc; 247 248 mtc = class_create(THIS_MODULE, "mt"); 249 if (IS_ERR(mtc)) 250 return PTR_ERR(mtc); 251 252 mt_class = mtc; 253 254 return 0; 255 } 256 257 subsys_initcall(mt_init); 258