1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (c) 2004 MIPS Inc 8 * Author: chris@mips.com 9 * 10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org> 11 */ 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/sched.h> 16 #include <linux/kernel_stat.h> 17 #include <asm/io.h> 18 #include <asm/irq.h> 19 #include <asm/msc01_ic.h> 20 #include <asm/traps.h> 21 22 static unsigned long _icctrl_msc; 23 #define MSC01_IC_REG_BASE _icctrl_msc 24 25 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) 26 #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) 27 28 static unsigned int irq_base; 29 30 /* mask off an interrupt */ 31 static inline void mask_msc_irq(unsigned int irq) 32 { 33 if (irq < (irq_base + 32)) 34 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); 35 else 36 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); 37 } 38 39 /* unmask an interrupt */ 40 static inline void unmask_msc_irq(unsigned int irq) 41 { 42 if (irq < (irq_base + 32)) 43 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); 44 else 45 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); 46 } 47 48 /* 49 * Masks and ACKs an IRQ 50 */ 51 static void level_mask_and_ack_msc_irq(unsigned int irq) 52 { 53 mask_msc_irq(irq); 54 if (!cpu_has_veic) 55 MSCIC_WRITE(MSC01_IC_EOI, 0); 56 /* This actually needs to be a call into platform code */ 57 smtc_im_ack_irq(irq); 58 } 59 60 /* 61 * Masks and ACKs an IRQ 62 */ 63 static void edge_mask_and_ack_msc_irq(unsigned int irq) 64 { 65 mask_msc_irq(irq); 66 if (!cpu_has_veic) 67 MSCIC_WRITE(MSC01_IC_EOI, 0); 68 else { 69 u32 r; 70 MSCIC_READ(MSC01_IC_SUP+irq*8, r); 71 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); 72 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); 73 } 74 smtc_im_ack_irq(irq); 75 } 76 77 /* 78 * End IRQ processing 79 */ 80 static void end_msc_irq(unsigned int irq) 81 { 82 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 83 unmask_msc_irq(irq); 84 } 85 86 /* 87 * Interrupt handler for interrupts coming from SOC-it. 88 */ 89 void ll_msc_irq(void) 90 { 91 unsigned int irq; 92 93 /* read the interrupt vector register */ 94 MSCIC_READ(MSC01_IC_VEC, irq); 95 if (irq < 64) 96 do_IRQ(irq + irq_base); 97 else { 98 /* Ignore spurious interrupt */ 99 } 100 } 101 102 static void msc_bind_eic_interrupt(int irq, int set) 103 { 104 MSCIC_WRITE(MSC01_IC_RAMW, 105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 106 } 107 108 static struct irq_chip msc_levelirq_type = { 109 .name = "SOC-it-Level", 110 .ack = level_mask_and_ack_msc_irq, 111 .mask = mask_msc_irq, 112 .mask_ack = level_mask_and_ack_msc_irq, 113 .unmask = unmask_msc_irq, 114 .eoi = unmask_msc_irq, 115 .end = end_msc_irq, 116 }; 117 118 static struct irq_chip msc_edgeirq_type = { 119 .name = "SOC-it-Edge", 120 .ack = edge_mask_and_ack_msc_irq, 121 .mask = mask_msc_irq, 122 .mask_ack = edge_mask_and_ack_msc_irq, 123 .unmask = unmask_msc_irq, 124 .eoi = unmask_msc_irq, 125 .end = end_msc_irq, 126 }; 127 128 129 void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) 130 { 131 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000); 132 133 /* Reset interrupt controller - initialises all registers to 0 */ 134 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); 135 136 board_bind_eic_interrupt = &msc_bind_eic_interrupt; 137 138 for (; nirq >= 0; nirq--, imp++) { 139 int n = imp->im_irq; 140 141 switch (imp->im_type) { 142 case MSC01_IRQ_EDGE: 143 set_irq_chip(irqbase+n, &msc_edgeirq_type); 144 if (cpu_has_veic) 145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 146 else 147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 148 break; 149 case MSC01_IRQ_LEVEL: 150 set_irq_chip(irqbase+n, &msc_levelirq_type); 151 if (cpu_has_veic) 152 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 153 else 154 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); 155 } 156 } 157 158 irq_base = irqbase; 159 160 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ 161 162 } 163