xref: /openbmc/linux/arch/mips/kernel/idle.c (revision ee89bd6b)
1 /*
2  * MIPS idle loop and WAIT instruction support.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004, 2011, 2012	 MIPS Technologies, Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/export.h>
15 #include <linux/init.h>
16 #include <linux/irqflags.h>
17 #include <linux/printk.h>
18 #include <linux/sched.h>
19 #include <asm/cpu.h>
20 #include <asm/cpu-info.h>
21 #include <asm/idle.h>
22 #include <asm/mipsregs.h>
23 
24 /*
25  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26  * the implementation of the "wait" feature differs between CPU families. This
27  * points to the function that implements CPU specific wait.
28  * The wait instruction stops the pipeline and reduces the power consumption of
29  * the CPU very much.
30  */
31 void (*cpu_wait)(void);
32 EXPORT_SYMBOL(cpu_wait);
33 
34 static void r3081_wait(void)
35 {
36 	unsigned long cfg = read_c0_conf();
37 	write_c0_conf(cfg | R30XX_CONF_HALT);
38 	local_irq_enable();
39 }
40 
41 static void r39xx_wait(void)
42 {
43 	if (!need_resched())
44 		write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
45 	local_irq_enable();
46 }
47 
48 void r4k_wait(void)
49 {
50 	local_irq_enable();
51 	__r4k_wait();
52 }
53 
54 /*
55  * This variant is preferable as it allows testing need_resched and going to
56  * sleep depending on the outcome atomically.  Unfortunately the "It is
57  * implementation-dependent whether the pipeline restarts when a non-enabled
58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59  * using this version a gamble.
60  */
61 void r4k_wait_irqoff(void)
62 {
63 	if (!need_resched())
64 		__asm__(
65 		"	.set	push		\n"
66 		"	.set	mips3		\n"
67 		"	wait			\n"
68 		"	.set	pop		\n");
69 	local_irq_enable();
70 	__asm__(
71 	"	.globl __pastwait	\n"
72 	"__pastwait:			\n");
73 }
74 
75 /*
76  * The RM7000 variant has to handle erratum 38.	 The workaround is to not
77  * have any pending stores when the WAIT instruction is executed.
78  */
79 static void rm7k_wait_irqoff(void)
80 {
81 	if (!need_resched())
82 		__asm__(
83 		"	.set	push					\n"
84 		"	.set	mips3					\n"
85 		"	.set	noat					\n"
86 		"	mfc0	$1, $12					\n"
87 		"	sync						\n"
88 		"	mtc0	$1, $12		# stalls until W stage	\n"
89 		"	wait						\n"
90 		"	mtc0	$1, $12		# stalls until W stage	\n"
91 		"	.set	pop					\n");
92 	local_irq_enable();
93 }
94 
95 /*
96  * The Au1xxx wait is available only if using 32khz counter or
97  * external timer source, but specifically not CP0 Counter.
98  * alchemy/common/time.c may override cpu_wait!
99  */
100 static void au1k_wait(void)
101 {
102 	__asm__(
103 	"	.set	mips3			\n"
104 	"	cache	0x14, 0(%0)		\n"
105 	"	cache	0x14, 32(%0)		\n"
106 	"	sync				\n"
107 	"	nop				\n"
108 	"	wait				\n"
109 	"	nop				\n"
110 	"	nop				\n"
111 	"	nop				\n"
112 	"	nop				\n"
113 	"	.set	mips0			\n"
114 	: : "r" (au1k_wait));
115 	local_irq_enable();
116 }
117 
118 static int __initdata nowait;
119 
120 static int __init wait_disable(char *s)
121 {
122 	nowait = 1;
123 
124 	return 1;
125 }
126 
127 __setup("nowait", wait_disable);
128 
129 void __init check_wait(void)
130 {
131 	struct cpuinfo_mips *c = &current_cpu_data;
132 
133 	if (nowait) {
134 		printk("Wait instruction disabled.\n");
135 		return;
136 	}
137 
138 	switch (c->cputype) {
139 	case CPU_R3081:
140 	case CPU_R3081E:
141 		cpu_wait = r3081_wait;
142 		break;
143 	case CPU_TX3927:
144 		cpu_wait = r39xx_wait;
145 		break;
146 	case CPU_R4200:
147 /*	case CPU_R4300: */
148 	case CPU_R4600:
149 	case CPU_R4640:
150 	case CPU_R4650:
151 	case CPU_R4700:
152 	case CPU_R5000:
153 	case CPU_R5500:
154 	case CPU_NEVADA:
155 	case CPU_4KC:
156 	case CPU_4KEC:
157 	case CPU_4KSC:
158 	case CPU_5KC:
159 	case CPU_25KF:
160 	case CPU_PR4450:
161 	case CPU_BMIPS3300:
162 	case CPU_BMIPS4350:
163 	case CPU_BMIPS4380:
164 	case CPU_BMIPS5000:
165 	case CPU_CAVIUM_OCTEON:
166 	case CPU_CAVIUM_OCTEON_PLUS:
167 	case CPU_CAVIUM_OCTEON2:
168 	case CPU_JZRISC:
169 	case CPU_LOONGSON1:
170 	case CPU_XLR:
171 	case CPU_XLP:
172 		cpu_wait = r4k_wait;
173 		break;
174 
175 	case CPU_RM7000:
176 		cpu_wait = rm7k_wait_irqoff;
177 		break;
178 
179 	case CPU_M14KC:
180 	case CPU_M14KEC:
181 	case CPU_24K:
182 	case CPU_34K:
183 	case CPU_1004K:
184 		cpu_wait = r4k_wait;
185 		if (read_c0_config7() & MIPS_CONF7_WII)
186 			cpu_wait = r4k_wait_irqoff;
187 		break;
188 
189 	case CPU_74K:
190 		cpu_wait = r4k_wait;
191 		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
192 			cpu_wait = r4k_wait_irqoff;
193 		break;
194 
195 	case CPU_TX49XX:
196 		cpu_wait = r4k_wait_irqoff;
197 		break;
198 	case CPU_ALCHEMY:
199 		cpu_wait = au1k_wait;
200 		break;
201 	case CPU_20KC:
202 		/*
203 		 * WAIT on Rev1.0 has E1, E2, E3 and E16.
204 		 * WAIT on Rev2.0 and Rev3.0 has E16.
205 		 * Rev3.1 WAIT is nop, why bother
206 		 */
207 		if ((c->processor_id & 0xff) <= 0x64)
208 			break;
209 
210 		/*
211 		 * Another rev is incremeting c0_count at a reduced clock
212 		 * rate while in WAIT mode.  So we basically have the choice
213 		 * between using the cp0 timer as clocksource or avoiding
214 		 * the WAIT instruction.  Until more details are known,
215 		 * disable the use of WAIT for 20Kc entirely.
216 		   cpu_wait = r4k_wait;
217 		 */
218 		break;
219 	case CPU_RM9000:
220 		if ((c->processor_id & 0x00ff) >= 0x40)
221 			cpu_wait = r4k_wait;
222 		break;
223 	default:
224 		break;
225 	}
226 }
227 
228 static void smtc_idle_hook(void)
229 {
230 #ifdef CONFIG_MIPS_MT_SMTC
231 	void smtc_idle_loop_hook(void);
232 
233 	smtc_idle_loop_hook();
234 #endif
235 }
236 
237 void arch_cpu_idle(void)
238 {
239 	smtc_idle_hook();
240 	if (cpu_wait)
241 		cpu_wait();
242 	else
243 		local_irq_enable();
244 }
245