1 /* 2 * MIPS idle loop and WAIT instruction support. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/export.h> 15 #include <linux/init.h> 16 #include <linux/irqflags.h> 17 #include <linux/printk.h> 18 #include <linux/sched.h> 19 #include <asm/cpu.h> 20 #include <asm/cpu-info.h> 21 #include <asm/cpu-type.h> 22 #include <asm/idle.h> 23 #include <asm/mipsregs.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void); 33 EXPORT_SYMBOL(cpu_wait); 34 35 static void r3081_wait(void) 36 { 37 unsigned long cfg = read_c0_conf(); 38 write_c0_conf(cfg | R30XX_CONF_HALT); 39 local_irq_enable(); 40 } 41 42 static void r39xx_wait(void) 43 { 44 if (!need_resched()) 45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 46 local_irq_enable(); 47 } 48 49 void r4k_wait(void) 50 { 51 local_irq_enable(); 52 __r4k_wait(); 53 } 54 55 /* 56 * This variant is preferable as it allows testing need_resched and going to 57 * sleep depending on the outcome atomically. Unfortunately the "It is 58 * implementation-dependent whether the pipeline restarts when a non-enabled 59 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 60 * using this version a gamble. 61 */ 62 void r4k_wait_irqoff(void) 63 { 64 if (!need_resched()) 65 __asm__( 66 " .set push \n" 67 " .set arch=r4000 \n" 68 " wait \n" 69 " .set pop \n"); 70 local_irq_enable(); 71 __asm__( 72 " .globl __pastwait \n" 73 "__pastwait: \n"); 74 } 75 76 /* 77 * The RM7000 variant has to handle erratum 38. The workaround is to not 78 * have any pending stores when the WAIT instruction is executed. 79 */ 80 static void rm7k_wait_irqoff(void) 81 { 82 if (!need_resched()) 83 __asm__( 84 " .set push \n" 85 " .set arch=r4000 \n" 86 " .set noat \n" 87 " mfc0 $1, $12 \n" 88 " sync \n" 89 " mtc0 $1, $12 # stalls until W stage \n" 90 " wait \n" 91 " mtc0 $1, $12 # stalls until W stage \n" 92 " .set pop \n"); 93 local_irq_enable(); 94 } 95 96 /* 97 * Au1 'wait' is only useful when the 32kHz counter is used as timer, 98 * since coreclock (and the cp0 counter) stops upon executing it. Only an 99 * interrupt can wake it, so they must be enabled before entering idle modes. 100 */ 101 static void au1k_wait(void) 102 { 103 unsigned long c0status = read_c0_status() | 1; /* irqs on */ 104 105 __asm__( 106 " .set arch=r4000 \n" 107 " cache 0x14, 0(%0) \n" 108 " cache 0x14, 32(%0) \n" 109 " sync \n" 110 " mtc0 %1, $12 \n" /* wr c0status */ 111 " wait \n" 112 " nop \n" 113 " nop \n" 114 " nop \n" 115 " nop \n" 116 " .set mips0 \n" 117 : : "r" (au1k_wait), "r" (c0status)); 118 } 119 120 static int __initdata nowait; 121 122 static int __init wait_disable(char *s) 123 { 124 nowait = 1; 125 126 return 1; 127 } 128 129 __setup("nowait", wait_disable); 130 131 void __init check_wait(void) 132 { 133 struct cpuinfo_mips *c = ¤t_cpu_data; 134 135 if (nowait) { 136 printk("Wait instruction disabled.\n"); 137 return; 138 } 139 140 switch (current_cpu_type()) { 141 case CPU_R3081: 142 case CPU_R3081E: 143 cpu_wait = r3081_wait; 144 break; 145 case CPU_TX3927: 146 cpu_wait = r39xx_wait; 147 break; 148 case CPU_R4200: 149 /* case CPU_R4300: */ 150 case CPU_R4600: 151 case CPU_R4640: 152 case CPU_R4650: 153 case CPU_R4700: 154 case CPU_R5000: 155 case CPU_R5500: 156 case CPU_NEVADA: 157 case CPU_4KC: 158 case CPU_4KEC: 159 case CPU_4KSC: 160 case CPU_5KC: 161 case CPU_25KF: 162 case CPU_PR4450: 163 case CPU_BMIPS3300: 164 case CPU_BMIPS4350: 165 case CPU_BMIPS4380: 166 case CPU_BMIPS5000: 167 case CPU_CAVIUM_OCTEON: 168 case CPU_CAVIUM_OCTEON_PLUS: 169 case CPU_CAVIUM_OCTEON2: 170 case CPU_CAVIUM_OCTEON3: 171 case CPU_JZRISC: 172 case CPU_LOONGSON1: 173 case CPU_XLR: 174 case CPU_XLP: 175 cpu_wait = r4k_wait; 176 break; 177 178 case CPU_RM7000: 179 cpu_wait = rm7k_wait_irqoff; 180 break; 181 182 case CPU_M14KC: 183 case CPU_M14KEC: 184 case CPU_24K: 185 case CPU_34K: 186 case CPU_1004K: 187 case CPU_1074K: 188 case CPU_INTERAPTIV: 189 case CPU_PROAPTIV: 190 case CPU_P5600: 191 case CPU_M5150: 192 cpu_wait = r4k_wait; 193 if (read_c0_config7() & MIPS_CONF7_WII) 194 cpu_wait = r4k_wait_irqoff; 195 break; 196 197 case CPU_74K: 198 cpu_wait = r4k_wait; 199 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 200 cpu_wait = r4k_wait_irqoff; 201 break; 202 203 case CPU_TX49XX: 204 cpu_wait = r4k_wait_irqoff; 205 break; 206 case CPU_ALCHEMY: 207 cpu_wait = au1k_wait; 208 break; 209 case CPU_20KC: 210 /* 211 * WAIT on Rev1.0 has E1, E2, E3 and E16. 212 * WAIT on Rev2.0 and Rev3.0 has E16. 213 * Rev3.1 WAIT is nop, why bother 214 */ 215 if ((c->processor_id & 0xff) <= 0x64) 216 break; 217 218 /* 219 * Another rev is incremeting c0_count at a reduced clock 220 * rate while in WAIT mode. So we basically have the choice 221 * between using the cp0 timer as clocksource or avoiding 222 * the WAIT instruction. Until more details are known, 223 * disable the use of WAIT for 20Kc entirely. 224 cpu_wait = r4k_wait; 225 */ 226 break; 227 case CPU_RM9000: 228 if ((c->processor_id & 0x00ff) >= 0x40) 229 cpu_wait = r4k_wait; 230 break; 231 default: 232 break; 233 } 234 } 235 236 static void smtc_idle_hook(void) 237 { 238 #ifdef CONFIG_MIPS_MT_SMTC 239 void smtc_idle_loop_hook(void); 240 241 smtc_idle_loop_hook(); 242 #endif 243 } 244 245 void arch_cpu_idle(void) 246 { 247 smtc_idle_hook(); 248 if (cpu_wait) 249 cpu_wait(); 250 else 251 local_irq_enable(); 252 } 253