1 /* 2 * MIPS idle loop and WAIT instruction support. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/export.h> 15 #include <linux/init.h> 16 #include <linux/irqflags.h> 17 #include <linux/printk.h> 18 #include <linux/sched.h> 19 #include <asm/cpu.h> 20 #include <asm/cpu-info.h> 21 #include <asm/idle.h> 22 #include <asm/mipsregs.h> 23 24 /* 25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 26 * the implementation of the "wait" feature differs between CPU families. This 27 * points to the function that implements CPU specific wait. 28 * The wait instruction stops the pipeline and reduces the power consumption of 29 * the CPU very much. 30 */ 31 void (*cpu_wait)(void); 32 EXPORT_SYMBOL(cpu_wait); 33 34 static void r3081_wait(void) 35 { 36 unsigned long cfg = read_c0_conf(); 37 write_c0_conf(cfg | R30XX_CONF_HALT); 38 local_irq_enable(); 39 } 40 41 static void r39xx_wait(void) 42 { 43 if (!need_resched()) 44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 45 local_irq_enable(); 46 } 47 48 void r4k_wait(void) 49 { 50 local_irq_enable(); 51 __r4k_wait(); 52 } 53 54 /* 55 * This variant is preferable as it allows testing need_resched and going to 56 * sleep depending on the outcome atomically. Unfortunately the "It is 57 * implementation-dependent whether the pipeline restarts when a non-enabled 58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 59 * using this version a gamble. 60 */ 61 void r4k_wait_irqoff(void) 62 { 63 if (!need_resched()) 64 __asm__( 65 " .set push \n" 66 " .set mips3 \n" 67 " wait \n" 68 " .set pop \n"); 69 local_irq_enable(); 70 __asm__( 71 " .globl __pastwait \n" 72 "__pastwait: \n"); 73 } 74 75 /* 76 * The RM7000 variant has to handle erratum 38. The workaround is to not 77 * have any pending stores when the WAIT instruction is executed. 78 */ 79 static void rm7k_wait_irqoff(void) 80 { 81 if (!need_resched()) 82 __asm__( 83 " .set push \n" 84 " .set mips3 \n" 85 " .set noat \n" 86 " mfc0 $1, $12 \n" 87 " sync \n" 88 " mtc0 $1, $12 # stalls until W stage \n" 89 " wait \n" 90 " mtc0 $1, $12 # stalls until W stage \n" 91 " .set pop \n"); 92 local_irq_enable(); 93 } 94 95 /* 96 * Au1 'wait' is only useful when the 32kHz counter is used as timer, 97 * since coreclock (and the cp0 counter) stops upon executing it. Only an 98 * interrupt can wake it, so they must be enabled before entering idle modes. 99 */ 100 static void au1k_wait(void) 101 { 102 unsigned long c0status = read_c0_status() | 1; /* irqs on */ 103 104 __asm__( 105 " .set mips3 \n" 106 " cache 0x14, 0(%0) \n" 107 " cache 0x14, 32(%0) \n" 108 " sync \n" 109 " mtc0 %1, $12 \n" /* wr c0status */ 110 " wait \n" 111 " nop \n" 112 " nop \n" 113 " nop \n" 114 " nop \n" 115 " .set mips0 \n" 116 : : "r" (au1k_wait), "r" (c0status)); 117 } 118 119 static int __initdata nowait; 120 121 static int __init wait_disable(char *s) 122 { 123 nowait = 1; 124 125 return 1; 126 } 127 128 __setup("nowait", wait_disable); 129 130 void __init check_wait(void) 131 { 132 struct cpuinfo_mips *c = ¤t_cpu_data; 133 134 if (nowait) { 135 printk("Wait instruction disabled.\n"); 136 return; 137 } 138 139 switch (c->cputype) { 140 case CPU_R3081: 141 case CPU_R3081E: 142 cpu_wait = r3081_wait; 143 break; 144 case CPU_TX3927: 145 cpu_wait = r39xx_wait; 146 break; 147 case CPU_R4200: 148 /* case CPU_R4300: */ 149 case CPU_R4600: 150 case CPU_R4640: 151 case CPU_R4650: 152 case CPU_R4700: 153 case CPU_R5000: 154 case CPU_R5500: 155 case CPU_NEVADA: 156 case CPU_4KC: 157 case CPU_4KEC: 158 case CPU_4KSC: 159 case CPU_5KC: 160 case CPU_25KF: 161 case CPU_PR4450: 162 case CPU_BMIPS3300: 163 case CPU_BMIPS4350: 164 case CPU_BMIPS4380: 165 case CPU_BMIPS5000: 166 case CPU_CAVIUM_OCTEON: 167 case CPU_CAVIUM_OCTEON_PLUS: 168 case CPU_CAVIUM_OCTEON2: 169 case CPU_CAVIUM_OCTEON3: 170 case CPU_JZRISC: 171 case CPU_LOONGSON1: 172 case CPU_XLR: 173 case CPU_XLP: 174 cpu_wait = r4k_wait; 175 break; 176 177 case CPU_RM7000: 178 cpu_wait = rm7k_wait_irqoff; 179 break; 180 181 case CPU_M14KC: 182 case CPU_M14KEC: 183 case CPU_24K: 184 case CPU_34K: 185 case CPU_1004K: 186 cpu_wait = r4k_wait; 187 if (read_c0_config7() & MIPS_CONF7_WII) 188 cpu_wait = r4k_wait_irqoff; 189 break; 190 191 case CPU_74K: 192 cpu_wait = r4k_wait; 193 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 194 cpu_wait = r4k_wait_irqoff; 195 break; 196 197 case CPU_TX49XX: 198 cpu_wait = r4k_wait_irqoff; 199 break; 200 case CPU_ALCHEMY: 201 cpu_wait = au1k_wait; 202 break; 203 case CPU_20KC: 204 /* 205 * WAIT on Rev1.0 has E1, E2, E3 and E16. 206 * WAIT on Rev2.0 and Rev3.0 has E16. 207 * Rev3.1 WAIT is nop, why bother 208 */ 209 if ((c->processor_id & 0xff) <= 0x64) 210 break; 211 212 /* 213 * Another rev is incremeting c0_count at a reduced clock 214 * rate while in WAIT mode. So we basically have the choice 215 * between using the cp0 timer as clocksource or avoiding 216 * the WAIT instruction. Until more details are known, 217 * disable the use of WAIT for 20Kc entirely. 218 cpu_wait = r4k_wait; 219 */ 220 break; 221 case CPU_RM9000: 222 if ((c->processor_id & 0x00ff) >= 0x40) 223 cpu_wait = r4k_wait; 224 break; 225 default: 226 break; 227 } 228 } 229 230 static void smtc_idle_hook(void) 231 { 232 #ifdef CONFIG_MIPS_MT_SMTC 233 void smtc_idle_loop_hook(void); 234 235 smtc_idle_loop_hook(); 236 #endif 237 } 238 239 void arch_cpu_idle(void) 240 { 241 smtc_idle_hook(); 242 if (cpu_wait) 243 cpu_wait(); 244 else 245 local_irq_enable(); 246 } 247