149f2ec91SRalf Baechle /* 249f2ec91SRalf Baechle * MIPS idle loop and WAIT instruction support. 349f2ec91SRalf Baechle * 449f2ec91SRalf Baechle * Copyright (C) xxxx the Anonymous 549f2ec91SRalf Baechle * Copyright (C) 1994 - 2006 Ralf Baechle 649f2ec91SRalf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki 749f2ec91SRalf Baechle * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 849f2ec91SRalf Baechle * 949f2ec91SRalf Baechle * This program is free software; you can redistribute it and/or 1049f2ec91SRalf Baechle * modify it under the terms of the GNU General Public License 1149f2ec91SRalf Baechle * as published by the Free Software Foundation; either version 1249f2ec91SRalf Baechle * 2 of the License, or (at your option) any later version. 1349f2ec91SRalf Baechle */ 1491955e3eSPaul Burton #include <linux/cpu.h> 1549f2ec91SRalf Baechle #include <linux/export.h> 1649f2ec91SRalf Baechle #include <linux/init.h> 1749f2ec91SRalf Baechle #include <linux/irqflags.h> 1849f2ec91SRalf Baechle #include <linux/printk.h> 1949f2ec91SRalf Baechle #include <linux/sched.h> 2049f2ec91SRalf Baechle #include <asm/cpu.h> 2149f2ec91SRalf Baechle #include <asm/cpu-info.h> 2269f24d17SRalf Baechle #include <asm/cpu-type.h> 23bdc92d74SRalf Baechle #include <asm/idle.h> 2449f2ec91SRalf Baechle #include <asm/mipsregs.h> 2549f2ec91SRalf Baechle 2649f2ec91SRalf Baechle /* 2749f2ec91SRalf Baechle * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 2849f2ec91SRalf Baechle * the implementation of the "wait" feature differs between CPU families. This 2949f2ec91SRalf Baechle * points to the function that implements CPU specific wait. 3049f2ec91SRalf Baechle * The wait instruction stops the pipeline and reduces the power consumption of 3149f2ec91SRalf Baechle * the CPU very much. 3249f2ec91SRalf Baechle */ 3349f2ec91SRalf Baechle void (*cpu_wait)(void); 3449f2ec91SRalf Baechle EXPORT_SYMBOL(cpu_wait); 3549f2ec91SRalf Baechle 3697c8580eSPaul Burton static void __cpuidle r3081_wait(void) 3749f2ec91SRalf Baechle { 3849f2ec91SRalf Baechle unsigned long cfg = read_c0_conf(); 3949f2ec91SRalf Baechle write_c0_conf(cfg | R30XX_CONF_HALT); 40fb40bc3eSRalf Baechle local_irq_enable(); 4149f2ec91SRalf Baechle } 4249f2ec91SRalf Baechle 4397c8580eSPaul Burton static void __cpuidle r39xx_wait(void) 4449f2ec91SRalf Baechle { 4549f2ec91SRalf Baechle if (!need_resched()) 4649f2ec91SRalf Baechle write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 4749f2ec91SRalf Baechle local_irq_enable(); 4849f2ec91SRalf Baechle } 4949f2ec91SRalf Baechle 5097c8580eSPaul Burton void __cpuidle r4k_wait(void) 51087d990bSRalf Baechle { 52087d990bSRalf Baechle local_irq_enable(); 53087d990bSRalf Baechle __r4k_wait(); 54087d990bSRalf Baechle } 55087d990bSRalf Baechle 5649f2ec91SRalf Baechle /* 5749f2ec91SRalf Baechle * This variant is preferable as it allows testing need_resched and going to 5849f2ec91SRalf Baechle * sleep depending on the outcome atomically. Unfortunately the "It is 5949f2ec91SRalf Baechle * implementation-dependent whether the pipeline restarts when a non-enabled 6049f2ec91SRalf Baechle * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 6149f2ec91SRalf Baechle * using this version a gamble. 6249f2ec91SRalf Baechle */ 6397c8580eSPaul Burton void __cpuidle r4k_wait_irqoff(void) 6449f2ec91SRalf Baechle { 6549f2ec91SRalf Baechle if (!need_resched()) 66f91a148aSRalf Baechle __asm__( 67f91a148aSRalf Baechle " .set push \n" 68a809d460SRalf Baechle " .set arch=r4000 \n" 6949f2ec91SRalf Baechle " wait \n" 7049f2ec91SRalf Baechle " .set pop \n"); 7149f2ec91SRalf Baechle local_irq_enable(); 7249f2ec91SRalf Baechle } 7349f2ec91SRalf Baechle 7449f2ec91SRalf Baechle /* 7549f2ec91SRalf Baechle * The RM7000 variant has to handle erratum 38. The workaround is to not 7649f2ec91SRalf Baechle * have any pending stores when the WAIT instruction is executed. 7749f2ec91SRalf Baechle */ 7897c8580eSPaul Burton static void __cpuidle rm7k_wait_irqoff(void) 7949f2ec91SRalf Baechle { 8049f2ec91SRalf Baechle if (!need_resched()) 8149f2ec91SRalf Baechle __asm__( 8249f2ec91SRalf Baechle " .set push \n" 83a809d460SRalf Baechle " .set arch=r4000 \n" 8449f2ec91SRalf Baechle " .set noat \n" 8549f2ec91SRalf Baechle " mfc0 $1, $12 \n" 8649f2ec91SRalf Baechle " sync \n" 8749f2ec91SRalf Baechle " mtc0 $1, $12 # stalls until W stage \n" 8849f2ec91SRalf Baechle " wait \n" 8949f2ec91SRalf Baechle " mtc0 $1, $12 # stalls until W stage \n" 9049f2ec91SRalf Baechle " .set pop \n"); 9149f2ec91SRalf Baechle local_irq_enable(); 9249f2ec91SRalf Baechle } 9349f2ec91SRalf Baechle 9449f2ec91SRalf Baechle /* 95e63a24ddSManuel Lauss * Au1 'wait' is only useful when the 32kHz counter is used as timer, 96e63a24ddSManuel Lauss * since coreclock (and the cp0 counter) stops upon executing it. Only an 97e63a24ddSManuel Lauss * interrupt can wake it, so they must be enabled before entering idle modes. 9849f2ec91SRalf Baechle */ 9997c8580eSPaul Burton static void __cpuidle au1k_wait(void) 10049f2ec91SRalf Baechle { 101e63a24ddSManuel Lauss unsigned long c0status = read_c0_status() | 1; /* irqs on */ 102e63a24ddSManuel Lauss 103f91a148aSRalf Baechle __asm__( 104378ed6f0SPaul Burton " .set push \n" 105a809d460SRalf Baechle " .set arch=r4000 \n" 10649f2ec91SRalf Baechle " cache 0x14, 0(%0) \n" 10749f2ec91SRalf Baechle " cache 0x14, 32(%0) \n" 10849f2ec91SRalf Baechle " sync \n" 109e63a24ddSManuel Lauss " mtc0 %1, $12 \n" /* wr c0status */ 11049f2ec91SRalf Baechle " wait \n" 11149f2ec91SRalf Baechle " nop \n" 11249f2ec91SRalf Baechle " nop \n" 11349f2ec91SRalf Baechle " nop \n" 11449f2ec91SRalf Baechle " nop \n" 115378ed6f0SPaul Burton " .set pop \n" 116e63a24ddSManuel Lauss : : "r" (au1k_wait), "r" (c0status)); 11749f2ec91SRalf Baechle } 11849f2ec91SRalf Baechle 11949f2ec91SRalf Baechle static int __initdata nowait; 12049f2ec91SRalf Baechle 12149f2ec91SRalf Baechle static int __init wait_disable(char *s) 12249f2ec91SRalf Baechle { 12349f2ec91SRalf Baechle nowait = 1; 12449f2ec91SRalf Baechle 12549f2ec91SRalf Baechle return 1; 12649f2ec91SRalf Baechle } 12749f2ec91SRalf Baechle 12849f2ec91SRalf Baechle __setup("nowait", wait_disable); 12949f2ec91SRalf Baechle 13049f2ec91SRalf Baechle void __init check_wait(void) 13149f2ec91SRalf Baechle { 13249f2ec91SRalf Baechle struct cpuinfo_mips *c = ¤t_cpu_data; 13349f2ec91SRalf Baechle 13449f2ec91SRalf Baechle if (nowait) { 13549f2ec91SRalf Baechle printk("Wait instruction disabled.\n"); 13649f2ec91SRalf Baechle return; 13749f2ec91SRalf Baechle } 13849f2ec91SRalf Baechle 1395b10a0e8SPaul Burton /* 1405b10a0e8SPaul Burton * MIPSr6 specifies that masked interrupts should unblock an executing 1415b10a0e8SPaul Burton * wait instruction, and thus that it is safe for us to use 1425b10a0e8SPaul Burton * r4k_wait_irqoff. Yippee! 1435b10a0e8SPaul Burton */ 1445b10a0e8SPaul Burton if (cpu_has_mips_r6) { 1455b10a0e8SPaul Burton cpu_wait = r4k_wait_irqoff; 1465b10a0e8SPaul Burton return; 1475b10a0e8SPaul Burton } 1485b10a0e8SPaul Burton 14969f24d17SRalf Baechle switch (current_cpu_type()) { 15049f2ec91SRalf Baechle case CPU_R3081: 15149f2ec91SRalf Baechle case CPU_R3081E: 15249f2ec91SRalf Baechle cpu_wait = r3081_wait; 15349f2ec91SRalf Baechle break; 15449f2ec91SRalf Baechle case CPU_TX3927: 15549f2ec91SRalf Baechle cpu_wait = r39xx_wait; 15649f2ec91SRalf Baechle break; 15749f2ec91SRalf Baechle case CPU_R4200: 15849f2ec91SRalf Baechle /* case CPU_R4300: */ 15949f2ec91SRalf Baechle case CPU_R4600: 16049f2ec91SRalf Baechle case CPU_R4640: 16149f2ec91SRalf Baechle case CPU_R4650: 16249f2ec91SRalf Baechle case CPU_R4700: 16349f2ec91SRalf Baechle case CPU_R5000: 16449f2ec91SRalf Baechle case CPU_R5500: 16549f2ec91SRalf Baechle case CPU_NEVADA: 16649f2ec91SRalf Baechle case CPU_4KC: 16749f2ec91SRalf Baechle case CPU_4KEC: 16849f2ec91SRalf Baechle case CPU_4KSC: 16949f2ec91SRalf Baechle case CPU_5KC: 170bf463f2fSAurelien Jarno case CPU_5KE: 17149f2ec91SRalf Baechle case CPU_25KF: 17249f2ec91SRalf Baechle case CPU_PR4450: 17349f2ec91SRalf Baechle case CPU_BMIPS3300: 17449f2ec91SRalf Baechle case CPU_BMIPS4350: 17549f2ec91SRalf Baechle case CPU_BMIPS4380: 17649f2ec91SRalf Baechle case CPU_CAVIUM_OCTEON: 17749f2ec91SRalf Baechle case CPU_CAVIUM_OCTEON_PLUS: 17849f2ec91SRalf Baechle case CPU_CAVIUM_OCTEON2: 1794122af0aSDavid Daney case CPU_CAVIUM_OCTEON3: 18049f2ec91SRalf Baechle case CPU_JZRISC: 18149f2ec91SRalf Baechle case CPU_LOONGSON1: 18249f2ec91SRalf Baechle case CPU_XLR: 18349f2ec91SRalf Baechle case CPU_XLP: 18449f2ec91SRalf Baechle cpu_wait = r4k_wait; 18549f2ec91SRalf Baechle break; 186b2edcfc8SHuacai Chen case CPU_LOONGSON3: 187b2edcfc8SHuacai Chen if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2) 188b2edcfc8SHuacai Chen cpu_wait = r4k_wait; 189b2edcfc8SHuacai Chen break; 190b2edcfc8SHuacai Chen 191adaa0b6cSPetri Gynther case CPU_BMIPS5000: 192adaa0b6cSPetri Gynther cpu_wait = r4k_wait_irqoff; 193adaa0b6cSPetri Gynther break; 19449f2ec91SRalf Baechle case CPU_RM7000: 19549f2ec91SRalf Baechle cpu_wait = rm7k_wait_irqoff; 19649f2ec91SRalf Baechle break; 19749f2ec91SRalf Baechle 198e38df288SJames Hogan case CPU_PROAPTIV: 199e38df288SJames Hogan case CPU_P5600: 200e38df288SJames Hogan /* 201e38df288SJames Hogan * Incoming Fast Debug Channel (FDC) data during a wait 202e38df288SJames Hogan * instruction causes the wait never to resume, even if an 203e38df288SJames Hogan * interrupt is received. Avoid using wait at all if FDC data is 204e38df288SJames Hogan * likely to be received. 205e38df288SJames Hogan */ 206e38df288SJames Hogan if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY)) 207e38df288SJames Hogan break; 208e38df288SJames Hogan /* fall through */ 20949f2ec91SRalf Baechle case CPU_M14KC: 21049f2ec91SRalf Baechle case CPU_M14KEC: 21149f2ec91SRalf Baechle case CPU_24K: 21249f2ec91SRalf Baechle case CPU_34K: 21349f2ec91SRalf Baechle case CPU_1004K: 214442e14a2SSteven J. Hill case CPU_1074K: 21526ab96dfSLeonid Yegoshin case CPU_INTERAPTIV: 216f36c4720SLeonid Yegoshin case CPU_M5150: 2174695089fSLeonid Yegoshin case CPU_QEMU_GENERIC: 21849f2ec91SRalf Baechle cpu_wait = r4k_wait; 21949f2ec91SRalf Baechle if (read_c0_config7() & MIPS_CONF7_WII) 22049f2ec91SRalf Baechle cpu_wait = r4k_wait_irqoff; 22149f2ec91SRalf Baechle break; 22249f2ec91SRalf Baechle 22349f2ec91SRalf Baechle case CPU_74K: 22449f2ec91SRalf Baechle cpu_wait = r4k_wait; 22549f2ec91SRalf Baechle if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 22649f2ec91SRalf Baechle cpu_wait = r4k_wait_irqoff; 22749f2ec91SRalf Baechle break; 22849f2ec91SRalf Baechle 22949f2ec91SRalf Baechle case CPU_TX49XX: 23049f2ec91SRalf Baechle cpu_wait = r4k_wait_irqoff; 23149f2ec91SRalf Baechle break; 23249f2ec91SRalf Baechle case CPU_ALCHEMY: 23349f2ec91SRalf Baechle cpu_wait = au1k_wait; 23449f2ec91SRalf Baechle break; 23549f2ec91SRalf Baechle case CPU_20KC: 23649f2ec91SRalf Baechle /* 23749f2ec91SRalf Baechle * WAIT on Rev1.0 has E1, E2, E3 and E16. 23849f2ec91SRalf Baechle * WAIT on Rev2.0 and Rev3.0 has E16. 23949f2ec91SRalf Baechle * Rev3.1 WAIT is nop, why bother 24049f2ec91SRalf Baechle */ 24149f2ec91SRalf Baechle if ((c->processor_id & 0xff) <= 0x64) 24249f2ec91SRalf Baechle break; 24349f2ec91SRalf Baechle 24449f2ec91SRalf Baechle /* 24549f2ec91SRalf Baechle * Another rev is incremeting c0_count at a reduced clock 24649f2ec91SRalf Baechle * rate while in WAIT mode. So we basically have the choice 24749f2ec91SRalf Baechle * between using the cp0 timer as clocksource or avoiding 24849f2ec91SRalf Baechle * the WAIT instruction. Until more details are known, 24949f2ec91SRalf Baechle * disable the use of WAIT for 20Kc entirely. 25049f2ec91SRalf Baechle cpu_wait = r4k_wait; 25149f2ec91SRalf Baechle */ 25249f2ec91SRalf Baechle break; 25349f2ec91SRalf Baechle default: 25449f2ec91SRalf Baechle break; 25549f2ec91SRalf Baechle } 25649f2ec91SRalf Baechle } 25749f2ec91SRalf Baechle 25800baf857SRalf Baechle void arch_cpu_idle(void) 25900baf857SRalf Baechle { 26049f2ec91SRalf Baechle if (cpu_wait) 261c9b6869dSRalf Baechle cpu_wait(); 26249f2ec91SRalf Baechle else 26349f2ec91SRalf Baechle local_irq_enable(); 26449f2ec91SRalf Baechle } 265da9f970fSPaul Burton 266da9f970fSPaul Burton #ifdef CONFIG_CPU_IDLE 267da9f970fSPaul Burton 268da9f970fSPaul Burton int mips_cpuidle_wait_enter(struct cpuidle_device *dev, 269da9f970fSPaul Burton struct cpuidle_driver *drv, int index) 270da9f970fSPaul Burton { 271da9f970fSPaul Burton arch_cpu_idle(); 272da9f970fSPaul Burton return index; 273da9f970fSPaul Burton } 274da9f970fSPaul Burton 275da9f970fSPaul Burton #endif 276