xref: /openbmc/linux/arch/mips/kernel/head.S (revision d0b73b48) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
15 */
16#include <linux/init.h>
17#include <linux/threads.h>
18
19#include <asm/addrspace.h>
20#include <asm/asm.h>
21#include <asm/asmmacro.h>
22#include <asm/irqflags.h>
23#include <asm/regdef.h>
24#include <asm/pgtable-bits.h>
25#include <asm/mipsregs.h>
26#include <asm/stackframe.h>
27
28#include <kernel-entry-init.h>
29
30	/*
31	 * inputs are the text nasid in t1, data nasid in t2.
32	 */
33	.macro MAPPED_KERNEL_SETUP_TLB
34#ifdef CONFIG_MAPPED_KERNEL
35	/*
36	 * This needs to read the nasid - assume 0 for now.
37	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
38	 * 0+DVG in tlblo_1.
39	 */
40	dli	t0, 0xffffffffc0000000
41	dmtc0	t0, CP0_ENTRYHI
42	li	t0, 0x1c000		# Offset of text into node memory
43	dsll	t1, NASID_SHFT		# Shift text nasid into place
44	dsll	t2, NASID_SHFT		# Same for data nasid
45	or	t1, t1, t0		# Physical load address of kernel text
46	or	t2, t2, t0		# Physical load address of kernel data
47	dsrl	t1, 12			# 4K pfn
48	dsrl	t2, 12			# 4K pfn
49	dsll	t1, 6			# Get pfn into place
50	dsll	t2, 6			# Get pfn into place
51	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
52	or	t0, t0, t1
53	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr
54	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
55	or	t0, t0, t2
56	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr
57	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M
58	mtc0	t0, CP0_PAGEMASK
59	li	t0, 0			# KMAP_INX
60	mtc0	t0, CP0_INDEX
61	li	t0, 1
62	mtc0	t0, CP0_WIRED
63	tlbwi
64#else
65	mtc0	zero, CP0_WIRED
66#endif
67	.endm
68
69	/*
70	 * For the moment disable interrupts, mark the kernel mode and
71	 * set ST0_KX so that the CPU does not spit fire when using
72	 * 64-bit addresses.  A full initialization of the CPU's status
73	 * register is done later in per_cpu_trap_init().
74	 */
75	.macro	setup_c0_status set clr
76	.set	push
77#ifdef CONFIG_MIPS_MT_SMTC
78	/*
79	 * For SMTC, we need to set privilege and disable interrupts only for
80	 * the current TC, using the TCStatus register.
81	 */
82	mfc0	t0, CP0_TCSTATUS
83	/* Fortunately CU 0 is in the same place in both registers */
84	/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
85	li	t1, ST0_CU0 | 0x08001c00
86	or	t0, t1
87	/* Clear TKSU, leave IXMT */
88	xori	t0, 0x00001800
89	mtc0	t0, CP0_TCSTATUS
90	_ehb
91	/* We need to leave the global IE bit set, but clear EXL...*/
92	mfc0	t0, CP0_STATUS
93	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
94	xor	t0, ST0_EXL | ST0_ERL | \clr
95	mtc0	t0, CP0_STATUS
96#else
97	mfc0	t0, CP0_STATUS
98	or	t0, ST0_CU0|\set|0x1f|\clr
99	xor	t0, 0x1f|\clr
100	mtc0	t0, CP0_STATUS
101	.set	noreorder
102	sll	zero,3				# ehb
103#endif
104	.set	pop
105	.endm
106
107	.macro	setup_c0_status_pri
108#ifdef CONFIG_64BIT
109	setup_c0_status ST0_KX 0
110#else
111	setup_c0_status 0 0
112#endif
113	.endm
114
115	.macro	setup_c0_status_sec
116#ifdef CONFIG_64BIT
117	setup_c0_status ST0_KX ST0_BEV
118#else
119	setup_c0_status 0 ST0_BEV
120#endif
121	.endm
122
123#ifndef CONFIG_NO_EXCEPT_FILL
124	/*
125	 * Reserved space for exception handlers.
126	 * Necessary for machines which link their kernels at KSEG0.
127	 */
128	.fill	0x400
129#endif
130
131EXPORT(_stext)
132
133#ifdef CONFIG_BOOT_RAW
134	/*
135	 * Give us a fighting chance of running if execution beings at the
136	 * kernel load address.  This is needed because this platform does
137	 * not have a ELF loader yet.
138	 */
139FEXPORT(__kernel_entry)
140	j	kernel_entry
141#endif
142
143	__REF
144
145NESTED(kernel_entry, 16, sp)			# kernel entry point
146
147	kernel_entry_setup			# cpu specific setup
148
149	setup_c0_status_pri
150
151	/* We might not get launched at the address the kernel is linked to,
152	   so we jump there.  */
153	PTR_LA	t0, 0f
154	jr	t0
1550:
156
157#ifdef CONFIG_MIPS_MT_SMTC
158	/*
159	 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
160	 * We still need to enable interrupts globally in Status,
161	 * and clear EXL/ERL.
162	 *
163	 * TCContext is used to track interrupt levels under
164	 * service in SMTC kernel. Clear for boot TC before
165	 * allowing any interrupts.
166	 */
167	mtc0	zero, CP0_TCCONTEXT
168
169	mfc0	t0, CP0_STATUS
170	ori	t0, t0, 0xff1f
171	xori	t0, t0, 0x001e
172	mtc0	t0, CP0_STATUS
173#endif /* CONFIG_MIPS_MT_SMTC */
174
175	PTR_LA		t0, __bss_start		# clear .bss
176	LONG_S		zero, (t0)
177	PTR_LA		t1, __bss_stop - LONGSIZE
1781:
179	PTR_ADDIU	t0, LONGSIZE
180	LONG_S		zero, (t0)
181	bne		t0, t1, 1b
182
183	LONG_S		a0, fw_arg0		# firmware arguments
184	LONG_S		a1, fw_arg1
185	LONG_S		a2, fw_arg2
186	LONG_S		a3, fw_arg3
187
188	MTC0		zero, CP0_CONTEXT	# clear context register
189	PTR_LA		$28, init_thread_union
190	/* Set the SP after an empty pt_regs.  */
191	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
192	PTR_ADDU	sp, $28
193	back_to_back_c0_hazard
194	set_saved_sp	sp, t0, t1
195	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
196
197	j		start_kernel
198	END(kernel_entry)
199
200	__CPUINIT
201
202#ifdef CONFIG_SMP
203/*
204 * SMP slave cpus entry point.  Board specific code for bootstrap calls this
205 * function after setting up the stack and gp registers.
206 */
207NESTED(smp_bootstrap, 16, sp)
208#ifdef CONFIG_MIPS_MT_SMTC
209	/*
210	 * Read-modify-writes of Status must be atomic, and this
211	 * is one case where CLI is invoked without EXL being
212	 * necessarily set. The CLI and setup_c0_status will
213	 * in fact be redundant for all but the first TC of
214	 * each VPE being booted.
215	 */
216	DMT	10	# dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
217	jal	mips_ihb
218#endif /* CONFIG_MIPS_MT_SMTC */
219	setup_c0_status_sec
220	smp_slave_setup
221#ifdef CONFIG_MIPS_MT_SMTC
222	andi	t2, t2, VPECONTROL_TE
223	beqz	t2, 2f
224	EMT		# emt
2252:
226#endif /* CONFIG_MIPS_MT_SMTC */
227	j	start_secondary
228	END(smp_bootstrap)
229#endif /* CONFIG_SMP */
230
231	__FINIT
232