1 /* 2 * Copyright (C) 2014 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #include <linux/elf.h> 12 #include <linux/sched.h> 13 14 /* FPU modes */ 15 enum { 16 FP_FRE, 17 FP_FR0, 18 FP_FR1, 19 }; 20 21 /** 22 * struct mode_req - ABI FPU mode requirements 23 * @single: The program being loaded needs an FPU but it will only issue 24 * single precision instructions meaning that it can execute in 25 * either FR0 or FR1. 26 * @soft: The soft(-float) requirement means that the program being 27 * loaded needs has no FPU dependency at all (i.e. it has no 28 * FPU instructions). 29 * @fr1: The program being loaded depends on FPU being in FR=1 mode. 30 * @frdefault: The program being loaded depends on the default FPU mode. 31 * That is FR0 for O32 and FR1 for N32/N64. 32 * @fre: The program being loaded depends on FPU with FRE=1. This mode is 33 * a bridge which uses FR=1 whilst still being able to maintain 34 * full compatibility with pre-existing code using the O32 FP32 35 * ABI. 36 * 37 * More information about the FP ABIs can be found here: 38 * 39 * https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up 40 * 41 */ 42 43 struct mode_req { 44 bool single; 45 bool soft; 46 bool fr1; 47 bool frdefault; 48 bool fre; 49 }; 50 51 static const struct mode_req fpu_reqs[] = { 52 [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, 53 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, 54 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, 55 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, 56 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, 57 [MIPS_ABI_FP_XX] = { false, false, true, true, true }, 58 [MIPS_ABI_FP_64] = { false, false, true, false, false }, 59 [MIPS_ABI_FP_64A] = { false, false, true, false, true } 60 }; 61 62 /* 63 * Mode requirements when .MIPS.abiflags is not present in the ELF. 64 * Not present means that everything is acceptable except FR1. 65 */ 66 static struct mode_req none_req = { true, true, false, true, true }; 67 68 int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, 69 bool is_interp, struct arch_elf_state *state) 70 { 71 struct elf32_hdr *ehdr32 = _ehdr; 72 struct elf32_phdr *phdr32 = _phdr; 73 struct elf64_phdr *phdr64 = _phdr; 74 struct mips_elf_abiflags_v0 abiflags; 75 int ret; 76 77 /* Lets see if this is an O32 ELF */ 78 if (ehdr32->e_ident[EI_CLASS] == ELFCLASS32) { 79 /* FR = 1 for N32 */ 80 if (ehdr32->e_flags & EF_MIPS_ABI2) 81 state->overall_fp_mode = FP_FR1; 82 else 83 /* Set a good default FPU mode for O32 */ 84 state->overall_fp_mode = cpu_has_mips_r6 ? 85 FP_FRE : FP_FR0; 86 87 if (ehdr32->e_flags & EF_MIPS_FP64) { 88 /* 89 * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it 90 * later if needed 91 */ 92 if (is_interp) 93 state->interp_fp_abi = MIPS_ABI_FP_OLD_64; 94 else 95 state->fp_abi = MIPS_ABI_FP_OLD_64; 96 } 97 if (phdr32->p_type != PT_MIPS_ABIFLAGS) 98 return 0; 99 100 if (phdr32->p_filesz < sizeof(abiflags)) 101 return -EINVAL; 102 103 ret = kernel_read(elf, phdr32->p_offset, 104 (char *)&abiflags, 105 sizeof(abiflags)); 106 } else { 107 /* FR=1 is really the only option for 64-bit */ 108 state->overall_fp_mode = FP_FR1; 109 110 if (phdr64->p_type != PT_MIPS_ABIFLAGS) 111 return 0; 112 if (phdr64->p_filesz < sizeof(abiflags)) 113 return -EINVAL; 114 115 ret = kernel_read(elf, phdr64->p_offset, 116 (char *)&abiflags, 117 sizeof(abiflags)); 118 } 119 120 if (ret < 0) 121 return ret; 122 if (ret != sizeof(abiflags)) 123 return -EIO; 124 125 /* Record the required FP ABIs for use by mips_check_elf */ 126 if (is_interp) 127 state->interp_fp_abi = abiflags.fp_abi; 128 else 129 state->fp_abi = abiflags.fp_abi; 130 131 return 0; 132 } 133 134 int arch_check_elf(void *_ehdr, bool has_interpreter, 135 struct arch_elf_state *state) 136 { 137 struct elf32_hdr *ehdr = _ehdr; 138 struct mode_req prog_req, interp_req; 139 int fp_abi, interp_fp_abi, abi0, abi1, max_abi; 140 141 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 142 return 0; 143 144 fp_abi = state->fp_abi; 145 146 if (has_interpreter) { 147 interp_fp_abi = state->interp_fp_abi; 148 149 abi0 = min(fp_abi, interp_fp_abi); 150 abi1 = max(fp_abi, interp_fp_abi); 151 } else { 152 abi0 = abi1 = fp_abi; 153 } 154 155 /* ABI limits. O32 = FP_64A, N32/N64 = FP_SOFT */ 156 max_abi = ((ehdr->e_ident[EI_CLASS] == ELFCLASS32) && 157 (!(ehdr->e_flags & EF_MIPS_ABI2))) ? 158 MIPS_ABI_FP_64A : MIPS_ABI_FP_SOFT; 159 160 if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) || 161 (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN)) 162 return -ELIBBAD; 163 164 /* It's time to determine the FPU mode requirements */ 165 prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0]; 166 interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1]; 167 168 /* 169 * Check whether the program's and interp's ABIs have a matching FPU 170 * mode requirement. 171 */ 172 prog_req.single = interp_req.single && prog_req.single; 173 prog_req.soft = interp_req.soft && prog_req.soft; 174 prog_req.fr1 = interp_req.fr1 && prog_req.fr1; 175 prog_req.frdefault = interp_req.frdefault && prog_req.frdefault; 176 prog_req.fre = interp_req.fre && prog_req.fre; 177 178 /* 179 * Determine the desired FPU mode 180 * 181 * Decision making: 182 * 183 * - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This 184 * means that we have a combination of program and interpreter 185 * that inherently require the hybrid FP mode. 186 * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or 187 * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU 188 * instructions so we don't care about the mode. We will simply use 189 * the one preferred by the hardware. In fpxx case, that ABI can 190 * handle both FR=1 and FR=0, so, again, we simply choose the one 191 * preferred by the hardware. Next, if we only use single-precision 192 * FPU instructions, and the default ABI FPU mode is not good 193 * (ie single + any ABI combination), we set again the FPU mode to the 194 * one is preferred by the hardware. Next, if we know that the code 195 * will only use single-precision instructions, shown by single being 196 * true but frdefault being false, then we again set the FPU mode to 197 * the one that is preferred by the hardware. 198 * - We want FP_FR1 if that's the only matching mode and the default one 199 * is not good. 200 * - Return with -ELIBADD if we can't find a matching FPU mode. 201 */ 202 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) 203 state->overall_fp_mode = FP_FRE; 204 else if ((prog_req.fr1 && prog_req.frdefault) || 205 (prog_req.single && !prog_req.frdefault)) 206 /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */ 207 state->overall_fp_mode = ((current_cpu_data.fpu_id & MIPS_FPIR_F64) && 208 cpu_has_mips_r2_r6) ? 209 FP_FR1 : FP_FR0; 210 else if (prog_req.fr1) 211 state->overall_fp_mode = FP_FR1; 212 else if (!prog_req.fre && !prog_req.frdefault && 213 !prog_req.fr1 && !prog_req.single && !prog_req.soft) 214 return -ELIBBAD; 215 216 return 0; 217 } 218 219 static inline void set_thread_fp_mode(int hybrid, int regs32) 220 { 221 if (hybrid) 222 set_thread_flag(TIF_HYBRID_FPREGS); 223 else 224 clear_thread_flag(TIF_HYBRID_FPREGS); 225 if (regs32) 226 set_thread_flag(TIF_32BIT_FPREGS); 227 else 228 clear_thread_flag(TIF_32BIT_FPREGS); 229 } 230 231 void mips_set_personality_fp(struct arch_elf_state *state) 232 { 233 /* 234 * This function is only ever called for O32 ELFs so we should 235 * not be worried about N32/N64 binaries. 236 */ 237 238 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 239 return; 240 241 switch (state->overall_fp_mode) { 242 case FP_FRE: 243 set_thread_fp_mode(1, 0); 244 break; 245 case FP_FR0: 246 set_thread_fp_mode(0, 1); 247 break; 248 case FP_FR1: 249 set_thread_fp_mode(0, 0); 250 break; 251 default: 252 BUG(); 253 } 254 } 255