1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <asm/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 38 /* 39 * Get the FPU Implementation/Revision. 40 */ 41 static inline unsigned long cpu_get_fpu_id(void) 42 { 43 unsigned long tmp, fpu_id; 44 45 tmp = read_c0_status(); 46 __enable_fpu(FPU_AS_IS); 47 fpu_id = read_32bit_cp1_register(CP1_REVISION); 48 write_c0_status(tmp); 49 return fpu_id; 50 } 51 52 /* 53 * Check if the CPU has an external FPU. 54 */ 55 static inline int __cpu_has_fpu(void) 56 { 57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 58 } 59 60 static inline unsigned long cpu_get_msa_id(void) 61 { 62 unsigned long status, msa_id; 63 64 status = read_c0_status(); 65 __enable_fpu(FPU_64BIT); 66 enable_msa(); 67 msa_id = read_msa_ir(); 68 disable_msa(); 69 write_c0_status(status); 70 return msa_id; 71 } 72 73 /* 74 * Determine the FCSR mask for FPU hardware. 75 */ 76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 77 { 78 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 79 80 fcsr = c->fpu_csr31; 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 82 83 sr = read_c0_status(); 84 __enable_fpu(FPU_AS_IS); 85 86 fcsr0 = fcsr & mask; 87 write_32bit_cp1_register(CP1_STATUS, fcsr0); 88 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 89 90 fcsr1 = fcsr | ~mask; 91 write_32bit_cp1_register(CP1_STATUS, fcsr1); 92 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 93 94 write_32bit_cp1_register(CP1_STATUS, fcsr); 95 96 write_c0_status(sr); 97 98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 99 } 100 101 /* 102 * Set the FIR feature flags for the FPU emulator. 103 */ 104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 105 { 106 u32 value; 107 108 value = 0; 109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 112 value |= MIPS_FPIR_D | MIPS_FPIR_S; 113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 116 c->fpu_id = value; 117 } 118 119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 120 static unsigned int mips_nofpu_msk31; 121 122 /* 123 * Set options for FPU hardware. 124 */ 125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 126 { 127 c->fpu_id = cpu_get_fpu_id(); 128 mips_nofpu_msk31 = c->fpu_msk31; 129 130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 133 if (c->fpu_id & MIPS_FPIR_3D) 134 c->ases |= MIPS_ASE_MIPS3D; 135 if (c->fpu_id & MIPS_FPIR_FREP) 136 c->options |= MIPS_CPU_FRE; 137 } 138 139 cpu_set_fpu_fcsr_mask(c); 140 } 141 142 /* 143 * Set options for the FPU emulator. 144 */ 145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 146 { 147 c->options &= ~MIPS_CPU_FPU; 148 c->fpu_msk31 = mips_nofpu_msk31; 149 150 cpu_set_nofpu_id(c); 151 } 152 153 static int mips_fpu_disabled; 154 155 static int __init fpu_disable(char *s) 156 { 157 cpu_set_nofpu_opts(&boot_cpu_data); 158 mips_fpu_disabled = 1; 159 160 return 1; 161 } 162 163 __setup("nofpu", fpu_disable); 164 165 int mips_dsp_disabled; 166 167 static int __init dsp_disable(char *s) 168 { 169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 170 mips_dsp_disabled = 1; 171 172 return 1; 173 } 174 175 __setup("nodsp", dsp_disable); 176 177 static int mips_htw_disabled; 178 179 static int __init htw_disable(char *s) 180 { 181 mips_htw_disabled = 1; 182 cpu_data[0].options &= ~MIPS_CPU_HTW; 183 write_c0_pwctl(read_c0_pwctl() & 184 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 185 186 return 1; 187 } 188 189 __setup("nohtw", htw_disable); 190 191 static int mips_ftlb_disabled; 192 static int mips_has_ftlb_configured; 193 194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable); 195 196 static int __init ftlb_disable(char *s) 197 { 198 unsigned int config4, mmuextdef; 199 200 /* 201 * If the core hasn't done any FTLB configuration, there is nothing 202 * for us to do here. 203 */ 204 if (!mips_has_ftlb_configured) 205 return 1; 206 207 /* Disable it in the boot cpu */ 208 if (set_ftlb_enable(&cpu_data[0], 0)) { 209 pr_warn("Can't turn FTLB off\n"); 210 return 1; 211 } 212 213 back_to_back_c0_hazard(); 214 215 config4 = read_c0_config4(); 216 217 /* Check that FTLB has been disabled */ 218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 221 /* This should never happen */ 222 pr_warn("FTLB could not be disabled!\n"); 223 return 1; 224 } 225 226 mips_ftlb_disabled = 1; 227 mips_has_ftlb_configured = 0; 228 229 /* 230 * noftlb is mainly used for debug purposes so print 231 * an informative message instead of using pr_debug() 232 */ 233 pr_info("FTLB has been disabled\n"); 234 235 /* 236 * Some of these bits are duplicated in the decode_config4. 237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 238 * once FTLB has been disabled so undo what decode_config4 did. 239 */ 240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 241 cpu_data[0].tlbsizeftlbsets; 242 cpu_data[0].tlbsizeftlbsets = 0; 243 cpu_data[0].tlbsizeftlbways = 0; 244 245 return 1; 246 } 247 248 __setup("noftlb", ftlb_disable); 249 250 251 static inline void check_errata(void) 252 { 253 struct cpuinfo_mips *c = ¤t_cpu_data; 254 255 switch (current_cpu_type()) { 256 case CPU_34K: 257 /* 258 * Erratum "RPS May Cause Incorrect Instruction Execution" 259 * This code only handles VPE0, any SMP/RTOS code 260 * making use of VPE1 will be responsable for that VPE. 261 */ 262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 264 break; 265 default: 266 break; 267 } 268 } 269 270 void __init check_bugs32(void) 271 { 272 check_errata(); 273 } 274 275 /* 276 * Probe whether cpu has config register by trying to play with 277 * alternate cache bit and see whether it matters. 278 * It's used by cpu_probe to distinguish between R3000A and R3081. 279 */ 280 static inline int cpu_has_confreg(void) 281 { 282 #ifdef CONFIG_CPU_R3000 283 extern unsigned long r3k_cache_size(unsigned long); 284 unsigned long size1, size2; 285 unsigned long cfg = read_c0_conf(); 286 287 size1 = r3k_cache_size(ST0_ISC); 288 write_c0_conf(cfg ^ R30XX_CONF_AC); 289 size2 = r3k_cache_size(ST0_ISC); 290 write_c0_conf(cfg); 291 return size1 != size2; 292 #else 293 return 0; 294 #endif 295 } 296 297 static inline void set_elf_platform(int cpu, const char *plat) 298 { 299 if (cpu == 0) 300 __elf_platform = plat; 301 } 302 303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 304 { 305 #ifdef __NEED_VMBITS_PROBE 306 write_c0_entryhi(0x3fffffffffffe000ULL); 307 back_to_back_c0_hazard(); 308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 309 #endif 310 } 311 312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 313 { 314 switch (isa) { 315 case MIPS_CPU_ISA_M64R2: 316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 317 case MIPS_CPU_ISA_M64R1: 318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 319 case MIPS_CPU_ISA_V: 320 c->isa_level |= MIPS_CPU_ISA_V; 321 case MIPS_CPU_ISA_IV: 322 c->isa_level |= MIPS_CPU_ISA_IV; 323 case MIPS_CPU_ISA_III: 324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 325 break; 326 327 /* R6 incompatible with everything else */ 328 case MIPS_CPU_ISA_M64R6: 329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 330 case MIPS_CPU_ISA_M32R6: 331 c->isa_level |= MIPS_CPU_ISA_M32R6; 332 /* Break here so we don't add incompatible ISAs */ 333 break; 334 case MIPS_CPU_ISA_M32R2: 335 c->isa_level |= MIPS_CPU_ISA_M32R2; 336 case MIPS_CPU_ISA_M32R1: 337 c->isa_level |= MIPS_CPU_ISA_M32R1; 338 case MIPS_CPU_ISA_II: 339 c->isa_level |= MIPS_CPU_ISA_II; 340 break; 341 } 342 } 343 344 static char unknown_isa[] = KERN_ERR \ 345 "Unsupported ISA type, c0.config0: %d."; 346 347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 348 { 349 350 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 351 352 /* 353 * 0 = All TLBWR instructions go to FTLB 354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 355 * FTLB and 1 goes to the VTLB. 356 * 2 = 7:1: As above with 7:1 ratio. 357 * 3 = 3:1: As above with 3:1 ratio. 358 * 359 * Use the linear midpoint as the probability threshold. 360 */ 361 if (probability >= 12) 362 return 1; 363 else if (probability >= 6) 364 return 2; 365 else 366 /* 367 * So FTLB is less than 4 times bigger than VTLB. 368 * A 3:1 ratio can still be useful though. 369 */ 370 return 3; 371 } 372 373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) 374 { 375 unsigned int config; 376 377 /* It's implementation dependent how the FTLB can be enabled */ 378 switch (c->cputype) { 379 case CPU_PROAPTIV: 380 case CPU_P5600: 381 /* proAptiv & related cores use Config6 to enable the FTLB */ 382 config = read_c0_config6(); 383 /* Clear the old probability value */ 384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 385 if (enable) 386 /* Enable FTLB */ 387 write_c0_config6(config | 388 (calculate_ftlb_probability(c) 389 << MIPS_CONF6_FTLBP_SHIFT) 390 | MIPS_CONF6_FTLBEN); 391 else 392 /* Disable FTLB */ 393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN); 394 break; 395 case CPU_I6400: 396 /* I6400 & related cores use Config7 to configure FTLB */ 397 config = read_c0_config7(); 398 /* Clear the old probability value */ 399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT); 400 write_c0_config7(config | (calculate_ftlb_probability(c) 401 << MIPS_CONF7_FTLBP_SHIFT)); 402 break; 403 default: 404 return 1; 405 } 406 407 return 0; 408 } 409 410 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 411 { 412 unsigned int config0; 413 int isa; 414 415 config0 = read_c0_config(); 416 417 /* 418 * Look for Standard TLB or Dual VTLB and FTLB 419 */ 420 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 421 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 422 c->options |= MIPS_CPU_TLB; 423 424 isa = (config0 & MIPS_CONF_AT) >> 13; 425 switch (isa) { 426 case 0: 427 switch ((config0 & MIPS_CONF_AR) >> 10) { 428 case 0: 429 set_isa(c, MIPS_CPU_ISA_M32R1); 430 break; 431 case 1: 432 set_isa(c, MIPS_CPU_ISA_M32R2); 433 break; 434 case 2: 435 set_isa(c, MIPS_CPU_ISA_M32R6); 436 break; 437 default: 438 goto unknown; 439 } 440 break; 441 case 2: 442 switch ((config0 & MIPS_CONF_AR) >> 10) { 443 case 0: 444 set_isa(c, MIPS_CPU_ISA_M64R1); 445 break; 446 case 1: 447 set_isa(c, MIPS_CPU_ISA_M64R2); 448 break; 449 case 2: 450 set_isa(c, MIPS_CPU_ISA_M64R6); 451 break; 452 default: 453 goto unknown; 454 } 455 break; 456 default: 457 goto unknown; 458 } 459 460 return config0 & MIPS_CONF_M; 461 462 unknown: 463 panic(unknown_isa, config0); 464 } 465 466 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 467 { 468 unsigned int config1; 469 470 config1 = read_c0_config1(); 471 472 if (config1 & MIPS_CONF1_MD) 473 c->ases |= MIPS_ASE_MDMX; 474 if (config1 & MIPS_CONF1_WR) 475 c->options |= MIPS_CPU_WATCH; 476 if (config1 & MIPS_CONF1_CA) 477 c->ases |= MIPS_ASE_MIPS16; 478 if (config1 & MIPS_CONF1_EP) 479 c->options |= MIPS_CPU_EJTAG; 480 if (config1 & MIPS_CONF1_FP) { 481 c->options |= MIPS_CPU_FPU; 482 c->options |= MIPS_CPU_32FPR; 483 } 484 if (cpu_has_tlb) { 485 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 486 c->tlbsizevtlb = c->tlbsize; 487 c->tlbsizeftlbsets = 0; 488 } 489 490 return config1 & MIPS_CONF_M; 491 } 492 493 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 494 { 495 unsigned int config2; 496 497 config2 = read_c0_config2(); 498 499 if (config2 & MIPS_CONF2_SL) 500 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 501 502 return config2 & MIPS_CONF_M; 503 } 504 505 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 506 { 507 unsigned int config3; 508 509 config3 = read_c0_config3(); 510 511 if (config3 & MIPS_CONF3_SM) { 512 c->ases |= MIPS_ASE_SMARTMIPS; 513 c->options |= MIPS_CPU_RIXI; 514 } 515 if (config3 & MIPS_CONF3_RXI) 516 c->options |= MIPS_CPU_RIXI; 517 if (config3 & MIPS_CONF3_DSP) 518 c->ases |= MIPS_ASE_DSP; 519 if (config3 & MIPS_CONF3_DSP2P) 520 c->ases |= MIPS_ASE_DSP2P; 521 if (config3 & MIPS_CONF3_VINT) 522 c->options |= MIPS_CPU_VINT; 523 if (config3 & MIPS_CONF3_VEIC) 524 c->options |= MIPS_CPU_VEIC; 525 if (config3 & MIPS_CONF3_MT) 526 c->ases |= MIPS_ASE_MIPSMT; 527 if (config3 & MIPS_CONF3_ULRI) 528 c->options |= MIPS_CPU_ULRI; 529 if (config3 & MIPS_CONF3_ISA) 530 c->options |= MIPS_CPU_MICROMIPS; 531 if (config3 & MIPS_CONF3_VZ) 532 c->ases |= MIPS_ASE_VZ; 533 if (config3 & MIPS_CONF3_SC) 534 c->options |= MIPS_CPU_SEGMENTS; 535 if (config3 & MIPS_CONF3_MSA) 536 c->ases |= MIPS_ASE_MSA; 537 /* Only tested on 32-bit cores */ 538 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { 539 c->htw_seq = 0; 540 c->options |= MIPS_CPU_HTW; 541 } 542 if (config3 & MIPS_CONF3_CDMM) 543 c->options |= MIPS_CPU_CDMM; 544 if (config3 & MIPS_CONF3_SP) 545 c->options |= MIPS_CPU_SP; 546 547 return config3 & MIPS_CONF_M; 548 } 549 550 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 551 { 552 unsigned int config4; 553 unsigned int newcf4; 554 unsigned int mmuextdef; 555 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 556 557 config4 = read_c0_config4(); 558 559 if (cpu_has_tlb) { 560 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 561 c->options |= MIPS_CPU_TLBINV; 562 /* 563 * This is a bit ugly. R6 has dropped that field from 564 * config4 and the only valid configuration is VTLB+FTLB so 565 * set a good value for mmuextdef for that case. 566 */ 567 if (cpu_has_mips_r6) 568 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 569 else 570 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 571 572 switch (mmuextdef) { 573 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 574 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 575 c->tlbsizevtlb = c->tlbsize; 576 break; 577 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 578 c->tlbsizevtlb += 579 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 580 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 581 c->tlbsize = c->tlbsizevtlb; 582 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 583 /* fall through */ 584 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 585 if (mips_ftlb_disabled) 586 break; 587 newcf4 = (config4 & ~ftlb_page) | 588 (page_size_ftlb(mmuextdef) << 589 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 590 write_c0_config4(newcf4); 591 back_to_back_c0_hazard(); 592 config4 = read_c0_config4(); 593 if (config4 != newcf4) { 594 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 595 PAGE_SIZE, config4); 596 /* Switch FTLB off */ 597 set_ftlb_enable(c, 0); 598 break; 599 } 600 c->tlbsizeftlbsets = 1 << 601 ((config4 & MIPS_CONF4_FTLBSETS) >> 602 MIPS_CONF4_FTLBSETS_SHIFT); 603 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 604 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 605 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 606 mips_has_ftlb_configured = 1; 607 break; 608 } 609 } 610 611 c->kscratch_mask = (config4 >> 16) & 0xff; 612 613 return config4 & MIPS_CONF_M; 614 } 615 616 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 617 { 618 unsigned int config5; 619 620 config5 = read_c0_config5(); 621 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 622 write_c0_config5(config5); 623 624 if (config5 & MIPS_CONF5_EVA) 625 c->options |= MIPS_CPU_EVA; 626 if (config5 & MIPS_CONF5_MRP) 627 c->options |= MIPS_CPU_MAAR; 628 if (config5 & MIPS_CONF5_LLB) 629 c->options |= MIPS_CPU_RW_LLB; 630 #ifdef CONFIG_XPA 631 if (config5 & MIPS_CONF5_MVH) 632 c->options |= MIPS_CPU_XPA; 633 #endif 634 635 return config5 & MIPS_CONF_M; 636 } 637 638 static void decode_configs(struct cpuinfo_mips *c) 639 { 640 int ok; 641 642 /* MIPS32 or MIPS64 compliant CPU. */ 643 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 644 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 645 646 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 647 648 /* Enable FTLB if present and not disabled */ 649 set_ftlb_enable(c, !mips_ftlb_disabled); 650 651 ok = decode_config0(c); /* Read Config registers. */ 652 BUG_ON(!ok); /* Arch spec violation! */ 653 if (ok) 654 ok = decode_config1(c); 655 if (ok) 656 ok = decode_config2(c); 657 if (ok) 658 ok = decode_config3(c); 659 if (ok) 660 ok = decode_config4(c); 661 if (ok) 662 ok = decode_config5(c); 663 664 mips_probe_watch_registers(c); 665 666 if (cpu_has_rixi) { 667 /* Enable the RIXI exceptions */ 668 set_c0_pagegrain(PG_IEC); 669 back_to_back_c0_hazard(); 670 /* Verify the IEC bit is set */ 671 if (read_c0_pagegrain() & PG_IEC) 672 c->options |= MIPS_CPU_RIXIEX; 673 } 674 675 #ifndef CONFIG_MIPS_CPS 676 if (cpu_has_mips_r2_r6) { 677 c->core = get_ebase_cpunum(); 678 if (cpu_has_mipsmt) 679 c->core >>= fls(core_nvpes()) - 1; 680 } 681 #endif 682 } 683 684 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 685 | MIPS_CPU_COUNTER) 686 687 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 688 { 689 switch (c->processor_id & PRID_IMP_MASK) { 690 case PRID_IMP_R2000: 691 c->cputype = CPU_R2000; 692 __cpu_name[cpu] = "R2000"; 693 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 694 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 695 MIPS_CPU_NOFPUEX; 696 if (__cpu_has_fpu()) 697 c->options |= MIPS_CPU_FPU; 698 c->tlbsize = 64; 699 break; 700 case PRID_IMP_R3000: 701 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 702 if (cpu_has_confreg()) { 703 c->cputype = CPU_R3081E; 704 __cpu_name[cpu] = "R3081"; 705 } else { 706 c->cputype = CPU_R3000A; 707 __cpu_name[cpu] = "R3000A"; 708 } 709 } else { 710 c->cputype = CPU_R3000; 711 __cpu_name[cpu] = "R3000"; 712 } 713 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 714 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 715 MIPS_CPU_NOFPUEX; 716 if (__cpu_has_fpu()) 717 c->options |= MIPS_CPU_FPU; 718 c->tlbsize = 64; 719 break; 720 case PRID_IMP_R4000: 721 if (read_c0_config() & CONF_SC) { 722 if ((c->processor_id & PRID_REV_MASK) >= 723 PRID_REV_R4400) { 724 c->cputype = CPU_R4400PC; 725 __cpu_name[cpu] = "R4400PC"; 726 } else { 727 c->cputype = CPU_R4000PC; 728 __cpu_name[cpu] = "R4000PC"; 729 } 730 } else { 731 int cca = read_c0_config() & CONF_CM_CMASK; 732 int mc; 733 734 /* 735 * SC and MC versions can't be reliably told apart, 736 * but only the latter support coherent caching 737 * modes so assume the firmware has set the KSEG0 738 * coherency attribute reasonably (if uncached, we 739 * assume SC). 740 */ 741 switch (cca) { 742 case CONF_CM_CACHABLE_CE: 743 case CONF_CM_CACHABLE_COW: 744 case CONF_CM_CACHABLE_CUW: 745 mc = 1; 746 break; 747 default: 748 mc = 0; 749 break; 750 } 751 if ((c->processor_id & PRID_REV_MASK) >= 752 PRID_REV_R4400) { 753 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 754 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 755 } else { 756 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 757 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 758 } 759 } 760 761 set_isa(c, MIPS_CPU_ISA_III); 762 c->fpu_msk31 |= FPU_CSR_CONDX; 763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 764 MIPS_CPU_WATCH | MIPS_CPU_VCE | 765 MIPS_CPU_LLSC; 766 c->tlbsize = 48; 767 break; 768 case PRID_IMP_VR41XX: 769 set_isa(c, MIPS_CPU_ISA_III); 770 c->fpu_msk31 |= FPU_CSR_CONDX; 771 c->options = R4K_OPTS; 772 c->tlbsize = 32; 773 switch (c->processor_id & 0xf0) { 774 case PRID_REV_VR4111: 775 c->cputype = CPU_VR4111; 776 __cpu_name[cpu] = "NEC VR4111"; 777 break; 778 case PRID_REV_VR4121: 779 c->cputype = CPU_VR4121; 780 __cpu_name[cpu] = "NEC VR4121"; 781 break; 782 case PRID_REV_VR4122: 783 if ((c->processor_id & 0xf) < 0x3) { 784 c->cputype = CPU_VR4122; 785 __cpu_name[cpu] = "NEC VR4122"; 786 } else { 787 c->cputype = CPU_VR4181A; 788 __cpu_name[cpu] = "NEC VR4181A"; 789 } 790 break; 791 case PRID_REV_VR4130: 792 if ((c->processor_id & 0xf) < 0x4) { 793 c->cputype = CPU_VR4131; 794 __cpu_name[cpu] = "NEC VR4131"; 795 } else { 796 c->cputype = CPU_VR4133; 797 c->options |= MIPS_CPU_LLSC; 798 __cpu_name[cpu] = "NEC VR4133"; 799 } 800 break; 801 default: 802 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 803 c->cputype = CPU_VR41XX; 804 __cpu_name[cpu] = "NEC Vr41xx"; 805 break; 806 } 807 break; 808 case PRID_IMP_R4300: 809 c->cputype = CPU_R4300; 810 __cpu_name[cpu] = "R4300"; 811 set_isa(c, MIPS_CPU_ISA_III); 812 c->fpu_msk31 |= FPU_CSR_CONDX; 813 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 814 MIPS_CPU_LLSC; 815 c->tlbsize = 32; 816 break; 817 case PRID_IMP_R4600: 818 c->cputype = CPU_R4600; 819 __cpu_name[cpu] = "R4600"; 820 set_isa(c, MIPS_CPU_ISA_III); 821 c->fpu_msk31 |= FPU_CSR_CONDX; 822 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 823 MIPS_CPU_LLSC; 824 c->tlbsize = 48; 825 break; 826 #if 0 827 case PRID_IMP_R4650: 828 /* 829 * This processor doesn't have an MMU, so it's not 830 * "real easy" to run Linux on it. It is left purely 831 * for documentation. Commented out because it shares 832 * it's c0_prid id number with the TX3900. 833 */ 834 c->cputype = CPU_R4650; 835 __cpu_name[cpu] = "R4650"; 836 set_isa(c, MIPS_CPU_ISA_III); 837 c->fpu_msk31 |= FPU_CSR_CONDX; 838 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 839 c->tlbsize = 48; 840 break; 841 #endif 842 case PRID_IMP_TX39: 843 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 844 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 845 846 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 847 c->cputype = CPU_TX3927; 848 __cpu_name[cpu] = "TX3927"; 849 c->tlbsize = 64; 850 } else { 851 switch (c->processor_id & PRID_REV_MASK) { 852 case PRID_REV_TX3912: 853 c->cputype = CPU_TX3912; 854 __cpu_name[cpu] = "TX3912"; 855 c->tlbsize = 32; 856 break; 857 case PRID_REV_TX3922: 858 c->cputype = CPU_TX3922; 859 __cpu_name[cpu] = "TX3922"; 860 c->tlbsize = 64; 861 break; 862 } 863 } 864 break; 865 case PRID_IMP_R4700: 866 c->cputype = CPU_R4700; 867 __cpu_name[cpu] = "R4700"; 868 set_isa(c, MIPS_CPU_ISA_III); 869 c->fpu_msk31 |= FPU_CSR_CONDX; 870 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 871 MIPS_CPU_LLSC; 872 c->tlbsize = 48; 873 break; 874 case PRID_IMP_TX49: 875 c->cputype = CPU_TX49XX; 876 __cpu_name[cpu] = "R49XX"; 877 set_isa(c, MIPS_CPU_ISA_III); 878 c->fpu_msk31 |= FPU_CSR_CONDX; 879 c->options = R4K_OPTS | MIPS_CPU_LLSC; 880 if (!(c->processor_id & 0x08)) 881 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 882 c->tlbsize = 48; 883 break; 884 case PRID_IMP_R5000: 885 c->cputype = CPU_R5000; 886 __cpu_name[cpu] = "R5000"; 887 set_isa(c, MIPS_CPU_ISA_IV); 888 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 889 MIPS_CPU_LLSC; 890 c->tlbsize = 48; 891 break; 892 case PRID_IMP_R5432: 893 c->cputype = CPU_R5432; 894 __cpu_name[cpu] = "R5432"; 895 set_isa(c, MIPS_CPU_ISA_IV); 896 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 897 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 898 c->tlbsize = 48; 899 break; 900 case PRID_IMP_R5500: 901 c->cputype = CPU_R5500; 902 __cpu_name[cpu] = "R5500"; 903 set_isa(c, MIPS_CPU_ISA_IV); 904 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 905 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 906 c->tlbsize = 48; 907 break; 908 case PRID_IMP_NEVADA: 909 c->cputype = CPU_NEVADA; 910 __cpu_name[cpu] = "Nevada"; 911 set_isa(c, MIPS_CPU_ISA_IV); 912 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 913 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 914 c->tlbsize = 48; 915 break; 916 case PRID_IMP_R6000: 917 c->cputype = CPU_R6000; 918 __cpu_name[cpu] = "R6000"; 919 set_isa(c, MIPS_CPU_ISA_II); 920 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 921 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 922 MIPS_CPU_LLSC; 923 c->tlbsize = 32; 924 break; 925 case PRID_IMP_R6000A: 926 c->cputype = CPU_R6000A; 927 __cpu_name[cpu] = "R6000A"; 928 set_isa(c, MIPS_CPU_ISA_II); 929 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 930 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 931 MIPS_CPU_LLSC; 932 c->tlbsize = 32; 933 break; 934 case PRID_IMP_RM7000: 935 c->cputype = CPU_RM7000; 936 __cpu_name[cpu] = "RM7000"; 937 set_isa(c, MIPS_CPU_ISA_IV); 938 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 939 MIPS_CPU_LLSC; 940 /* 941 * Undocumented RM7000: Bit 29 in the info register of 942 * the RM7000 v2.0 indicates if the TLB has 48 or 64 943 * entries. 944 * 945 * 29 1 => 64 entry JTLB 946 * 0 => 48 entry JTLB 947 */ 948 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 949 break; 950 case PRID_IMP_R8000: 951 c->cputype = CPU_R8000; 952 __cpu_name[cpu] = "RM8000"; 953 set_isa(c, MIPS_CPU_ISA_IV); 954 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 955 MIPS_CPU_FPU | MIPS_CPU_32FPR | 956 MIPS_CPU_LLSC; 957 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 958 break; 959 case PRID_IMP_R10000: 960 c->cputype = CPU_R10000; 961 __cpu_name[cpu] = "R10000"; 962 set_isa(c, MIPS_CPU_ISA_IV); 963 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 964 MIPS_CPU_FPU | MIPS_CPU_32FPR | 965 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 966 MIPS_CPU_LLSC; 967 c->tlbsize = 64; 968 break; 969 case PRID_IMP_R12000: 970 c->cputype = CPU_R12000; 971 __cpu_name[cpu] = "R12000"; 972 set_isa(c, MIPS_CPU_ISA_IV); 973 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 974 MIPS_CPU_FPU | MIPS_CPU_32FPR | 975 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 976 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 977 c->tlbsize = 64; 978 break; 979 case PRID_IMP_R14000: 980 if (((c->processor_id >> 4) & 0x0f) > 2) { 981 c->cputype = CPU_R16000; 982 __cpu_name[cpu] = "R16000"; 983 } else { 984 c->cputype = CPU_R14000; 985 __cpu_name[cpu] = "R14000"; 986 } 987 set_isa(c, MIPS_CPU_ISA_IV); 988 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 989 MIPS_CPU_FPU | MIPS_CPU_32FPR | 990 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 991 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 992 c->tlbsize = 64; 993 break; 994 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 995 switch (c->processor_id & PRID_REV_MASK) { 996 case PRID_REV_LOONGSON2E: 997 c->cputype = CPU_LOONGSON2; 998 __cpu_name[cpu] = "ICT Loongson-2"; 999 set_elf_platform(cpu, "loongson2e"); 1000 set_isa(c, MIPS_CPU_ISA_III); 1001 c->fpu_msk31 |= FPU_CSR_CONDX; 1002 break; 1003 case PRID_REV_LOONGSON2F: 1004 c->cputype = CPU_LOONGSON2; 1005 __cpu_name[cpu] = "ICT Loongson-2"; 1006 set_elf_platform(cpu, "loongson2f"); 1007 set_isa(c, MIPS_CPU_ISA_III); 1008 c->fpu_msk31 |= FPU_CSR_CONDX; 1009 break; 1010 case PRID_REV_LOONGSON3A: 1011 c->cputype = CPU_LOONGSON3; 1012 __cpu_name[cpu] = "ICT Loongson-3"; 1013 set_elf_platform(cpu, "loongson3a"); 1014 set_isa(c, MIPS_CPU_ISA_M64R1); 1015 break; 1016 case PRID_REV_LOONGSON3B_R1: 1017 case PRID_REV_LOONGSON3B_R2: 1018 c->cputype = CPU_LOONGSON3; 1019 __cpu_name[cpu] = "ICT Loongson-3"; 1020 set_elf_platform(cpu, "loongson3b"); 1021 set_isa(c, MIPS_CPU_ISA_M64R1); 1022 break; 1023 } 1024 1025 c->options = R4K_OPTS | 1026 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1027 MIPS_CPU_32FPR; 1028 c->tlbsize = 64; 1029 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1030 break; 1031 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1032 decode_configs(c); 1033 1034 c->cputype = CPU_LOONGSON1; 1035 1036 switch (c->processor_id & PRID_REV_MASK) { 1037 case PRID_REV_LOONGSON1B: 1038 __cpu_name[cpu] = "Loongson 1B"; 1039 break; 1040 } 1041 1042 break; 1043 } 1044 } 1045 1046 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1047 { 1048 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1049 switch (c->processor_id & PRID_IMP_MASK) { 1050 case PRID_IMP_QEMU_GENERIC: 1051 c->writecombine = _CACHE_UNCACHED; 1052 c->cputype = CPU_QEMU_GENERIC; 1053 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1054 break; 1055 case PRID_IMP_4KC: 1056 c->cputype = CPU_4KC; 1057 c->writecombine = _CACHE_UNCACHED; 1058 __cpu_name[cpu] = "MIPS 4Kc"; 1059 break; 1060 case PRID_IMP_4KEC: 1061 case PRID_IMP_4KECR2: 1062 c->cputype = CPU_4KEC; 1063 c->writecombine = _CACHE_UNCACHED; 1064 __cpu_name[cpu] = "MIPS 4KEc"; 1065 break; 1066 case PRID_IMP_4KSC: 1067 case PRID_IMP_4KSD: 1068 c->cputype = CPU_4KSC; 1069 c->writecombine = _CACHE_UNCACHED; 1070 __cpu_name[cpu] = "MIPS 4KSc"; 1071 break; 1072 case PRID_IMP_5KC: 1073 c->cputype = CPU_5KC; 1074 c->writecombine = _CACHE_UNCACHED; 1075 __cpu_name[cpu] = "MIPS 5Kc"; 1076 break; 1077 case PRID_IMP_5KE: 1078 c->cputype = CPU_5KE; 1079 c->writecombine = _CACHE_UNCACHED; 1080 __cpu_name[cpu] = "MIPS 5KE"; 1081 break; 1082 case PRID_IMP_20KC: 1083 c->cputype = CPU_20KC; 1084 c->writecombine = _CACHE_UNCACHED; 1085 __cpu_name[cpu] = "MIPS 20Kc"; 1086 break; 1087 case PRID_IMP_24K: 1088 c->cputype = CPU_24K; 1089 c->writecombine = _CACHE_UNCACHED; 1090 __cpu_name[cpu] = "MIPS 24Kc"; 1091 break; 1092 case PRID_IMP_24KE: 1093 c->cputype = CPU_24K; 1094 c->writecombine = _CACHE_UNCACHED; 1095 __cpu_name[cpu] = "MIPS 24KEc"; 1096 break; 1097 case PRID_IMP_25KF: 1098 c->cputype = CPU_25KF; 1099 c->writecombine = _CACHE_UNCACHED; 1100 __cpu_name[cpu] = "MIPS 25Kc"; 1101 break; 1102 case PRID_IMP_34K: 1103 c->cputype = CPU_34K; 1104 c->writecombine = _CACHE_UNCACHED; 1105 __cpu_name[cpu] = "MIPS 34Kc"; 1106 break; 1107 case PRID_IMP_74K: 1108 c->cputype = CPU_74K; 1109 c->writecombine = _CACHE_UNCACHED; 1110 __cpu_name[cpu] = "MIPS 74Kc"; 1111 break; 1112 case PRID_IMP_M14KC: 1113 c->cputype = CPU_M14KC; 1114 c->writecombine = _CACHE_UNCACHED; 1115 __cpu_name[cpu] = "MIPS M14Kc"; 1116 break; 1117 case PRID_IMP_M14KEC: 1118 c->cputype = CPU_M14KEC; 1119 c->writecombine = _CACHE_UNCACHED; 1120 __cpu_name[cpu] = "MIPS M14KEc"; 1121 break; 1122 case PRID_IMP_1004K: 1123 c->cputype = CPU_1004K; 1124 c->writecombine = _CACHE_UNCACHED; 1125 __cpu_name[cpu] = "MIPS 1004Kc"; 1126 break; 1127 case PRID_IMP_1074K: 1128 c->cputype = CPU_1074K; 1129 c->writecombine = _CACHE_UNCACHED; 1130 __cpu_name[cpu] = "MIPS 1074Kc"; 1131 break; 1132 case PRID_IMP_INTERAPTIV_UP: 1133 c->cputype = CPU_INTERAPTIV; 1134 __cpu_name[cpu] = "MIPS interAptiv"; 1135 break; 1136 case PRID_IMP_INTERAPTIV_MP: 1137 c->cputype = CPU_INTERAPTIV; 1138 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1139 break; 1140 case PRID_IMP_PROAPTIV_UP: 1141 c->cputype = CPU_PROAPTIV; 1142 __cpu_name[cpu] = "MIPS proAptiv"; 1143 break; 1144 case PRID_IMP_PROAPTIV_MP: 1145 c->cputype = CPU_PROAPTIV; 1146 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1147 break; 1148 case PRID_IMP_P5600: 1149 c->cputype = CPU_P5600; 1150 __cpu_name[cpu] = "MIPS P5600"; 1151 break; 1152 case PRID_IMP_I6400: 1153 c->cputype = CPU_I6400; 1154 __cpu_name[cpu] = "MIPS I6400"; 1155 break; 1156 case PRID_IMP_M5150: 1157 c->cputype = CPU_M5150; 1158 __cpu_name[cpu] = "MIPS M5150"; 1159 break; 1160 } 1161 1162 decode_configs(c); 1163 1164 spram_config(); 1165 } 1166 1167 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1168 { 1169 decode_configs(c); 1170 switch (c->processor_id & PRID_IMP_MASK) { 1171 case PRID_IMP_AU1_REV1: 1172 case PRID_IMP_AU1_REV2: 1173 c->cputype = CPU_ALCHEMY; 1174 switch ((c->processor_id >> 24) & 0xff) { 1175 case 0: 1176 __cpu_name[cpu] = "Au1000"; 1177 break; 1178 case 1: 1179 __cpu_name[cpu] = "Au1500"; 1180 break; 1181 case 2: 1182 __cpu_name[cpu] = "Au1100"; 1183 break; 1184 case 3: 1185 __cpu_name[cpu] = "Au1550"; 1186 break; 1187 case 4: 1188 __cpu_name[cpu] = "Au1200"; 1189 if ((c->processor_id & PRID_REV_MASK) == 2) 1190 __cpu_name[cpu] = "Au1250"; 1191 break; 1192 case 5: 1193 __cpu_name[cpu] = "Au1210"; 1194 break; 1195 default: 1196 __cpu_name[cpu] = "Au1xxx"; 1197 break; 1198 } 1199 break; 1200 } 1201 } 1202 1203 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1204 { 1205 decode_configs(c); 1206 1207 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1208 switch (c->processor_id & PRID_IMP_MASK) { 1209 case PRID_IMP_SB1: 1210 c->cputype = CPU_SB1; 1211 __cpu_name[cpu] = "SiByte SB1"; 1212 /* FPU in pass1 is known to have issues. */ 1213 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1214 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1215 break; 1216 case PRID_IMP_SB1A: 1217 c->cputype = CPU_SB1A; 1218 __cpu_name[cpu] = "SiByte SB1A"; 1219 break; 1220 } 1221 } 1222 1223 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1224 { 1225 decode_configs(c); 1226 switch (c->processor_id & PRID_IMP_MASK) { 1227 case PRID_IMP_SR71000: 1228 c->cputype = CPU_SR71000; 1229 __cpu_name[cpu] = "Sandcraft SR71000"; 1230 c->scache.ways = 8; 1231 c->tlbsize = 64; 1232 break; 1233 } 1234 } 1235 1236 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1237 { 1238 decode_configs(c); 1239 switch (c->processor_id & PRID_IMP_MASK) { 1240 case PRID_IMP_PR4450: 1241 c->cputype = CPU_PR4450; 1242 __cpu_name[cpu] = "Philips PR4450"; 1243 set_isa(c, MIPS_CPU_ISA_M32R1); 1244 break; 1245 } 1246 } 1247 1248 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1249 { 1250 decode_configs(c); 1251 switch (c->processor_id & PRID_IMP_MASK) { 1252 case PRID_IMP_BMIPS32_REV4: 1253 case PRID_IMP_BMIPS32_REV8: 1254 c->cputype = CPU_BMIPS32; 1255 __cpu_name[cpu] = "Broadcom BMIPS32"; 1256 set_elf_platform(cpu, "bmips32"); 1257 break; 1258 case PRID_IMP_BMIPS3300: 1259 case PRID_IMP_BMIPS3300_ALT: 1260 case PRID_IMP_BMIPS3300_BUG: 1261 c->cputype = CPU_BMIPS3300; 1262 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1263 set_elf_platform(cpu, "bmips3300"); 1264 break; 1265 case PRID_IMP_BMIPS43XX: { 1266 int rev = c->processor_id & PRID_REV_MASK; 1267 1268 if (rev >= PRID_REV_BMIPS4380_LO && 1269 rev <= PRID_REV_BMIPS4380_HI) { 1270 c->cputype = CPU_BMIPS4380; 1271 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1272 set_elf_platform(cpu, "bmips4380"); 1273 } else { 1274 c->cputype = CPU_BMIPS4350; 1275 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1276 set_elf_platform(cpu, "bmips4350"); 1277 } 1278 break; 1279 } 1280 case PRID_IMP_BMIPS5000: 1281 case PRID_IMP_BMIPS5200: 1282 c->cputype = CPU_BMIPS5000; 1283 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1284 set_elf_platform(cpu, "bmips5000"); 1285 c->options |= MIPS_CPU_ULRI; 1286 break; 1287 } 1288 } 1289 1290 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1291 { 1292 decode_configs(c); 1293 switch (c->processor_id & PRID_IMP_MASK) { 1294 case PRID_IMP_CAVIUM_CN38XX: 1295 case PRID_IMP_CAVIUM_CN31XX: 1296 case PRID_IMP_CAVIUM_CN30XX: 1297 c->cputype = CPU_CAVIUM_OCTEON; 1298 __cpu_name[cpu] = "Cavium Octeon"; 1299 goto platform; 1300 case PRID_IMP_CAVIUM_CN58XX: 1301 case PRID_IMP_CAVIUM_CN56XX: 1302 case PRID_IMP_CAVIUM_CN50XX: 1303 case PRID_IMP_CAVIUM_CN52XX: 1304 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1305 __cpu_name[cpu] = "Cavium Octeon+"; 1306 platform: 1307 set_elf_platform(cpu, "octeon"); 1308 break; 1309 case PRID_IMP_CAVIUM_CN61XX: 1310 case PRID_IMP_CAVIUM_CN63XX: 1311 case PRID_IMP_CAVIUM_CN66XX: 1312 case PRID_IMP_CAVIUM_CN68XX: 1313 case PRID_IMP_CAVIUM_CNF71XX: 1314 c->cputype = CPU_CAVIUM_OCTEON2; 1315 __cpu_name[cpu] = "Cavium Octeon II"; 1316 set_elf_platform(cpu, "octeon2"); 1317 break; 1318 case PRID_IMP_CAVIUM_CN70XX: 1319 case PRID_IMP_CAVIUM_CN78XX: 1320 c->cputype = CPU_CAVIUM_OCTEON3; 1321 __cpu_name[cpu] = "Cavium Octeon III"; 1322 set_elf_platform(cpu, "octeon3"); 1323 break; 1324 default: 1325 printk(KERN_INFO "Unknown Octeon chip!\n"); 1326 c->cputype = CPU_UNKNOWN; 1327 break; 1328 } 1329 } 1330 1331 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1332 { 1333 decode_configs(c); 1334 /* JZRISC does not implement the CP0 counter. */ 1335 c->options &= ~MIPS_CPU_COUNTER; 1336 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1337 switch (c->processor_id & PRID_IMP_MASK) { 1338 case PRID_IMP_JZRISC: 1339 c->cputype = CPU_JZRISC; 1340 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1341 __cpu_name[cpu] = "Ingenic JZRISC"; 1342 break; 1343 default: 1344 panic("Unknown Ingenic Processor ID!"); 1345 break; 1346 } 1347 } 1348 1349 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1350 { 1351 decode_configs(c); 1352 1353 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1354 c->cputype = CPU_ALCHEMY; 1355 __cpu_name[cpu] = "Au1300"; 1356 /* following stuff is not for Alchemy */ 1357 return; 1358 } 1359 1360 c->options = (MIPS_CPU_TLB | 1361 MIPS_CPU_4KEX | 1362 MIPS_CPU_COUNTER | 1363 MIPS_CPU_DIVEC | 1364 MIPS_CPU_WATCH | 1365 MIPS_CPU_EJTAG | 1366 MIPS_CPU_LLSC); 1367 1368 switch (c->processor_id & PRID_IMP_MASK) { 1369 case PRID_IMP_NETLOGIC_XLP2XX: 1370 case PRID_IMP_NETLOGIC_XLP9XX: 1371 case PRID_IMP_NETLOGIC_XLP5XX: 1372 c->cputype = CPU_XLP; 1373 __cpu_name[cpu] = "Broadcom XLPII"; 1374 break; 1375 1376 case PRID_IMP_NETLOGIC_XLP8XX: 1377 case PRID_IMP_NETLOGIC_XLP3XX: 1378 c->cputype = CPU_XLP; 1379 __cpu_name[cpu] = "Netlogic XLP"; 1380 break; 1381 1382 case PRID_IMP_NETLOGIC_XLR732: 1383 case PRID_IMP_NETLOGIC_XLR716: 1384 case PRID_IMP_NETLOGIC_XLR532: 1385 case PRID_IMP_NETLOGIC_XLR308: 1386 case PRID_IMP_NETLOGIC_XLR532C: 1387 case PRID_IMP_NETLOGIC_XLR516C: 1388 case PRID_IMP_NETLOGIC_XLR508C: 1389 case PRID_IMP_NETLOGIC_XLR308C: 1390 c->cputype = CPU_XLR; 1391 __cpu_name[cpu] = "Netlogic XLR"; 1392 break; 1393 1394 case PRID_IMP_NETLOGIC_XLS608: 1395 case PRID_IMP_NETLOGIC_XLS408: 1396 case PRID_IMP_NETLOGIC_XLS404: 1397 case PRID_IMP_NETLOGIC_XLS208: 1398 case PRID_IMP_NETLOGIC_XLS204: 1399 case PRID_IMP_NETLOGIC_XLS108: 1400 case PRID_IMP_NETLOGIC_XLS104: 1401 case PRID_IMP_NETLOGIC_XLS616B: 1402 case PRID_IMP_NETLOGIC_XLS608B: 1403 case PRID_IMP_NETLOGIC_XLS416B: 1404 case PRID_IMP_NETLOGIC_XLS412B: 1405 case PRID_IMP_NETLOGIC_XLS408B: 1406 case PRID_IMP_NETLOGIC_XLS404B: 1407 c->cputype = CPU_XLR; 1408 __cpu_name[cpu] = "Netlogic XLS"; 1409 break; 1410 1411 default: 1412 pr_info("Unknown Netlogic chip id [%02x]!\n", 1413 c->processor_id); 1414 c->cputype = CPU_XLR; 1415 break; 1416 } 1417 1418 if (c->cputype == CPU_XLP) { 1419 set_isa(c, MIPS_CPU_ISA_M64R2); 1420 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1421 /* This will be updated again after all threads are woken up */ 1422 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1423 } else { 1424 set_isa(c, MIPS_CPU_ISA_M64R1); 1425 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1426 } 1427 c->kscratch_mask = 0xf; 1428 } 1429 1430 #ifdef CONFIG_64BIT 1431 /* For use by uaccess.h */ 1432 u64 __ua_limit; 1433 EXPORT_SYMBOL(__ua_limit); 1434 #endif 1435 1436 const char *__cpu_name[NR_CPUS]; 1437 const char *__elf_platform; 1438 1439 void cpu_probe(void) 1440 { 1441 struct cpuinfo_mips *c = ¤t_cpu_data; 1442 unsigned int cpu = smp_processor_id(); 1443 1444 c->processor_id = PRID_IMP_UNKNOWN; 1445 c->fpu_id = FPIR_IMP_NONE; 1446 c->cputype = CPU_UNKNOWN; 1447 c->writecombine = _CACHE_UNCACHED; 1448 1449 c->fpu_csr31 = FPU_CSR_RN; 1450 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1451 1452 c->processor_id = read_c0_prid(); 1453 switch (c->processor_id & PRID_COMP_MASK) { 1454 case PRID_COMP_LEGACY: 1455 cpu_probe_legacy(c, cpu); 1456 break; 1457 case PRID_COMP_MIPS: 1458 cpu_probe_mips(c, cpu); 1459 break; 1460 case PRID_COMP_ALCHEMY: 1461 cpu_probe_alchemy(c, cpu); 1462 break; 1463 case PRID_COMP_SIBYTE: 1464 cpu_probe_sibyte(c, cpu); 1465 break; 1466 case PRID_COMP_BROADCOM: 1467 cpu_probe_broadcom(c, cpu); 1468 break; 1469 case PRID_COMP_SANDCRAFT: 1470 cpu_probe_sandcraft(c, cpu); 1471 break; 1472 case PRID_COMP_NXP: 1473 cpu_probe_nxp(c, cpu); 1474 break; 1475 case PRID_COMP_CAVIUM: 1476 cpu_probe_cavium(c, cpu); 1477 break; 1478 case PRID_COMP_INGENIC_D0: 1479 case PRID_COMP_INGENIC_D1: 1480 case PRID_COMP_INGENIC_E1: 1481 cpu_probe_ingenic(c, cpu); 1482 break; 1483 case PRID_COMP_NETLOGIC: 1484 cpu_probe_netlogic(c, cpu); 1485 break; 1486 } 1487 1488 BUG_ON(!__cpu_name[cpu]); 1489 BUG_ON(c->cputype == CPU_UNKNOWN); 1490 1491 /* 1492 * Platform code can force the cpu type to optimize code 1493 * generation. In that case be sure the cpu type is correctly 1494 * manually setup otherwise it could trigger some nasty bugs. 1495 */ 1496 BUG_ON(current_cpu_type() != c->cputype); 1497 1498 if (mips_fpu_disabled) 1499 c->options &= ~MIPS_CPU_FPU; 1500 1501 if (mips_dsp_disabled) 1502 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1503 1504 if (mips_htw_disabled) { 1505 c->options &= ~MIPS_CPU_HTW; 1506 write_c0_pwctl(read_c0_pwctl() & 1507 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1508 } 1509 1510 if (c->options & MIPS_CPU_FPU) 1511 cpu_set_fpu_opts(c); 1512 else 1513 cpu_set_nofpu_opts(c); 1514 1515 if (cpu_has_bp_ghist) 1516 write_c0_r10k_diag(read_c0_r10k_diag() | 1517 R10K_DIAG_E_GHIST); 1518 1519 if (cpu_has_mips_r2_r6) { 1520 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1521 /* R2 has Performance Counter Interrupt indicator */ 1522 c->options |= MIPS_CPU_PCI; 1523 } 1524 else 1525 c->srsets = 1; 1526 1527 if (cpu_has_mips_r6) 1528 elf_hwcap |= HWCAP_MIPS_R6; 1529 1530 if (cpu_has_msa) { 1531 c->msa_id = cpu_get_msa_id(); 1532 WARN(c->msa_id & MSA_IR_WRPF, 1533 "Vector register partitioning unimplemented!"); 1534 elf_hwcap |= HWCAP_MIPS_MSA; 1535 } 1536 1537 cpu_probe_vmbits(c); 1538 1539 #ifdef CONFIG_64BIT 1540 if (cpu == 0) 1541 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1542 #endif 1543 } 1544 1545 void cpu_report(void) 1546 { 1547 struct cpuinfo_mips *c = ¤t_cpu_data; 1548 1549 pr_info("CPU%d revision is: %08x (%s)\n", 1550 smp_processor_id(), c->processor_id, cpu_name_string()); 1551 if (c->options & MIPS_CPU_FPU) 1552 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1553 if (cpu_has_msa) 1554 pr_info("MSA revision is: %08x\n", c->msa_id); 1555 } 1556