1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <asm/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 38 /* 39 * Get the FPU Implementation/Revision. 40 */ 41 static inline unsigned long cpu_get_fpu_id(void) 42 { 43 unsigned long tmp, fpu_id; 44 45 tmp = read_c0_status(); 46 __enable_fpu(FPU_AS_IS); 47 fpu_id = read_32bit_cp1_register(CP1_REVISION); 48 write_c0_status(tmp); 49 return fpu_id; 50 } 51 52 /* 53 * Check if the CPU has an external FPU. 54 */ 55 static inline int __cpu_has_fpu(void) 56 { 57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 58 } 59 60 static inline unsigned long cpu_get_msa_id(void) 61 { 62 unsigned long status, msa_id; 63 64 status = read_c0_status(); 65 __enable_fpu(FPU_64BIT); 66 enable_msa(); 67 msa_id = read_msa_ir(); 68 disable_msa(); 69 write_c0_status(status); 70 return msa_id; 71 } 72 73 /* 74 * Determine the FCSR mask for FPU hardware. 75 */ 76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 77 { 78 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 79 80 fcsr = c->fpu_csr31; 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 82 83 sr = read_c0_status(); 84 __enable_fpu(FPU_AS_IS); 85 86 fcsr0 = fcsr & mask; 87 write_32bit_cp1_register(CP1_STATUS, fcsr0); 88 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 89 90 fcsr1 = fcsr | ~mask; 91 write_32bit_cp1_register(CP1_STATUS, fcsr1); 92 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 93 94 write_32bit_cp1_register(CP1_STATUS, fcsr); 95 96 write_c0_status(sr); 97 98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 99 } 100 101 /* 102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 103 * supported by FPU hardware. 104 */ 105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 106 { 107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 110 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 111 112 sr = read_c0_status(); 113 __enable_fpu(FPU_AS_IS); 114 115 fir = read_32bit_cp1_register(CP1_REVISION); 116 if (fir & MIPS_FPIR_HAS2008) { 117 fcsr = read_32bit_cp1_register(CP1_STATUS); 118 119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 120 write_32bit_cp1_register(CP1_STATUS, fcsr0); 121 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 122 123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 124 write_32bit_cp1_register(CP1_STATUS, fcsr1); 125 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 126 127 write_32bit_cp1_register(CP1_STATUS, fcsr); 128 129 if (!(fcsr0 & FPU_CSR_NAN2008)) 130 c->options |= MIPS_CPU_NAN_LEGACY; 131 if (fcsr1 & FPU_CSR_NAN2008) 132 c->options |= MIPS_CPU_NAN_2008; 133 134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 135 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 136 else 137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 138 139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 140 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 141 else 142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 143 } else { 144 c->options |= MIPS_CPU_NAN_LEGACY; 145 } 146 147 write_c0_status(sr); 148 } else { 149 c->options |= MIPS_CPU_NAN_LEGACY; 150 } 151 } 152 153 /* 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 155 * ABS.fmt/NEG.fmt execution mode. 156 */ 157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 158 159 /* 160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 161 * to support by the FPU emulator according to the IEEE 754 conformance 162 * mode selected. Note that "relaxed" straps the emulator so that it 163 * allows 2008-NaN binaries even for legacy processors. 164 */ 165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 166 { 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 171 switch (ieee754) { 172 case STRICT: 173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 177 } else { 178 c->options |= MIPS_CPU_NAN_LEGACY; 179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 180 } 181 break; 182 case LEGACY: 183 c->options |= MIPS_CPU_NAN_LEGACY; 184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 185 break; 186 case STD2008: 187 c->options |= MIPS_CPU_NAN_2008; 188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 break; 191 case RELAXED: 192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 193 break; 194 } 195 } 196 197 /* 198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 199 * according to the "ieee754=" parameter. 200 */ 201 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 202 { 203 switch (ieee754) { 204 case STRICT: 205 mips_use_nan_legacy = !!cpu_has_nan_legacy; 206 mips_use_nan_2008 = !!cpu_has_nan_2008; 207 break; 208 case LEGACY: 209 mips_use_nan_legacy = !!cpu_has_nan_legacy; 210 mips_use_nan_2008 = !cpu_has_nan_legacy; 211 break; 212 case STD2008: 213 mips_use_nan_legacy = !cpu_has_nan_2008; 214 mips_use_nan_2008 = !!cpu_has_nan_2008; 215 break; 216 case RELAXED: 217 mips_use_nan_legacy = true; 218 mips_use_nan_2008 = true; 219 break; 220 } 221 } 222 223 /* 224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 225 * settings: 226 * 227 * strict: accept binaries that request a NaN encoding supported by the FPU 228 * legacy: only accept legacy-NaN binaries 229 * 2008: only accept 2008-NaN binaries 230 * relaxed: accept any binaries regardless of whether supported by the FPU 231 */ 232 static int __init ieee754_setup(char *s) 233 { 234 if (!s) 235 return -1; 236 else if (!strcmp(s, "strict")) 237 ieee754 = STRICT; 238 else if (!strcmp(s, "legacy")) 239 ieee754 = LEGACY; 240 else if (!strcmp(s, "2008")) 241 ieee754 = STD2008; 242 else if (!strcmp(s, "relaxed")) 243 ieee754 = RELAXED; 244 else 245 return -1; 246 247 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 248 cpu_set_nofpu_2008(&boot_cpu_data); 249 cpu_set_nan_2008(&boot_cpu_data); 250 251 return 0; 252 } 253 254 early_param("ieee754", ieee754_setup); 255 256 /* 257 * Set the FIR feature flags for the FPU emulator. 258 */ 259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 260 { 261 u32 value; 262 263 value = 0; 264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 267 value |= MIPS_FPIR_D | MIPS_FPIR_S; 268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 271 if (c->options & MIPS_CPU_NAN_2008) 272 value |= MIPS_FPIR_HAS2008; 273 c->fpu_id = value; 274 } 275 276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 277 static unsigned int mips_nofpu_msk31; 278 279 /* 280 * Set options for FPU hardware. 281 */ 282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 283 { 284 c->fpu_id = cpu_get_fpu_id(); 285 mips_nofpu_msk31 = c->fpu_msk31; 286 287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 290 if (c->fpu_id & MIPS_FPIR_3D) 291 c->ases |= MIPS_ASE_MIPS3D; 292 if (c->fpu_id & MIPS_FPIR_FREP) 293 c->options |= MIPS_CPU_FRE; 294 } 295 296 cpu_set_fpu_fcsr_mask(c); 297 cpu_set_fpu_2008(c); 298 cpu_set_nan_2008(c); 299 } 300 301 /* 302 * Set options for the FPU emulator. 303 */ 304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 305 { 306 c->options &= ~MIPS_CPU_FPU; 307 c->fpu_msk31 = mips_nofpu_msk31; 308 309 cpu_set_nofpu_2008(c); 310 cpu_set_nan_2008(c); 311 cpu_set_nofpu_id(c); 312 } 313 314 static int mips_fpu_disabled; 315 316 static int __init fpu_disable(char *s) 317 { 318 cpu_set_nofpu_opts(&boot_cpu_data); 319 mips_fpu_disabled = 1; 320 321 return 1; 322 } 323 324 __setup("nofpu", fpu_disable); 325 326 int mips_dsp_disabled; 327 328 static int __init dsp_disable(char *s) 329 { 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 331 mips_dsp_disabled = 1; 332 333 return 1; 334 } 335 336 __setup("nodsp", dsp_disable); 337 338 static int mips_htw_disabled; 339 340 static int __init htw_disable(char *s) 341 { 342 mips_htw_disabled = 1; 343 cpu_data[0].options &= ~MIPS_CPU_HTW; 344 write_c0_pwctl(read_c0_pwctl() & 345 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 346 347 return 1; 348 } 349 350 __setup("nohtw", htw_disable); 351 352 static int mips_ftlb_disabled; 353 static int mips_has_ftlb_configured; 354 355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable); 356 357 static int __init ftlb_disable(char *s) 358 { 359 unsigned int config4, mmuextdef; 360 361 /* 362 * If the core hasn't done any FTLB configuration, there is nothing 363 * for us to do here. 364 */ 365 if (!mips_has_ftlb_configured) 366 return 1; 367 368 /* Disable it in the boot cpu */ 369 if (set_ftlb_enable(&cpu_data[0], 0)) { 370 pr_warn("Can't turn FTLB off\n"); 371 return 1; 372 } 373 374 back_to_back_c0_hazard(); 375 376 config4 = read_c0_config4(); 377 378 /* Check that FTLB has been disabled */ 379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 382 /* This should never happen */ 383 pr_warn("FTLB could not be disabled!\n"); 384 return 1; 385 } 386 387 mips_ftlb_disabled = 1; 388 mips_has_ftlb_configured = 0; 389 390 /* 391 * noftlb is mainly used for debug purposes so print 392 * an informative message instead of using pr_debug() 393 */ 394 pr_info("FTLB has been disabled\n"); 395 396 /* 397 * Some of these bits are duplicated in the decode_config4. 398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 399 * once FTLB has been disabled so undo what decode_config4 did. 400 */ 401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 402 cpu_data[0].tlbsizeftlbsets; 403 cpu_data[0].tlbsizeftlbsets = 0; 404 cpu_data[0].tlbsizeftlbways = 0; 405 406 return 1; 407 } 408 409 __setup("noftlb", ftlb_disable); 410 411 412 static inline void check_errata(void) 413 { 414 struct cpuinfo_mips *c = ¤t_cpu_data; 415 416 switch (current_cpu_type()) { 417 case CPU_34K: 418 /* 419 * Erratum "RPS May Cause Incorrect Instruction Execution" 420 * This code only handles VPE0, any SMP/RTOS code 421 * making use of VPE1 will be responsable for that VPE. 422 */ 423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 425 break; 426 default: 427 break; 428 } 429 } 430 431 void __init check_bugs32(void) 432 { 433 check_errata(); 434 } 435 436 /* 437 * Probe whether cpu has config register by trying to play with 438 * alternate cache bit and see whether it matters. 439 * It's used by cpu_probe to distinguish between R3000A and R3081. 440 */ 441 static inline int cpu_has_confreg(void) 442 { 443 #ifdef CONFIG_CPU_R3000 444 extern unsigned long r3k_cache_size(unsigned long); 445 unsigned long size1, size2; 446 unsigned long cfg = read_c0_conf(); 447 448 size1 = r3k_cache_size(ST0_ISC); 449 write_c0_conf(cfg ^ R30XX_CONF_AC); 450 size2 = r3k_cache_size(ST0_ISC); 451 write_c0_conf(cfg); 452 return size1 != size2; 453 #else 454 return 0; 455 #endif 456 } 457 458 static inline void set_elf_platform(int cpu, const char *plat) 459 { 460 if (cpu == 0) 461 __elf_platform = plat; 462 } 463 464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 465 { 466 #ifdef __NEED_VMBITS_PROBE 467 write_c0_entryhi(0x3fffffffffffe000ULL); 468 back_to_back_c0_hazard(); 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 470 #endif 471 } 472 473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 474 { 475 switch (isa) { 476 case MIPS_CPU_ISA_M64R2: 477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 478 case MIPS_CPU_ISA_M64R1: 479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 480 case MIPS_CPU_ISA_V: 481 c->isa_level |= MIPS_CPU_ISA_V; 482 case MIPS_CPU_ISA_IV: 483 c->isa_level |= MIPS_CPU_ISA_IV; 484 case MIPS_CPU_ISA_III: 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 486 break; 487 488 /* R6 incompatible with everything else */ 489 case MIPS_CPU_ISA_M64R6: 490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 491 case MIPS_CPU_ISA_M32R6: 492 c->isa_level |= MIPS_CPU_ISA_M32R6; 493 /* Break here so we don't add incompatible ISAs */ 494 break; 495 case MIPS_CPU_ISA_M32R2: 496 c->isa_level |= MIPS_CPU_ISA_M32R2; 497 case MIPS_CPU_ISA_M32R1: 498 c->isa_level |= MIPS_CPU_ISA_M32R1; 499 case MIPS_CPU_ISA_II: 500 c->isa_level |= MIPS_CPU_ISA_II; 501 break; 502 } 503 } 504 505 static char unknown_isa[] = KERN_ERR \ 506 "Unsupported ISA type, c0.config0: %d."; 507 508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 509 { 510 511 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 512 513 /* 514 * 0 = All TLBWR instructions go to FTLB 515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 516 * FTLB and 1 goes to the VTLB. 517 * 2 = 7:1: As above with 7:1 ratio. 518 * 3 = 3:1: As above with 3:1 ratio. 519 * 520 * Use the linear midpoint as the probability threshold. 521 */ 522 if (probability >= 12) 523 return 1; 524 else if (probability >= 6) 525 return 2; 526 else 527 /* 528 * So FTLB is less than 4 times bigger than VTLB. 529 * A 3:1 ratio can still be useful though. 530 */ 531 return 3; 532 } 533 534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) 535 { 536 unsigned int config; 537 538 /* It's implementation dependent how the FTLB can be enabled */ 539 switch (c->cputype) { 540 case CPU_PROAPTIV: 541 case CPU_P5600: 542 /* proAptiv & related cores use Config6 to enable the FTLB */ 543 config = read_c0_config6(); 544 /* Clear the old probability value */ 545 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 546 if (enable) 547 /* Enable FTLB */ 548 write_c0_config6(config | 549 (calculate_ftlb_probability(c) 550 << MIPS_CONF6_FTLBP_SHIFT) 551 | MIPS_CONF6_FTLBEN); 552 else 553 /* Disable FTLB */ 554 write_c0_config6(config & ~MIPS_CONF6_FTLBEN); 555 break; 556 case CPU_I6400: 557 /* I6400 & related cores use Config7 to configure FTLB */ 558 config = read_c0_config7(); 559 /* Clear the old probability value */ 560 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT); 561 write_c0_config7(config | (calculate_ftlb_probability(c) 562 << MIPS_CONF7_FTLBP_SHIFT)); 563 break; 564 default: 565 return 1; 566 } 567 568 return 0; 569 } 570 571 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 572 { 573 unsigned int config0; 574 int isa, mt; 575 576 config0 = read_c0_config(); 577 578 /* 579 * Look for Standard TLB or Dual VTLB and FTLB 580 */ 581 mt = config0 & MIPS_CONF_MT; 582 if (mt == MIPS_CONF_MT_TLB) 583 c->options |= MIPS_CPU_TLB; 584 else if (mt == MIPS_CONF_MT_FTLB) 585 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 586 587 isa = (config0 & MIPS_CONF_AT) >> 13; 588 switch (isa) { 589 case 0: 590 switch ((config0 & MIPS_CONF_AR) >> 10) { 591 case 0: 592 set_isa(c, MIPS_CPU_ISA_M32R1); 593 break; 594 case 1: 595 set_isa(c, MIPS_CPU_ISA_M32R2); 596 break; 597 case 2: 598 set_isa(c, MIPS_CPU_ISA_M32R6); 599 break; 600 default: 601 goto unknown; 602 } 603 break; 604 case 2: 605 switch ((config0 & MIPS_CONF_AR) >> 10) { 606 case 0: 607 set_isa(c, MIPS_CPU_ISA_M64R1); 608 break; 609 case 1: 610 set_isa(c, MIPS_CPU_ISA_M64R2); 611 break; 612 case 2: 613 set_isa(c, MIPS_CPU_ISA_M64R6); 614 break; 615 default: 616 goto unknown; 617 } 618 break; 619 default: 620 goto unknown; 621 } 622 623 return config0 & MIPS_CONF_M; 624 625 unknown: 626 panic(unknown_isa, config0); 627 } 628 629 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 630 { 631 unsigned int config1; 632 633 config1 = read_c0_config1(); 634 635 if (config1 & MIPS_CONF1_MD) 636 c->ases |= MIPS_ASE_MDMX; 637 if (config1 & MIPS_CONF1_WR) 638 c->options |= MIPS_CPU_WATCH; 639 if (config1 & MIPS_CONF1_CA) 640 c->ases |= MIPS_ASE_MIPS16; 641 if (config1 & MIPS_CONF1_EP) 642 c->options |= MIPS_CPU_EJTAG; 643 if (config1 & MIPS_CONF1_FP) { 644 c->options |= MIPS_CPU_FPU; 645 c->options |= MIPS_CPU_32FPR; 646 } 647 if (cpu_has_tlb) { 648 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 649 c->tlbsizevtlb = c->tlbsize; 650 c->tlbsizeftlbsets = 0; 651 } 652 653 return config1 & MIPS_CONF_M; 654 } 655 656 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 657 { 658 unsigned int config2; 659 660 config2 = read_c0_config2(); 661 662 if (config2 & MIPS_CONF2_SL) 663 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 664 665 return config2 & MIPS_CONF_M; 666 } 667 668 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 669 { 670 unsigned int config3; 671 672 config3 = read_c0_config3(); 673 674 if (config3 & MIPS_CONF3_SM) { 675 c->ases |= MIPS_ASE_SMARTMIPS; 676 c->options |= MIPS_CPU_RIXI; 677 } 678 if (config3 & MIPS_CONF3_RXI) 679 c->options |= MIPS_CPU_RIXI; 680 if (config3 & MIPS_CONF3_DSP) 681 c->ases |= MIPS_ASE_DSP; 682 if (config3 & MIPS_CONF3_DSP2P) 683 c->ases |= MIPS_ASE_DSP2P; 684 if (config3 & MIPS_CONF3_VINT) 685 c->options |= MIPS_CPU_VINT; 686 if (config3 & MIPS_CONF3_VEIC) 687 c->options |= MIPS_CPU_VEIC; 688 if (config3 & MIPS_CONF3_MT) 689 c->ases |= MIPS_ASE_MIPSMT; 690 if (config3 & MIPS_CONF3_ULRI) 691 c->options |= MIPS_CPU_ULRI; 692 if (config3 & MIPS_CONF3_ISA) 693 c->options |= MIPS_CPU_MICROMIPS; 694 if (config3 & MIPS_CONF3_VZ) 695 c->ases |= MIPS_ASE_VZ; 696 if (config3 & MIPS_CONF3_SC) 697 c->options |= MIPS_CPU_SEGMENTS; 698 if (config3 & MIPS_CONF3_MSA) 699 c->ases |= MIPS_ASE_MSA; 700 if (config3 & MIPS_CONF3_PW) { 701 c->htw_seq = 0; 702 c->options |= MIPS_CPU_HTW; 703 } 704 if (config3 & MIPS_CONF3_CDMM) 705 c->options |= MIPS_CPU_CDMM; 706 if (config3 & MIPS_CONF3_SP) 707 c->options |= MIPS_CPU_SP; 708 709 return config3 & MIPS_CONF_M; 710 } 711 712 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 713 { 714 unsigned int config4; 715 unsigned int newcf4; 716 unsigned int mmuextdef; 717 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 718 719 config4 = read_c0_config4(); 720 721 if (cpu_has_tlb) { 722 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 723 c->options |= MIPS_CPU_TLBINV; 724 725 /* 726 * R6 has dropped the MMUExtDef field from config4. 727 * On R6 the fields always describe the FTLB, and only if it is 728 * present according to Config.MT. 729 */ 730 if (!cpu_has_mips_r6) 731 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 732 else if (cpu_has_ftlb) 733 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 734 else 735 mmuextdef = 0; 736 737 switch (mmuextdef) { 738 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 739 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 740 c->tlbsizevtlb = c->tlbsize; 741 break; 742 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 743 c->tlbsizevtlb += 744 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 745 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 746 c->tlbsize = c->tlbsizevtlb; 747 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 748 /* fall through */ 749 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 750 if (mips_ftlb_disabled) 751 break; 752 newcf4 = (config4 & ~ftlb_page) | 753 (page_size_ftlb(mmuextdef) << 754 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 755 write_c0_config4(newcf4); 756 back_to_back_c0_hazard(); 757 config4 = read_c0_config4(); 758 if (config4 != newcf4) { 759 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 760 PAGE_SIZE, config4); 761 /* Switch FTLB off */ 762 set_ftlb_enable(c, 0); 763 break; 764 } 765 c->tlbsizeftlbsets = 1 << 766 ((config4 & MIPS_CONF4_FTLBSETS) >> 767 MIPS_CONF4_FTLBSETS_SHIFT); 768 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 769 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 770 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 771 mips_has_ftlb_configured = 1; 772 break; 773 } 774 } 775 776 c->kscratch_mask = (config4 >> 16) & 0xff; 777 778 return config4 & MIPS_CONF_M; 779 } 780 781 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 782 { 783 unsigned int config5; 784 785 config5 = read_c0_config5(); 786 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 787 write_c0_config5(config5); 788 789 if (config5 & MIPS_CONF5_EVA) 790 c->options |= MIPS_CPU_EVA; 791 if (config5 & MIPS_CONF5_MRP) 792 c->options |= MIPS_CPU_MAAR; 793 if (config5 & MIPS_CONF5_LLB) 794 c->options |= MIPS_CPU_RW_LLB; 795 #ifdef CONFIG_XPA 796 if (config5 & MIPS_CONF5_MVH) 797 c->options |= MIPS_CPU_XPA; 798 #endif 799 800 return config5 & MIPS_CONF_M; 801 } 802 803 static void decode_configs(struct cpuinfo_mips *c) 804 { 805 int ok; 806 807 /* MIPS32 or MIPS64 compliant CPU. */ 808 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 809 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 810 811 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 812 813 /* Enable FTLB if present and not disabled */ 814 set_ftlb_enable(c, !mips_ftlb_disabled); 815 816 ok = decode_config0(c); /* Read Config registers. */ 817 BUG_ON(!ok); /* Arch spec violation! */ 818 if (ok) 819 ok = decode_config1(c); 820 if (ok) 821 ok = decode_config2(c); 822 if (ok) 823 ok = decode_config3(c); 824 if (ok) 825 ok = decode_config4(c); 826 if (ok) 827 ok = decode_config5(c); 828 829 mips_probe_watch_registers(c); 830 831 if (cpu_has_rixi) { 832 /* Enable the RIXI exceptions */ 833 set_c0_pagegrain(PG_IEC); 834 back_to_back_c0_hazard(); 835 /* Verify the IEC bit is set */ 836 if (read_c0_pagegrain() & PG_IEC) 837 c->options |= MIPS_CPU_RIXIEX; 838 } 839 840 #ifndef CONFIG_MIPS_CPS 841 if (cpu_has_mips_r2_r6) { 842 c->core = get_ebase_cpunum(); 843 if (cpu_has_mipsmt) 844 c->core >>= fls(core_nvpes()) - 1; 845 } 846 #endif 847 } 848 849 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 850 | MIPS_CPU_COUNTER) 851 852 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 853 { 854 switch (c->processor_id & PRID_IMP_MASK) { 855 case PRID_IMP_R2000: 856 c->cputype = CPU_R2000; 857 __cpu_name[cpu] = "R2000"; 858 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 859 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 860 MIPS_CPU_NOFPUEX; 861 if (__cpu_has_fpu()) 862 c->options |= MIPS_CPU_FPU; 863 c->tlbsize = 64; 864 break; 865 case PRID_IMP_R3000: 866 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 867 if (cpu_has_confreg()) { 868 c->cputype = CPU_R3081E; 869 __cpu_name[cpu] = "R3081"; 870 } else { 871 c->cputype = CPU_R3000A; 872 __cpu_name[cpu] = "R3000A"; 873 } 874 } else { 875 c->cputype = CPU_R3000; 876 __cpu_name[cpu] = "R3000"; 877 } 878 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 879 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 880 MIPS_CPU_NOFPUEX; 881 if (__cpu_has_fpu()) 882 c->options |= MIPS_CPU_FPU; 883 c->tlbsize = 64; 884 break; 885 case PRID_IMP_R4000: 886 if (read_c0_config() & CONF_SC) { 887 if ((c->processor_id & PRID_REV_MASK) >= 888 PRID_REV_R4400) { 889 c->cputype = CPU_R4400PC; 890 __cpu_name[cpu] = "R4400PC"; 891 } else { 892 c->cputype = CPU_R4000PC; 893 __cpu_name[cpu] = "R4000PC"; 894 } 895 } else { 896 int cca = read_c0_config() & CONF_CM_CMASK; 897 int mc; 898 899 /* 900 * SC and MC versions can't be reliably told apart, 901 * but only the latter support coherent caching 902 * modes so assume the firmware has set the KSEG0 903 * coherency attribute reasonably (if uncached, we 904 * assume SC). 905 */ 906 switch (cca) { 907 case CONF_CM_CACHABLE_CE: 908 case CONF_CM_CACHABLE_COW: 909 case CONF_CM_CACHABLE_CUW: 910 mc = 1; 911 break; 912 default: 913 mc = 0; 914 break; 915 } 916 if ((c->processor_id & PRID_REV_MASK) >= 917 PRID_REV_R4400) { 918 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 919 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 920 } else { 921 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 922 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 923 } 924 } 925 926 set_isa(c, MIPS_CPU_ISA_III); 927 c->fpu_msk31 |= FPU_CSR_CONDX; 928 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 929 MIPS_CPU_WATCH | MIPS_CPU_VCE | 930 MIPS_CPU_LLSC; 931 c->tlbsize = 48; 932 break; 933 case PRID_IMP_VR41XX: 934 set_isa(c, MIPS_CPU_ISA_III); 935 c->fpu_msk31 |= FPU_CSR_CONDX; 936 c->options = R4K_OPTS; 937 c->tlbsize = 32; 938 switch (c->processor_id & 0xf0) { 939 case PRID_REV_VR4111: 940 c->cputype = CPU_VR4111; 941 __cpu_name[cpu] = "NEC VR4111"; 942 break; 943 case PRID_REV_VR4121: 944 c->cputype = CPU_VR4121; 945 __cpu_name[cpu] = "NEC VR4121"; 946 break; 947 case PRID_REV_VR4122: 948 if ((c->processor_id & 0xf) < 0x3) { 949 c->cputype = CPU_VR4122; 950 __cpu_name[cpu] = "NEC VR4122"; 951 } else { 952 c->cputype = CPU_VR4181A; 953 __cpu_name[cpu] = "NEC VR4181A"; 954 } 955 break; 956 case PRID_REV_VR4130: 957 if ((c->processor_id & 0xf) < 0x4) { 958 c->cputype = CPU_VR4131; 959 __cpu_name[cpu] = "NEC VR4131"; 960 } else { 961 c->cputype = CPU_VR4133; 962 c->options |= MIPS_CPU_LLSC; 963 __cpu_name[cpu] = "NEC VR4133"; 964 } 965 break; 966 default: 967 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 968 c->cputype = CPU_VR41XX; 969 __cpu_name[cpu] = "NEC Vr41xx"; 970 break; 971 } 972 break; 973 case PRID_IMP_R4300: 974 c->cputype = CPU_R4300; 975 __cpu_name[cpu] = "R4300"; 976 set_isa(c, MIPS_CPU_ISA_III); 977 c->fpu_msk31 |= FPU_CSR_CONDX; 978 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 979 MIPS_CPU_LLSC; 980 c->tlbsize = 32; 981 break; 982 case PRID_IMP_R4600: 983 c->cputype = CPU_R4600; 984 __cpu_name[cpu] = "R4600"; 985 set_isa(c, MIPS_CPU_ISA_III); 986 c->fpu_msk31 |= FPU_CSR_CONDX; 987 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 988 MIPS_CPU_LLSC; 989 c->tlbsize = 48; 990 break; 991 #if 0 992 case PRID_IMP_R4650: 993 /* 994 * This processor doesn't have an MMU, so it's not 995 * "real easy" to run Linux on it. It is left purely 996 * for documentation. Commented out because it shares 997 * it's c0_prid id number with the TX3900. 998 */ 999 c->cputype = CPU_R4650; 1000 __cpu_name[cpu] = "R4650"; 1001 set_isa(c, MIPS_CPU_ISA_III); 1002 c->fpu_msk31 |= FPU_CSR_CONDX; 1003 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1004 c->tlbsize = 48; 1005 break; 1006 #endif 1007 case PRID_IMP_TX39: 1008 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1009 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1010 1011 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1012 c->cputype = CPU_TX3927; 1013 __cpu_name[cpu] = "TX3927"; 1014 c->tlbsize = 64; 1015 } else { 1016 switch (c->processor_id & PRID_REV_MASK) { 1017 case PRID_REV_TX3912: 1018 c->cputype = CPU_TX3912; 1019 __cpu_name[cpu] = "TX3912"; 1020 c->tlbsize = 32; 1021 break; 1022 case PRID_REV_TX3922: 1023 c->cputype = CPU_TX3922; 1024 __cpu_name[cpu] = "TX3922"; 1025 c->tlbsize = 64; 1026 break; 1027 } 1028 } 1029 break; 1030 case PRID_IMP_R4700: 1031 c->cputype = CPU_R4700; 1032 __cpu_name[cpu] = "R4700"; 1033 set_isa(c, MIPS_CPU_ISA_III); 1034 c->fpu_msk31 |= FPU_CSR_CONDX; 1035 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1036 MIPS_CPU_LLSC; 1037 c->tlbsize = 48; 1038 break; 1039 case PRID_IMP_TX49: 1040 c->cputype = CPU_TX49XX; 1041 __cpu_name[cpu] = "R49XX"; 1042 set_isa(c, MIPS_CPU_ISA_III); 1043 c->fpu_msk31 |= FPU_CSR_CONDX; 1044 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1045 if (!(c->processor_id & 0x08)) 1046 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1047 c->tlbsize = 48; 1048 break; 1049 case PRID_IMP_R5000: 1050 c->cputype = CPU_R5000; 1051 __cpu_name[cpu] = "R5000"; 1052 set_isa(c, MIPS_CPU_ISA_IV); 1053 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1054 MIPS_CPU_LLSC; 1055 c->tlbsize = 48; 1056 break; 1057 case PRID_IMP_R5432: 1058 c->cputype = CPU_R5432; 1059 __cpu_name[cpu] = "R5432"; 1060 set_isa(c, MIPS_CPU_ISA_IV); 1061 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1062 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1063 c->tlbsize = 48; 1064 break; 1065 case PRID_IMP_R5500: 1066 c->cputype = CPU_R5500; 1067 __cpu_name[cpu] = "R5500"; 1068 set_isa(c, MIPS_CPU_ISA_IV); 1069 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1070 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1071 c->tlbsize = 48; 1072 break; 1073 case PRID_IMP_NEVADA: 1074 c->cputype = CPU_NEVADA; 1075 __cpu_name[cpu] = "Nevada"; 1076 set_isa(c, MIPS_CPU_ISA_IV); 1077 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1078 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1079 c->tlbsize = 48; 1080 break; 1081 case PRID_IMP_R6000: 1082 c->cputype = CPU_R6000; 1083 __cpu_name[cpu] = "R6000"; 1084 set_isa(c, MIPS_CPU_ISA_II); 1085 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1086 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1087 MIPS_CPU_LLSC; 1088 c->tlbsize = 32; 1089 break; 1090 case PRID_IMP_R6000A: 1091 c->cputype = CPU_R6000A; 1092 __cpu_name[cpu] = "R6000A"; 1093 set_isa(c, MIPS_CPU_ISA_II); 1094 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1095 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1096 MIPS_CPU_LLSC; 1097 c->tlbsize = 32; 1098 break; 1099 case PRID_IMP_RM7000: 1100 c->cputype = CPU_RM7000; 1101 __cpu_name[cpu] = "RM7000"; 1102 set_isa(c, MIPS_CPU_ISA_IV); 1103 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1104 MIPS_CPU_LLSC; 1105 /* 1106 * Undocumented RM7000: Bit 29 in the info register of 1107 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1108 * entries. 1109 * 1110 * 29 1 => 64 entry JTLB 1111 * 0 => 48 entry JTLB 1112 */ 1113 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1114 break; 1115 case PRID_IMP_R8000: 1116 c->cputype = CPU_R8000; 1117 __cpu_name[cpu] = "RM8000"; 1118 set_isa(c, MIPS_CPU_ISA_IV); 1119 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 1120 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1121 MIPS_CPU_LLSC; 1122 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 1123 break; 1124 case PRID_IMP_R10000: 1125 c->cputype = CPU_R10000; 1126 __cpu_name[cpu] = "R10000"; 1127 set_isa(c, MIPS_CPU_ISA_IV); 1128 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1129 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1130 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1131 MIPS_CPU_LLSC; 1132 c->tlbsize = 64; 1133 break; 1134 case PRID_IMP_R12000: 1135 c->cputype = CPU_R12000; 1136 __cpu_name[cpu] = "R12000"; 1137 set_isa(c, MIPS_CPU_ISA_IV); 1138 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1139 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1140 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1141 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1142 c->tlbsize = 64; 1143 break; 1144 case PRID_IMP_R14000: 1145 if (((c->processor_id >> 4) & 0x0f) > 2) { 1146 c->cputype = CPU_R16000; 1147 __cpu_name[cpu] = "R16000"; 1148 } else { 1149 c->cputype = CPU_R14000; 1150 __cpu_name[cpu] = "R14000"; 1151 } 1152 set_isa(c, MIPS_CPU_ISA_IV); 1153 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1154 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1155 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1156 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1157 c->tlbsize = 64; 1158 break; 1159 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1160 switch (c->processor_id & PRID_REV_MASK) { 1161 case PRID_REV_LOONGSON2E: 1162 c->cputype = CPU_LOONGSON2; 1163 __cpu_name[cpu] = "ICT Loongson-2"; 1164 set_elf_platform(cpu, "loongson2e"); 1165 set_isa(c, MIPS_CPU_ISA_III); 1166 c->fpu_msk31 |= FPU_CSR_CONDX; 1167 break; 1168 case PRID_REV_LOONGSON2F: 1169 c->cputype = CPU_LOONGSON2; 1170 __cpu_name[cpu] = "ICT Loongson-2"; 1171 set_elf_platform(cpu, "loongson2f"); 1172 set_isa(c, MIPS_CPU_ISA_III); 1173 c->fpu_msk31 |= FPU_CSR_CONDX; 1174 break; 1175 case PRID_REV_LOONGSON3A: 1176 c->cputype = CPU_LOONGSON3; 1177 __cpu_name[cpu] = "ICT Loongson-3"; 1178 set_elf_platform(cpu, "loongson3a"); 1179 set_isa(c, MIPS_CPU_ISA_M64R1); 1180 break; 1181 case PRID_REV_LOONGSON3B_R1: 1182 case PRID_REV_LOONGSON3B_R2: 1183 c->cputype = CPU_LOONGSON3; 1184 __cpu_name[cpu] = "ICT Loongson-3"; 1185 set_elf_platform(cpu, "loongson3b"); 1186 set_isa(c, MIPS_CPU_ISA_M64R1); 1187 break; 1188 } 1189 1190 c->options = R4K_OPTS | 1191 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1192 MIPS_CPU_32FPR; 1193 c->tlbsize = 64; 1194 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1195 break; 1196 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1197 decode_configs(c); 1198 1199 c->cputype = CPU_LOONGSON1; 1200 1201 switch (c->processor_id & PRID_REV_MASK) { 1202 case PRID_REV_LOONGSON1B: 1203 __cpu_name[cpu] = "Loongson 1B"; 1204 break; 1205 } 1206 1207 break; 1208 } 1209 } 1210 1211 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1212 { 1213 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1214 switch (c->processor_id & PRID_IMP_MASK) { 1215 case PRID_IMP_QEMU_GENERIC: 1216 c->writecombine = _CACHE_UNCACHED; 1217 c->cputype = CPU_QEMU_GENERIC; 1218 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1219 break; 1220 case PRID_IMP_4KC: 1221 c->cputype = CPU_4KC; 1222 c->writecombine = _CACHE_UNCACHED; 1223 __cpu_name[cpu] = "MIPS 4Kc"; 1224 break; 1225 case PRID_IMP_4KEC: 1226 case PRID_IMP_4KECR2: 1227 c->cputype = CPU_4KEC; 1228 c->writecombine = _CACHE_UNCACHED; 1229 __cpu_name[cpu] = "MIPS 4KEc"; 1230 break; 1231 case PRID_IMP_4KSC: 1232 case PRID_IMP_4KSD: 1233 c->cputype = CPU_4KSC; 1234 c->writecombine = _CACHE_UNCACHED; 1235 __cpu_name[cpu] = "MIPS 4KSc"; 1236 break; 1237 case PRID_IMP_5KC: 1238 c->cputype = CPU_5KC; 1239 c->writecombine = _CACHE_UNCACHED; 1240 __cpu_name[cpu] = "MIPS 5Kc"; 1241 break; 1242 case PRID_IMP_5KE: 1243 c->cputype = CPU_5KE; 1244 c->writecombine = _CACHE_UNCACHED; 1245 __cpu_name[cpu] = "MIPS 5KE"; 1246 break; 1247 case PRID_IMP_20KC: 1248 c->cputype = CPU_20KC; 1249 c->writecombine = _CACHE_UNCACHED; 1250 __cpu_name[cpu] = "MIPS 20Kc"; 1251 break; 1252 case PRID_IMP_24K: 1253 c->cputype = CPU_24K; 1254 c->writecombine = _CACHE_UNCACHED; 1255 __cpu_name[cpu] = "MIPS 24Kc"; 1256 break; 1257 case PRID_IMP_24KE: 1258 c->cputype = CPU_24K; 1259 c->writecombine = _CACHE_UNCACHED; 1260 __cpu_name[cpu] = "MIPS 24KEc"; 1261 break; 1262 case PRID_IMP_25KF: 1263 c->cputype = CPU_25KF; 1264 c->writecombine = _CACHE_UNCACHED; 1265 __cpu_name[cpu] = "MIPS 25Kc"; 1266 break; 1267 case PRID_IMP_34K: 1268 c->cputype = CPU_34K; 1269 c->writecombine = _CACHE_UNCACHED; 1270 __cpu_name[cpu] = "MIPS 34Kc"; 1271 break; 1272 case PRID_IMP_74K: 1273 c->cputype = CPU_74K; 1274 c->writecombine = _CACHE_UNCACHED; 1275 __cpu_name[cpu] = "MIPS 74Kc"; 1276 break; 1277 case PRID_IMP_M14KC: 1278 c->cputype = CPU_M14KC; 1279 c->writecombine = _CACHE_UNCACHED; 1280 __cpu_name[cpu] = "MIPS M14Kc"; 1281 break; 1282 case PRID_IMP_M14KEC: 1283 c->cputype = CPU_M14KEC; 1284 c->writecombine = _CACHE_UNCACHED; 1285 __cpu_name[cpu] = "MIPS M14KEc"; 1286 break; 1287 case PRID_IMP_1004K: 1288 c->cputype = CPU_1004K; 1289 c->writecombine = _CACHE_UNCACHED; 1290 __cpu_name[cpu] = "MIPS 1004Kc"; 1291 break; 1292 case PRID_IMP_1074K: 1293 c->cputype = CPU_1074K; 1294 c->writecombine = _CACHE_UNCACHED; 1295 __cpu_name[cpu] = "MIPS 1074Kc"; 1296 break; 1297 case PRID_IMP_INTERAPTIV_UP: 1298 c->cputype = CPU_INTERAPTIV; 1299 __cpu_name[cpu] = "MIPS interAptiv"; 1300 break; 1301 case PRID_IMP_INTERAPTIV_MP: 1302 c->cputype = CPU_INTERAPTIV; 1303 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1304 break; 1305 case PRID_IMP_PROAPTIV_UP: 1306 c->cputype = CPU_PROAPTIV; 1307 __cpu_name[cpu] = "MIPS proAptiv"; 1308 break; 1309 case PRID_IMP_PROAPTIV_MP: 1310 c->cputype = CPU_PROAPTIV; 1311 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1312 break; 1313 case PRID_IMP_P5600: 1314 c->cputype = CPU_P5600; 1315 __cpu_name[cpu] = "MIPS P5600"; 1316 break; 1317 case PRID_IMP_I6400: 1318 c->cputype = CPU_I6400; 1319 __cpu_name[cpu] = "MIPS I6400"; 1320 break; 1321 case PRID_IMP_M5150: 1322 c->cputype = CPU_M5150; 1323 __cpu_name[cpu] = "MIPS M5150"; 1324 break; 1325 } 1326 1327 decode_configs(c); 1328 1329 spram_config(); 1330 } 1331 1332 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1333 { 1334 decode_configs(c); 1335 switch (c->processor_id & PRID_IMP_MASK) { 1336 case PRID_IMP_AU1_REV1: 1337 case PRID_IMP_AU1_REV2: 1338 c->cputype = CPU_ALCHEMY; 1339 switch ((c->processor_id >> 24) & 0xff) { 1340 case 0: 1341 __cpu_name[cpu] = "Au1000"; 1342 break; 1343 case 1: 1344 __cpu_name[cpu] = "Au1500"; 1345 break; 1346 case 2: 1347 __cpu_name[cpu] = "Au1100"; 1348 break; 1349 case 3: 1350 __cpu_name[cpu] = "Au1550"; 1351 break; 1352 case 4: 1353 __cpu_name[cpu] = "Au1200"; 1354 if ((c->processor_id & PRID_REV_MASK) == 2) 1355 __cpu_name[cpu] = "Au1250"; 1356 break; 1357 case 5: 1358 __cpu_name[cpu] = "Au1210"; 1359 break; 1360 default: 1361 __cpu_name[cpu] = "Au1xxx"; 1362 break; 1363 } 1364 break; 1365 } 1366 } 1367 1368 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1369 { 1370 decode_configs(c); 1371 1372 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1373 switch (c->processor_id & PRID_IMP_MASK) { 1374 case PRID_IMP_SB1: 1375 c->cputype = CPU_SB1; 1376 __cpu_name[cpu] = "SiByte SB1"; 1377 /* FPU in pass1 is known to have issues. */ 1378 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1379 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1380 break; 1381 case PRID_IMP_SB1A: 1382 c->cputype = CPU_SB1A; 1383 __cpu_name[cpu] = "SiByte SB1A"; 1384 break; 1385 } 1386 } 1387 1388 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1389 { 1390 decode_configs(c); 1391 switch (c->processor_id & PRID_IMP_MASK) { 1392 case PRID_IMP_SR71000: 1393 c->cputype = CPU_SR71000; 1394 __cpu_name[cpu] = "Sandcraft SR71000"; 1395 c->scache.ways = 8; 1396 c->tlbsize = 64; 1397 break; 1398 } 1399 } 1400 1401 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1402 { 1403 decode_configs(c); 1404 switch (c->processor_id & PRID_IMP_MASK) { 1405 case PRID_IMP_PR4450: 1406 c->cputype = CPU_PR4450; 1407 __cpu_name[cpu] = "Philips PR4450"; 1408 set_isa(c, MIPS_CPU_ISA_M32R1); 1409 break; 1410 } 1411 } 1412 1413 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1414 { 1415 decode_configs(c); 1416 switch (c->processor_id & PRID_IMP_MASK) { 1417 case PRID_IMP_BMIPS32_REV4: 1418 case PRID_IMP_BMIPS32_REV8: 1419 c->cputype = CPU_BMIPS32; 1420 __cpu_name[cpu] = "Broadcom BMIPS32"; 1421 set_elf_platform(cpu, "bmips32"); 1422 break; 1423 case PRID_IMP_BMIPS3300: 1424 case PRID_IMP_BMIPS3300_ALT: 1425 case PRID_IMP_BMIPS3300_BUG: 1426 c->cputype = CPU_BMIPS3300; 1427 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1428 set_elf_platform(cpu, "bmips3300"); 1429 break; 1430 case PRID_IMP_BMIPS43XX: { 1431 int rev = c->processor_id & PRID_REV_MASK; 1432 1433 if (rev >= PRID_REV_BMIPS4380_LO && 1434 rev <= PRID_REV_BMIPS4380_HI) { 1435 c->cputype = CPU_BMIPS4380; 1436 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1437 set_elf_platform(cpu, "bmips4380"); 1438 } else { 1439 c->cputype = CPU_BMIPS4350; 1440 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1441 set_elf_platform(cpu, "bmips4350"); 1442 } 1443 break; 1444 } 1445 case PRID_IMP_BMIPS5000: 1446 case PRID_IMP_BMIPS5200: 1447 c->cputype = CPU_BMIPS5000; 1448 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1449 set_elf_platform(cpu, "bmips5000"); 1450 c->options |= MIPS_CPU_ULRI; 1451 break; 1452 } 1453 } 1454 1455 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1456 { 1457 decode_configs(c); 1458 switch (c->processor_id & PRID_IMP_MASK) { 1459 case PRID_IMP_CAVIUM_CN38XX: 1460 case PRID_IMP_CAVIUM_CN31XX: 1461 case PRID_IMP_CAVIUM_CN30XX: 1462 c->cputype = CPU_CAVIUM_OCTEON; 1463 __cpu_name[cpu] = "Cavium Octeon"; 1464 goto platform; 1465 case PRID_IMP_CAVIUM_CN58XX: 1466 case PRID_IMP_CAVIUM_CN56XX: 1467 case PRID_IMP_CAVIUM_CN50XX: 1468 case PRID_IMP_CAVIUM_CN52XX: 1469 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1470 __cpu_name[cpu] = "Cavium Octeon+"; 1471 platform: 1472 set_elf_platform(cpu, "octeon"); 1473 break; 1474 case PRID_IMP_CAVIUM_CN61XX: 1475 case PRID_IMP_CAVIUM_CN63XX: 1476 case PRID_IMP_CAVIUM_CN66XX: 1477 case PRID_IMP_CAVIUM_CN68XX: 1478 case PRID_IMP_CAVIUM_CNF71XX: 1479 c->cputype = CPU_CAVIUM_OCTEON2; 1480 __cpu_name[cpu] = "Cavium Octeon II"; 1481 set_elf_platform(cpu, "octeon2"); 1482 break; 1483 case PRID_IMP_CAVIUM_CN70XX: 1484 case PRID_IMP_CAVIUM_CN78XX: 1485 c->cputype = CPU_CAVIUM_OCTEON3; 1486 __cpu_name[cpu] = "Cavium Octeon III"; 1487 set_elf_platform(cpu, "octeon3"); 1488 break; 1489 default: 1490 printk(KERN_INFO "Unknown Octeon chip!\n"); 1491 c->cputype = CPU_UNKNOWN; 1492 break; 1493 } 1494 } 1495 1496 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1497 { 1498 decode_configs(c); 1499 /* JZRISC does not implement the CP0 counter. */ 1500 c->options &= ~MIPS_CPU_COUNTER; 1501 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1502 switch (c->processor_id & PRID_IMP_MASK) { 1503 case PRID_IMP_JZRISC: 1504 c->cputype = CPU_JZRISC; 1505 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1506 __cpu_name[cpu] = "Ingenic JZRISC"; 1507 break; 1508 default: 1509 panic("Unknown Ingenic Processor ID!"); 1510 break; 1511 } 1512 } 1513 1514 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1515 { 1516 decode_configs(c); 1517 1518 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1519 c->cputype = CPU_ALCHEMY; 1520 __cpu_name[cpu] = "Au1300"; 1521 /* following stuff is not for Alchemy */ 1522 return; 1523 } 1524 1525 c->options = (MIPS_CPU_TLB | 1526 MIPS_CPU_4KEX | 1527 MIPS_CPU_COUNTER | 1528 MIPS_CPU_DIVEC | 1529 MIPS_CPU_WATCH | 1530 MIPS_CPU_EJTAG | 1531 MIPS_CPU_LLSC); 1532 1533 switch (c->processor_id & PRID_IMP_MASK) { 1534 case PRID_IMP_NETLOGIC_XLP2XX: 1535 case PRID_IMP_NETLOGIC_XLP9XX: 1536 case PRID_IMP_NETLOGIC_XLP5XX: 1537 c->cputype = CPU_XLP; 1538 __cpu_name[cpu] = "Broadcom XLPII"; 1539 break; 1540 1541 case PRID_IMP_NETLOGIC_XLP8XX: 1542 case PRID_IMP_NETLOGIC_XLP3XX: 1543 c->cputype = CPU_XLP; 1544 __cpu_name[cpu] = "Netlogic XLP"; 1545 break; 1546 1547 case PRID_IMP_NETLOGIC_XLR732: 1548 case PRID_IMP_NETLOGIC_XLR716: 1549 case PRID_IMP_NETLOGIC_XLR532: 1550 case PRID_IMP_NETLOGIC_XLR308: 1551 case PRID_IMP_NETLOGIC_XLR532C: 1552 case PRID_IMP_NETLOGIC_XLR516C: 1553 case PRID_IMP_NETLOGIC_XLR508C: 1554 case PRID_IMP_NETLOGIC_XLR308C: 1555 c->cputype = CPU_XLR; 1556 __cpu_name[cpu] = "Netlogic XLR"; 1557 break; 1558 1559 case PRID_IMP_NETLOGIC_XLS608: 1560 case PRID_IMP_NETLOGIC_XLS408: 1561 case PRID_IMP_NETLOGIC_XLS404: 1562 case PRID_IMP_NETLOGIC_XLS208: 1563 case PRID_IMP_NETLOGIC_XLS204: 1564 case PRID_IMP_NETLOGIC_XLS108: 1565 case PRID_IMP_NETLOGIC_XLS104: 1566 case PRID_IMP_NETLOGIC_XLS616B: 1567 case PRID_IMP_NETLOGIC_XLS608B: 1568 case PRID_IMP_NETLOGIC_XLS416B: 1569 case PRID_IMP_NETLOGIC_XLS412B: 1570 case PRID_IMP_NETLOGIC_XLS408B: 1571 case PRID_IMP_NETLOGIC_XLS404B: 1572 c->cputype = CPU_XLR; 1573 __cpu_name[cpu] = "Netlogic XLS"; 1574 break; 1575 1576 default: 1577 pr_info("Unknown Netlogic chip id [%02x]!\n", 1578 c->processor_id); 1579 c->cputype = CPU_XLR; 1580 break; 1581 } 1582 1583 if (c->cputype == CPU_XLP) { 1584 set_isa(c, MIPS_CPU_ISA_M64R2); 1585 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1586 /* This will be updated again after all threads are woken up */ 1587 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1588 } else { 1589 set_isa(c, MIPS_CPU_ISA_M64R1); 1590 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1591 } 1592 c->kscratch_mask = 0xf; 1593 } 1594 1595 #ifdef CONFIG_64BIT 1596 /* For use by uaccess.h */ 1597 u64 __ua_limit; 1598 EXPORT_SYMBOL(__ua_limit); 1599 #endif 1600 1601 const char *__cpu_name[NR_CPUS]; 1602 const char *__elf_platform; 1603 1604 void cpu_probe(void) 1605 { 1606 struct cpuinfo_mips *c = ¤t_cpu_data; 1607 unsigned int cpu = smp_processor_id(); 1608 1609 c->processor_id = PRID_IMP_UNKNOWN; 1610 c->fpu_id = FPIR_IMP_NONE; 1611 c->cputype = CPU_UNKNOWN; 1612 c->writecombine = _CACHE_UNCACHED; 1613 1614 c->fpu_csr31 = FPU_CSR_RN; 1615 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1616 1617 c->processor_id = read_c0_prid(); 1618 switch (c->processor_id & PRID_COMP_MASK) { 1619 case PRID_COMP_LEGACY: 1620 cpu_probe_legacy(c, cpu); 1621 break; 1622 case PRID_COMP_MIPS: 1623 cpu_probe_mips(c, cpu); 1624 break; 1625 case PRID_COMP_ALCHEMY: 1626 cpu_probe_alchemy(c, cpu); 1627 break; 1628 case PRID_COMP_SIBYTE: 1629 cpu_probe_sibyte(c, cpu); 1630 break; 1631 case PRID_COMP_BROADCOM: 1632 cpu_probe_broadcom(c, cpu); 1633 break; 1634 case PRID_COMP_SANDCRAFT: 1635 cpu_probe_sandcraft(c, cpu); 1636 break; 1637 case PRID_COMP_NXP: 1638 cpu_probe_nxp(c, cpu); 1639 break; 1640 case PRID_COMP_CAVIUM: 1641 cpu_probe_cavium(c, cpu); 1642 break; 1643 case PRID_COMP_INGENIC_D0: 1644 case PRID_COMP_INGENIC_D1: 1645 case PRID_COMP_INGENIC_E1: 1646 cpu_probe_ingenic(c, cpu); 1647 break; 1648 case PRID_COMP_NETLOGIC: 1649 cpu_probe_netlogic(c, cpu); 1650 break; 1651 } 1652 1653 BUG_ON(!__cpu_name[cpu]); 1654 BUG_ON(c->cputype == CPU_UNKNOWN); 1655 1656 /* 1657 * Platform code can force the cpu type to optimize code 1658 * generation. In that case be sure the cpu type is correctly 1659 * manually setup otherwise it could trigger some nasty bugs. 1660 */ 1661 BUG_ON(current_cpu_type() != c->cputype); 1662 1663 if (mips_fpu_disabled) 1664 c->options &= ~MIPS_CPU_FPU; 1665 1666 if (mips_dsp_disabled) 1667 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1668 1669 if (mips_htw_disabled) { 1670 c->options &= ~MIPS_CPU_HTW; 1671 write_c0_pwctl(read_c0_pwctl() & 1672 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1673 } 1674 1675 if (c->options & MIPS_CPU_FPU) 1676 cpu_set_fpu_opts(c); 1677 else 1678 cpu_set_nofpu_opts(c); 1679 1680 if (cpu_has_bp_ghist) 1681 write_c0_r10k_diag(read_c0_r10k_diag() | 1682 R10K_DIAG_E_GHIST); 1683 1684 if (cpu_has_mips_r2_r6) { 1685 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1686 /* R2 has Performance Counter Interrupt indicator */ 1687 c->options |= MIPS_CPU_PCI; 1688 } 1689 else 1690 c->srsets = 1; 1691 1692 if (cpu_has_mips_r6) 1693 elf_hwcap |= HWCAP_MIPS_R6; 1694 1695 if (cpu_has_msa) { 1696 c->msa_id = cpu_get_msa_id(); 1697 WARN(c->msa_id & MSA_IR_WRPF, 1698 "Vector register partitioning unimplemented!"); 1699 elf_hwcap |= HWCAP_MIPS_MSA; 1700 } 1701 1702 cpu_probe_vmbits(c); 1703 1704 #ifdef CONFIG_64BIT 1705 if (cpu == 0) 1706 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1707 #endif 1708 } 1709 1710 void cpu_report(void) 1711 { 1712 struct cpuinfo_mips *c = ¤t_cpu_data; 1713 1714 pr_info("CPU%d revision is: %08x (%s)\n", 1715 smp_processor_id(), c->processor_id, cpu_name_string()); 1716 if (c->options & MIPS_CPU_FPU) 1717 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1718 if (cpu_has_msa) 1719 pr_info("MSA revision is: %08x\n", c->msa_id); 1720 } 1721