1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <asm/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 38 /* 39 * Get the FPU Implementation/Revision. 40 */ 41 static inline unsigned long cpu_get_fpu_id(void) 42 { 43 unsigned long tmp, fpu_id; 44 45 tmp = read_c0_status(); 46 __enable_fpu(FPU_AS_IS); 47 fpu_id = read_32bit_cp1_register(CP1_REVISION); 48 write_c0_status(tmp); 49 return fpu_id; 50 } 51 52 /* 53 * Check if the CPU has an external FPU. 54 */ 55 static inline int __cpu_has_fpu(void) 56 { 57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 58 } 59 60 static inline unsigned long cpu_get_msa_id(void) 61 { 62 unsigned long status, msa_id; 63 64 status = read_c0_status(); 65 __enable_fpu(FPU_64BIT); 66 enable_msa(); 67 msa_id = read_msa_ir(); 68 disable_msa(); 69 write_c0_status(status); 70 return msa_id; 71 } 72 73 /* 74 * Determine the FCSR mask for FPU hardware. 75 */ 76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 77 { 78 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 79 80 fcsr = c->fpu_csr31; 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 82 83 sr = read_c0_status(); 84 __enable_fpu(FPU_AS_IS); 85 86 fcsr0 = fcsr & mask; 87 write_32bit_cp1_register(CP1_STATUS, fcsr0); 88 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 89 90 fcsr1 = fcsr | ~mask; 91 write_32bit_cp1_register(CP1_STATUS, fcsr1); 92 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 93 94 write_32bit_cp1_register(CP1_STATUS, fcsr); 95 96 write_c0_status(sr); 97 98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 99 } 100 101 /* 102 * Set the FIR feature flags for the FPU emulator. 103 */ 104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 105 { 106 u32 value; 107 108 value = 0; 109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 112 value |= MIPS_FPIR_D | MIPS_FPIR_S; 113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 116 c->fpu_id = value; 117 } 118 119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 120 static unsigned int mips_nofpu_msk31; 121 122 /* 123 * Set options for FPU hardware. 124 */ 125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 126 { 127 c->fpu_id = cpu_get_fpu_id(); 128 mips_nofpu_msk31 = c->fpu_msk31; 129 130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 133 if (c->fpu_id & MIPS_FPIR_3D) 134 c->ases |= MIPS_ASE_MIPS3D; 135 if (c->fpu_id & MIPS_FPIR_FREP) 136 c->options |= MIPS_CPU_FRE; 137 } 138 139 cpu_set_fpu_fcsr_mask(c); 140 } 141 142 /* 143 * Set options for the FPU emulator. 144 */ 145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 146 { 147 c->options &= ~MIPS_CPU_FPU; 148 c->fpu_msk31 = mips_nofpu_msk31; 149 150 cpu_set_nofpu_id(c); 151 } 152 153 static int mips_fpu_disabled; 154 155 static int __init fpu_disable(char *s) 156 { 157 cpu_set_nofpu_opts(&boot_cpu_data); 158 mips_fpu_disabled = 1; 159 160 return 1; 161 } 162 163 __setup("nofpu", fpu_disable); 164 165 int mips_dsp_disabled; 166 167 static int __init dsp_disable(char *s) 168 { 169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 170 mips_dsp_disabled = 1; 171 172 return 1; 173 } 174 175 __setup("nodsp", dsp_disable); 176 177 static int mips_htw_disabled; 178 179 static int __init htw_disable(char *s) 180 { 181 mips_htw_disabled = 1; 182 cpu_data[0].options &= ~MIPS_CPU_HTW; 183 write_c0_pwctl(read_c0_pwctl() & 184 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 185 186 return 1; 187 } 188 189 __setup("nohtw", htw_disable); 190 191 static int mips_ftlb_disabled; 192 static int mips_has_ftlb_configured; 193 194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable); 195 196 static int __init ftlb_disable(char *s) 197 { 198 unsigned int config4, mmuextdef; 199 200 /* 201 * If the core hasn't done any FTLB configuration, there is nothing 202 * for us to do here. 203 */ 204 if (!mips_has_ftlb_configured) 205 return 1; 206 207 /* Disable it in the boot cpu */ 208 if (set_ftlb_enable(&cpu_data[0], 0)) { 209 pr_warn("Can't turn FTLB off\n"); 210 return 1; 211 } 212 213 back_to_back_c0_hazard(); 214 215 config4 = read_c0_config4(); 216 217 /* Check that FTLB has been disabled */ 218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 221 /* This should never happen */ 222 pr_warn("FTLB could not be disabled!\n"); 223 return 1; 224 } 225 226 mips_ftlb_disabled = 1; 227 mips_has_ftlb_configured = 0; 228 229 /* 230 * noftlb is mainly used for debug purposes so print 231 * an informative message instead of using pr_debug() 232 */ 233 pr_info("FTLB has been disabled\n"); 234 235 /* 236 * Some of these bits are duplicated in the decode_config4. 237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 238 * once FTLB has been disabled so undo what decode_config4 did. 239 */ 240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 241 cpu_data[0].tlbsizeftlbsets; 242 cpu_data[0].tlbsizeftlbsets = 0; 243 cpu_data[0].tlbsizeftlbways = 0; 244 245 return 1; 246 } 247 248 __setup("noftlb", ftlb_disable); 249 250 251 static inline void check_errata(void) 252 { 253 struct cpuinfo_mips *c = ¤t_cpu_data; 254 255 switch (current_cpu_type()) { 256 case CPU_34K: 257 /* 258 * Erratum "RPS May Cause Incorrect Instruction Execution" 259 * This code only handles VPE0, any SMP/RTOS code 260 * making use of VPE1 will be responsable for that VPE. 261 */ 262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 264 break; 265 default: 266 break; 267 } 268 } 269 270 void __init check_bugs32(void) 271 { 272 check_errata(); 273 } 274 275 /* 276 * Probe whether cpu has config register by trying to play with 277 * alternate cache bit and see whether it matters. 278 * It's used by cpu_probe to distinguish between R3000A and R3081. 279 */ 280 static inline int cpu_has_confreg(void) 281 { 282 #ifdef CONFIG_CPU_R3000 283 extern unsigned long r3k_cache_size(unsigned long); 284 unsigned long size1, size2; 285 unsigned long cfg = read_c0_conf(); 286 287 size1 = r3k_cache_size(ST0_ISC); 288 write_c0_conf(cfg ^ R30XX_CONF_AC); 289 size2 = r3k_cache_size(ST0_ISC); 290 write_c0_conf(cfg); 291 return size1 != size2; 292 #else 293 return 0; 294 #endif 295 } 296 297 static inline void set_elf_platform(int cpu, const char *plat) 298 { 299 if (cpu == 0) 300 __elf_platform = plat; 301 } 302 303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 304 { 305 #ifdef __NEED_VMBITS_PROBE 306 write_c0_entryhi(0x3fffffffffffe000ULL); 307 back_to_back_c0_hazard(); 308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 309 #endif 310 } 311 312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 313 { 314 switch (isa) { 315 case MIPS_CPU_ISA_M64R2: 316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 317 case MIPS_CPU_ISA_M64R1: 318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 319 case MIPS_CPU_ISA_V: 320 c->isa_level |= MIPS_CPU_ISA_V; 321 case MIPS_CPU_ISA_IV: 322 c->isa_level |= MIPS_CPU_ISA_IV; 323 case MIPS_CPU_ISA_III: 324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 325 break; 326 327 /* R6 incompatible with everything else */ 328 case MIPS_CPU_ISA_M64R6: 329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 330 case MIPS_CPU_ISA_M32R6: 331 c->isa_level |= MIPS_CPU_ISA_M32R6; 332 /* Break here so we don't add incompatible ISAs */ 333 break; 334 case MIPS_CPU_ISA_M32R2: 335 c->isa_level |= MIPS_CPU_ISA_M32R2; 336 case MIPS_CPU_ISA_M32R1: 337 c->isa_level |= MIPS_CPU_ISA_M32R1; 338 case MIPS_CPU_ISA_II: 339 c->isa_level |= MIPS_CPU_ISA_II; 340 break; 341 } 342 } 343 344 static char unknown_isa[] = KERN_ERR \ 345 "Unsupported ISA type, c0.config0: %d."; 346 347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 348 { 349 350 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 351 352 /* 353 * 0 = All TLBWR instructions go to FTLB 354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 355 * FTLB and 1 goes to the VTLB. 356 * 2 = 7:1: As above with 7:1 ratio. 357 * 3 = 3:1: As above with 3:1 ratio. 358 * 359 * Use the linear midpoint as the probability threshold. 360 */ 361 if (probability >= 12) 362 return 1; 363 else if (probability >= 6) 364 return 2; 365 else 366 /* 367 * So FTLB is less than 4 times bigger than VTLB. 368 * A 3:1 ratio can still be useful though. 369 */ 370 return 3; 371 } 372 373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) 374 { 375 unsigned int config; 376 377 /* It's implementation dependent how the FTLB can be enabled */ 378 switch (c->cputype) { 379 case CPU_PROAPTIV: 380 case CPU_P5600: 381 /* proAptiv & related cores use Config6 to enable the FTLB */ 382 config = read_c0_config6(); 383 /* Clear the old probability value */ 384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 385 if (enable) 386 /* Enable FTLB */ 387 write_c0_config6(config | 388 (calculate_ftlb_probability(c) 389 << MIPS_CONF6_FTLBP_SHIFT) 390 | MIPS_CONF6_FTLBEN); 391 else 392 /* Disable FTLB */ 393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN); 394 break; 395 case CPU_I6400: 396 /* I6400 & related cores use Config7 to configure FTLB */ 397 config = read_c0_config7(); 398 /* Clear the old probability value */ 399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT); 400 write_c0_config7(config | (calculate_ftlb_probability(c) 401 << MIPS_CONF7_FTLBP_SHIFT)); 402 break; 403 default: 404 return 1; 405 } 406 407 return 0; 408 } 409 410 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 411 { 412 unsigned int config0; 413 int isa, mt; 414 415 config0 = read_c0_config(); 416 417 /* 418 * Look for Standard TLB or Dual VTLB and FTLB 419 */ 420 mt = config0 & MIPS_CONF_MT; 421 if (mt == MIPS_CONF_MT_TLB) 422 c->options |= MIPS_CPU_TLB; 423 else if (mt == MIPS_CONF_MT_FTLB) 424 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 425 426 isa = (config0 & MIPS_CONF_AT) >> 13; 427 switch (isa) { 428 case 0: 429 switch ((config0 & MIPS_CONF_AR) >> 10) { 430 case 0: 431 set_isa(c, MIPS_CPU_ISA_M32R1); 432 break; 433 case 1: 434 set_isa(c, MIPS_CPU_ISA_M32R2); 435 break; 436 case 2: 437 set_isa(c, MIPS_CPU_ISA_M32R6); 438 break; 439 default: 440 goto unknown; 441 } 442 break; 443 case 2: 444 switch ((config0 & MIPS_CONF_AR) >> 10) { 445 case 0: 446 set_isa(c, MIPS_CPU_ISA_M64R1); 447 break; 448 case 1: 449 set_isa(c, MIPS_CPU_ISA_M64R2); 450 break; 451 case 2: 452 set_isa(c, MIPS_CPU_ISA_M64R6); 453 break; 454 default: 455 goto unknown; 456 } 457 break; 458 default: 459 goto unknown; 460 } 461 462 return config0 & MIPS_CONF_M; 463 464 unknown: 465 panic(unknown_isa, config0); 466 } 467 468 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 469 { 470 unsigned int config1; 471 472 config1 = read_c0_config1(); 473 474 if (config1 & MIPS_CONF1_MD) 475 c->ases |= MIPS_ASE_MDMX; 476 if (config1 & MIPS_CONF1_WR) 477 c->options |= MIPS_CPU_WATCH; 478 if (config1 & MIPS_CONF1_CA) 479 c->ases |= MIPS_ASE_MIPS16; 480 if (config1 & MIPS_CONF1_EP) 481 c->options |= MIPS_CPU_EJTAG; 482 if (config1 & MIPS_CONF1_FP) { 483 c->options |= MIPS_CPU_FPU; 484 c->options |= MIPS_CPU_32FPR; 485 } 486 if (cpu_has_tlb) { 487 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 488 c->tlbsizevtlb = c->tlbsize; 489 c->tlbsizeftlbsets = 0; 490 } 491 492 return config1 & MIPS_CONF_M; 493 } 494 495 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 496 { 497 unsigned int config2; 498 499 config2 = read_c0_config2(); 500 501 if (config2 & MIPS_CONF2_SL) 502 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 503 504 return config2 & MIPS_CONF_M; 505 } 506 507 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 508 { 509 unsigned int config3; 510 511 config3 = read_c0_config3(); 512 513 if (config3 & MIPS_CONF3_SM) { 514 c->ases |= MIPS_ASE_SMARTMIPS; 515 c->options |= MIPS_CPU_RIXI; 516 } 517 if (config3 & MIPS_CONF3_RXI) 518 c->options |= MIPS_CPU_RIXI; 519 if (config3 & MIPS_CONF3_DSP) 520 c->ases |= MIPS_ASE_DSP; 521 if (config3 & MIPS_CONF3_DSP2P) 522 c->ases |= MIPS_ASE_DSP2P; 523 if (config3 & MIPS_CONF3_VINT) 524 c->options |= MIPS_CPU_VINT; 525 if (config3 & MIPS_CONF3_VEIC) 526 c->options |= MIPS_CPU_VEIC; 527 if (config3 & MIPS_CONF3_MT) 528 c->ases |= MIPS_ASE_MIPSMT; 529 if (config3 & MIPS_CONF3_ULRI) 530 c->options |= MIPS_CPU_ULRI; 531 if (config3 & MIPS_CONF3_ISA) 532 c->options |= MIPS_CPU_MICROMIPS; 533 if (config3 & MIPS_CONF3_VZ) 534 c->ases |= MIPS_ASE_VZ; 535 if (config3 & MIPS_CONF3_SC) 536 c->options |= MIPS_CPU_SEGMENTS; 537 if (config3 & MIPS_CONF3_MSA) 538 c->ases |= MIPS_ASE_MSA; 539 /* Only tested on 32-bit cores */ 540 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { 541 c->htw_seq = 0; 542 c->options |= MIPS_CPU_HTW; 543 } 544 if (config3 & MIPS_CONF3_CDMM) 545 c->options |= MIPS_CPU_CDMM; 546 if (config3 & MIPS_CONF3_SP) 547 c->options |= MIPS_CPU_SP; 548 549 return config3 & MIPS_CONF_M; 550 } 551 552 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 553 { 554 unsigned int config4; 555 unsigned int newcf4; 556 unsigned int mmuextdef; 557 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 558 559 config4 = read_c0_config4(); 560 561 if (cpu_has_tlb) { 562 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 563 c->options |= MIPS_CPU_TLBINV; 564 565 /* 566 * R6 has dropped the MMUExtDef field from config4. 567 * On R6 the fields always describe the FTLB, and only if it is 568 * present according to Config.MT. 569 */ 570 if (!cpu_has_mips_r6) 571 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 572 else if (cpu_has_ftlb) 573 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 574 else 575 mmuextdef = 0; 576 577 switch (mmuextdef) { 578 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 579 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 580 c->tlbsizevtlb = c->tlbsize; 581 break; 582 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 583 c->tlbsizevtlb += 584 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 585 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 586 c->tlbsize = c->tlbsizevtlb; 587 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 588 /* fall through */ 589 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 590 if (mips_ftlb_disabled) 591 break; 592 newcf4 = (config4 & ~ftlb_page) | 593 (page_size_ftlb(mmuextdef) << 594 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 595 write_c0_config4(newcf4); 596 back_to_back_c0_hazard(); 597 config4 = read_c0_config4(); 598 if (config4 != newcf4) { 599 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 600 PAGE_SIZE, config4); 601 /* Switch FTLB off */ 602 set_ftlb_enable(c, 0); 603 break; 604 } 605 c->tlbsizeftlbsets = 1 << 606 ((config4 & MIPS_CONF4_FTLBSETS) >> 607 MIPS_CONF4_FTLBSETS_SHIFT); 608 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 609 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 610 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 611 mips_has_ftlb_configured = 1; 612 break; 613 } 614 } 615 616 c->kscratch_mask = (config4 >> 16) & 0xff; 617 618 return config4 & MIPS_CONF_M; 619 } 620 621 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 622 { 623 unsigned int config5; 624 625 config5 = read_c0_config5(); 626 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 627 write_c0_config5(config5); 628 629 if (config5 & MIPS_CONF5_EVA) 630 c->options |= MIPS_CPU_EVA; 631 if (config5 & MIPS_CONF5_MRP) 632 c->options |= MIPS_CPU_MAAR; 633 if (config5 & MIPS_CONF5_LLB) 634 c->options |= MIPS_CPU_RW_LLB; 635 #ifdef CONFIG_XPA 636 if (config5 & MIPS_CONF5_MVH) 637 c->options |= MIPS_CPU_XPA; 638 #endif 639 640 return config5 & MIPS_CONF_M; 641 } 642 643 static void decode_configs(struct cpuinfo_mips *c) 644 { 645 int ok; 646 647 /* MIPS32 or MIPS64 compliant CPU. */ 648 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 649 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 650 651 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 652 653 /* Enable FTLB if present and not disabled */ 654 set_ftlb_enable(c, !mips_ftlb_disabled); 655 656 ok = decode_config0(c); /* Read Config registers. */ 657 BUG_ON(!ok); /* Arch spec violation! */ 658 if (ok) 659 ok = decode_config1(c); 660 if (ok) 661 ok = decode_config2(c); 662 if (ok) 663 ok = decode_config3(c); 664 if (ok) 665 ok = decode_config4(c); 666 if (ok) 667 ok = decode_config5(c); 668 669 mips_probe_watch_registers(c); 670 671 if (cpu_has_rixi) { 672 /* Enable the RIXI exceptions */ 673 set_c0_pagegrain(PG_IEC); 674 back_to_back_c0_hazard(); 675 /* Verify the IEC bit is set */ 676 if (read_c0_pagegrain() & PG_IEC) 677 c->options |= MIPS_CPU_RIXIEX; 678 } 679 680 #ifndef CONFIG_MIPS_CPS 681 if (cpu_has_mips_r2_r6) { 682 c->core = get_ebase_cpunum(); 683 if (cpu_has_mipsmt) 684 c->core >>= fls(core_nvpes()) - 1; 685 } 686 #endif 687 } 688 689 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 690 | MIPS_CPU_COUNTER) 691 692 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 693 { 694 switch (c->processor_id & PRID_IMP_MASK) { 695 case PRID_IMP_R2000: 696 c->cputype = CPU_R2000; 697 __cpu_name[cpu] = "R2000"; 698 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 699 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 700 MIPS_CPU_NOFPUEX; 701 if (__cpu_has_fpu()) 702 c->options |= MIPS_CPU_FPU; 703 c->tlbsize = 64; 704 break; 705 case PRID_IMP_R3000: 706 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 707 if (cpu_has_confreg()) { 708 c->cputype = CPU_R3081E; 709 __cpu_name[cpu] = "R3081"; 710 } else { 711 c->cputype = CPU_R3000A; 712 __cpu_name[cpu] = "R3000A"; 713 } 714 } else { 715 c->cputype = CPU_R3000; 716 __cpu_name[cpu] = "R3000"; 717 } 718 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 719 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 720 MIPS_CPU_NOFPUEX; 721 if (__cpu_has_fpu()) 722 c->options |= MIPS_CPU_FPU; 723 c->tlbsize = 64; 724 break; 725 case PRID_IMP_R4000: 726 if (read_c0_config() & CONF_SC) { 727 if ((c->processor_id & PRID_REV_MASK) >= 728 PRID_REV_R4400) { 729 c->cputype = CPU_R4400PC; 730 __cpu_name[cpu] = "R4400PC"; 731 } else { 732 c->cputype = CPU_R4000PC; 733 __cpu_name[cpu] = "R4000PC"; 734 } 735 } else { 736 int cca = read_c0_config() & CONF_CM_CMASK; 737 int mc; 738 739 /* 740 * SC and MC versions can't be reliably told apart, 741 * but only the latter support coherent caching 742 * modes so assume the firmware has set the KSEG0 743 * coherency attribute reasonably (if uncached, we 744 * assume SC). 745 */ 746 switch (cca) { 747 case CONF_CM_CACHABLE_CE: 748 case CONF_CM_CACHABLE_COW: 749 case CONF_CM_CACHABLE_CUW: 750 mc = 1; 751 break; 752 default: 753 mc = 0; 754 break; 755 } 756 if ((c->processor_id & PRID_REV_MASK) >= 757 PRID_REV_R4400) { 758 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 759 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 760 } else { 761 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 762 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 763 } 764 } 765 766 set_isa(c, MIPS_CPU_ISA_III); 767 c->fpu_msk31 |= FPU_CSR_CONDX; 768 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 769 MIPS_CPU_WATCH | MIPS_CPU_VCE | 770 MIPS_CPU_LLSC; 771 c->tlbsize = 48; 772 break; 773 case PRID_IMP_VR41XX: 774 set_isa(c, MIPS_CPU_ISA_III); 775 c->fpu_msk31 |= FPU_CSR_CONDX; 776 c->options = R4K_OPTS; 777 c->tlbsize = 32; 778 switch (c->processor_id & 0xf0) { 779 case PRID_REV_VR4111: 780 c->cputype = CPU_VR4111; 781 __cpu_name[cpu] = "NEC VR4111"; 782 break; 783 case PRID_REV_VR4121: 784 c->cputype = CPU_VR4121; 785 __cpu_name[cpu] = "NEC VR4121"; 786 break; 787 case PRID_REV_VR4122: 788 if ((c->processor_id & 0xf) < 0x3) { 789 c->cputype = CPU_VR4122; 790 __cpu_name[cpu] = "NEC VR4122"; 791 } else { 792 c->cputype = CPU_VR4181A; 793 __cpu_name[cpu] = "NEC VR4181A"; 794 } 795 break; 796 case PRID_REV_VR4130: 797 if ((c->processor_id & 0xf) < 0x4) { 798 c->cputype = CPU_VR4131; 799 __cpu_name[cpu] = "NEC VR4131"; 800 } else { 801 c->cputype = CPU_VR4133; 802 c->options |= MIPS_CPU_LLSC; 803 __cpu_name[cpu] = "NEC VR4133"; 804 } 805 break; 806 default: 807 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 808 c->cputype = CPU_VR41XX; 809 __cpu_name[cpu] = "NEC Vr41xx"; 810 break; 811 } 812 break; 813 case PRID_IMP_R4300: 814 c->cputype = CPU_R4300; 815 __cpu_name[cpu] = "R4300"; 816 set_isa(c, MIPS_CPU_ISA_III); 817 c->fpu_msk31 |= FPU_CSR_CONDX; 818 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 819 MIPS_CPU_LLSC; 820 c->tlbsize = 32; 821 break; 822 case PRID_IMP_R4600: 823 c->cputype = CPU_R4600; 824 __cpu_name[cpu] = "R4600"; 825 set_isa(c, MIPS_CPU_ISA_III); 826 c->fpu_msk31 |= FPU_CSR_CONDX; 827 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 828 MIPS_CPU_LLSC; 829 c->tlbsize = 48; 830 break; 831 #if 0 832 case PRID_IMP_R4650: 833 /* 834 * This processor doesn't have an MMU, so it's not 835 * "real easy" to run Linux on it. It is left purely 836 * for documentation. Commented out because it shares 837 * it's c0_prid id number with the TX3900. 838 */ 839 c->cputype = CPU_R4650; 840 __cpu_name[cpu] = "R4650"; 841 set_isa(c, MIPS_CPU_ISA_III); 842 c->fpu_msk31 |= FPU_CSR_CONDX; 843 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 844 c->tlbsize = 48; 845 break; 846 #endif 847 case PRID_IMP_TX39: 848 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 849 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 850 851 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 852 c->cputype = CPU_TX3927; 853 __cpu_name[cpu] = "TX3927"; 854 c->tlbsize = 64; 855 } else { 856 switch (c->processor_id & PRID_REV_MASK) { 857 case PRID_REV_TX3912: 858 c->cputype = CPU_TX3912; 859 __cpu_name[cpu] = "TX3912"; 860 c->tlbsize = 32; 861 break; 862 case PRID_REV_TX3922: 863 c->cputype = CPU_TX3922; 864 __cpu_name[cpu] = "TX3922"; 865 c->tlbsize = 64; 866 break; 867 } 868 } 869 break; 870 case PRID_IMP_R4700: 871 c->cputype = CPU_R4700; 872 __cpu_name[cpu] = "R4700"; 873 set_isa(c, MIPS_CPU_ISA_III); 874 c->fpu_msk31 |= FPU_CSR_CONDX; 875 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 876 MIPS_CPU_LLSC; 877 c->tlbsize = 48; 878 break; 879 case PRID_IMP_TX49: 880 c->cputype = CPU_TX49XX; 881 __cpu_name[cpu] = "R49XX"; 882 set_isa(c, MIPS_CPU_ISA_III); 883 c->fpu_msk31 |= FPU_CSR_CONDX; 884 c->options = R4K_OPTS | MIPS_CPU_LLSC; 885 if (!(c->processor_id & 0x08)) 886 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 887 c->tlbsize = 48; 888 break; 889 case PRID_IMP_R5000: 890 c->cputype = CPU_R5000; 891 __cpu_name[cpu] = "R5000"; 892 set_isa(c, MIPS_CPU_ISA_IV); 893 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 894 MIPS_CPU_LLSC; 895 c->tlbsize = 48; 896 break; 897 case PRID_IMP_R5432: 898 c->cputype = CPU_R5432; 899 __cpu_name[cpu] = "R5432"; 900 set_isa(c, MIPS_CPU_ISA_IV); 901 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 902 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 903 c->tlbsize = 48; 904 break; 905 case PRID_IMP_R5500: 906 c->cputype = CPU_R5500; 907 __cpu_name[cpu] = "R5500"; 908 set_isa(c, MIPS_CPU_ISA_IV); 909 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 910 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 911 c->tlbsize = 48; 912 break; 913 case PRID_IMP_NEVADA: 914 c->cputype = CPU_NEVADA; 915 __cpu_name[cpu] = "Nevada"; 916 set_isa(c, MIPS_CPU_ISA_IV); 917 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 918 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 919 c->tlbsize = 48; 920 break; 921 case PRID_IMP_R6000: 922 c->cputype = CPU_R6000; 923 __cpu_name[cpu] = "R6000"; 924 set_isa(c, MIPS_CPU_ISA_II); 925 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 926 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 927 MIPS_CPU_LLSC; 928 c->tlbsize = 32; 929 break; 930 case PRID_IMP_R6000A: 931 c->cputype = CPU_R6000A; 932 __cpu_name[cpu] = "R6000A"; 933 set_isa(c, MIPS_CPU_ISA_II); 934 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 935 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 936 MIPS_CPU_LLSC; 937 c->tlbsize = 32; 938 break; 939 case PRID_IMP_RM7000: 940 c->cputype = CPU_RM7000; 941 __cpu_name[cpu] = "RM7000"; 942 set_isa(c, MIPS_CPU_ISA_IV); 943 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 944 MIPS_CPU_LLSC; 945 /* 946 * Undocumented RM7000: Bit 29 in the info register of 947 * the RM7000 v2.0 indicates if the TLB has 48 or 64 948 * entries. 949 * 950 * 29 1 => 64 entry JTLB 951 * 0 => 48 entry JTLB 952 */ 953 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 954 break; 955 case PRID_IMP_R8000: 956 c->cputype = CPU_R8000; 957 __cpu_name[cpu] = "RM8000"; 958 set_isa(c, MIPS_CPU_ISA_IV); 959 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 960 MIPS_CPU_FPU | MIPS_CPU_32FPR | 961 MIPS_CPU_LLSC; 962 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 963 break; 964 case PRID_IMP_R10000: 965 c->cputype = CPU_R10000; 966 __cpu_name[cpu] = "R10000"; 967 set_isa(c, MIPS_CPU_ISA_IV); 968 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 969 MIPS_CPU_FPU | MIPS_CPU_32FPR | 970 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 971 MIPS_CPU_LLSC; 972 c->tlbsize = 64; 973 break; 974 case PRID_IMP_R12000: 975 c->cputype = CPU_R12000; 976 __cpu_name[cpu] = "R12000"; 977 set_isa(c, MIPS_CPU_ISA_IV); 978 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 979 MIPS_CPU_FPU | MIPS_CPU_32FPR | 980 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 981 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 982 c->tlbsize = 64; 983 break; 984 case PRID_IMP_R14000: 985 if (((c->processor_id >> 4) & 0x0f) > 2) { 986 c->cputype = CPU_R16000; 987 __cpu_name[cpu] = "R16000"; 988 } else { 989 c->cputype = CPU_R14000; 990 __cpu_name[cpu] = "R14000"; 991 } 992 set_isa(c, MIPS_CPU_ISA_IV); 993 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 994 MIPS_CPU_FPU | MIPS_CPU_32FPR | 995 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 996 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 997 c->tlbsize = 64; 998 break; 999 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1000 switch (c->processor_id & PRID_REV_MASK) { 1001 case PRID_REV_LOONGSON2E: 1002 c->cputype = CPU_LOONGSON2; 1003 __cpu_name[cpu] = "ICT Loongson-2"; 1004 set_elf_platform(cpu, "loongson2e"); 1005 set_isa(c, MIPS_CPU_ISA_III); 1006 c->fpu_msk31 |= FPU_CSR_CONDX; 1007 break; 1008 case PRID_REV_LOONGSON2F: 1009 c->cputype = CPU_LOONGSON2; 1010 __cpu_name[cpu] = "ICT Loongson-2"; 1011 set_elf_platform(cpu, "loongson2f"); 1012 set_isa(c, MIPS_CPU_ISA_III); 1013 c->fpu_msk31 |= FPU_CSR_CONDX; 1014 break; 1015 case PRID_REV_LOONGSON3A: 1016 c->cputype = CPU_LOONGSON3; 1017 __cpu_name[cpu] = "ICT Loongson-3"; 1018 set_elf_platform(cpu, "loongson3a"); 1019 set_isa(c, MIPS_CPU_ISA_M64R1); 1020 break; 1021 case PRID_REV_LOONGSON3B_R1: 1022 case PRID_REV_LOONGSON3B_R2: 1023 c->cputype = CPU_LOONGSON3; 1024 __cpu_name[cpu] = "ICT Loongson-3"; 1025 set_elf_platform(cpu, "loongson3b"); 1026 set_isa(c, MIPS_CPU_ISA_M64R1); 1027 break; 1028 } 1029 1030 c->options = R4K_OPTS | 1031 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1032 MIPS_CPU_32FPR; 1033 c->tlbsize = 64; 1034 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1035 break; 1036 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1037 decode_configs(c); 1038 1039 c->cputype = CPU_LOONGSON1; 1040 1041 switch (c->processor_id & PRID_REV_MASK) { 1042 case PRID_REV_LOONGSON1B: 1043 __cpu_name[cpu] = "Loongson 1B"; 1044 break; 1045 } 1046 1047 break; 1048 } 1049 } 1050 1051 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1052 { 1053 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1054 switch (c->processor_id & PRID_IMP_MASK) { 1055 case PRID_IMP_QEMU_GENERIC: 1056 c->writecombine = _CACHE_UNCACHED; 1057 c->cputype = CPU_QEMU_GENERIC; 1058 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1059 break; 1060 case PRID_IMP_4KC: 1061 c->cputype = CPU_4KC; 1062 c->writecombine = _CACHE_UNCACHED; 1063 __cpu_name[cpu] = "MIPS 4Kc"; 1064 break; 1065 case PRID_IMP_4KEC: 1066 case PRID_IMP_4KECR2: 1067 c->cputype = CPU_4KEC; 1068 c->writecombine = _CACHE_UNCACHED; 1069 __cpu_name[cpu] = "MIPS 4KEc"; 1070 break; 1071 case PRID_IMP_4KSC: 1072 case PRID_IMP_4KSD: 1073 c->cputype = CPU_4KSC; 1074 c->writecombine = _CACHE_UNCACHED; 1075 __cpu_name[cpu] = "MIPS 4KSc"; 1076 break; 1077 case PRID_IMP_5KC: 1078 c->cputype = CPU_5KC; 1079 c->writecombine = _CACHE_UNCACHED; 1080 __cpu_name[cpu] = "MIPS 5Kc"; 1081 break; 1082 case PRID_IMP_5KE: 1083 c->cputype = CPU_5KE; 1084 c->writecombine = _CACHE_UNCACHED; 1085 __cpu_name[cpu] = "MIPS 5KE"; 1086 break; 1087 case PRID_IMP_20KC: 1088 c->cputype = CPU_20KC; 1089 c->writecombine = _CACHE_UNCACHED; 1090 __cpu_name[cpu] = "MIPS 20Kc"; 1091 break; 1092 case PRID_IMP_24K: 1093 c->cputype = CPU_24K; 1094 c->writecombine = _CACHE_UNCACHED; 1095 __cpu_name[cpu] = "MIPS 24Kc"; 1096 break; 1097 case PRID_IMP_24KE: 1098 c->cputype = CPU_24K; 1099 c->writecombine = _CACHE_UNCACHED; 1100 __cpu_name[cpu] = "MIPS 24KEc"; 1101 break; 1102 case PRID_IMP_25KF: 1103 c->cputype = CPU_25KF; 1104 c->writecombine = _CACHE_UNCACHED; 1105 __cpu_name[cpu] = "MIPS 25Kc"; 1106 break; 1107 case PRID_IMP_34K: 1108 c->cputype = CPU_34K; 1109 c->writecombine = _CACHE_UNCACHED; 1110 __cpu_name[cpu] = "MIPS 34Kc"; 1111 break; 1112 case PRID_IMP_74K: 1113 c->cputype = CPU_74K; 1114 c->writecombine = _CACHE_UNCACHED; 1115 __cpu_name[cpu] = "MIPS 74Kc"; 1116 break; 1117 case PRID_IMP_M14KC: 1118 c->cputype = CPU_M14KC; 1119 c->writecombine = _CACHE_UNCACHED; 1120 __cpu_name[cpu] = "MIPS M14Kc"; 1121 break; 1122 case PRID_IMP_M14KEC: 1123 c->cputype = CPU_M14KEC; 1124 c->writecombine = _CACHE_UNCACHED; 1125 __cpu_name[cpu] = "MIPS M14KEc"; 1126 break; 1127 case PRID_IMP_1004K: 1128 c->cputype = CPU_1004K; 1129 c->writecombine = _CACHE_UNCACHED; 1130 __cpu_name[cpu] = "MIPS 1004Kc"; 1131 break; 1132 case PRID_IMP_1074K: 1133 c->cputype = CPU_1074K; 1134 c->writecombine = _CACHE_UNCACHED; 1135 __cpu_name[cpu] = "MIPS 1074Kc"; 1136 break; 1137 case PRID_IMP_INTERAPTIV_UP: 1138 c->cputype = CPU_INTERAPTIV; 1139 __cpu_name[cpu] = "MIPS interAptiv"; 1140 break; 1141 case PRID_IMP_INTERAPTIV_MP: 1142 c->cputype = CPU_INTERAPTIV; 1143 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1144 break; 1145 case PRID_IMP_PROAPTIV_UP: 1146 c->cputype = CPU_PROAPTIV; 1147 __cpu_name[cpu] = "MIPS proAptiv"; 1148 break; 1149 case PRID_IMP_PROAPTIV_MP: 1150 c->cputype = CPU_PROAPTIV; 1151 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1152 break; 1153 case PRID_IMP_P5600: 1154 c->cputype = CPU_P5600; 1155 __cpu_name[cpu] = "MIPS P5600"; 1156 break; 1157 case PRID_IMP_I6400: 1158 c->cputype = CPU_I6400; 1159 __cpu_name[cpu] = "MIPS I6400"; 1160 break; 1161 case PRID_IMP_M5150: 1162 c->cputype = CPU_M5150; 1163 __cpu_name[cpu] = "MIPS M5150"; 1164 break; 1165 } 1166 1167 decode_configs(c); 1168 1169 spram_config(); 1170 } 1171 1172 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1173 { 1174 decode_configs(c); 1175 switch (c->processor_id & PRID_IMP_MASK) { 1176 case PRID_IMP_AU1_REV1: 1177 case PRID_IMP_AU1_REV2: 1178 c->cputype = CPU_ALCHEMY; 1179 switch ((c->processor_id >> 24) & 0xff) { 1180 case 0: 1181 __cpu_name[cpu] = "Au1000"; 1182 break; 1183 case 1: 1184 __cpu_name[cpu] = "Au1500"; 1185 break; 1186 case 2: 1187 __cpu_name[cpu] = "Au1100"; 1188 break; 1189 case 3: 1190 __cpu_name[cpu] = "Au1550"; 1191 break; 1192 case 4: 1193 __cpu_name[cpu] = "Au1200"; 1194 if ((c->processor_id & PRID_REV_MASK) == 2) 1195 __cpu_name[cpu] = "Au1250"; 1196 break; 1197 case 5: 1198 __cpu_name[cpu] = "Au1210"; 1199 break; 1200 default: 1201 __cpu_name[cpu] = "Au1xxx"; 1202 break; 1203 } 1204 break; 1205 } 1206 } 1207 1208 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1209 { 1210 decode_configs(c); 1211 1212 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1213 switch (c->processor_id & PRID_IMP_MASK) { 1214 case PRID_IMP_SB1: 1215 c->cputype = CPU_SB1; 1216 __cpu_name[cpu] = "SiByte SB1"; 1217 /* FPU in pass1 is known to have issues. */ 1218 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1219 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1220 break; 1221 case PRID_IMP_SB1A: 1222 c->cputype = CPU_SB1A; 1223 __cpu_name[cpu] = "SiByte SB1A"; 1224 break; 1225 } 1226 } 1227 1228 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1229 { 1230 decode_configs(c); 1231 switch (c->processor_id & PRID_IMP_MASK) { 1232 case PRID_IMP_SR71000: 1233 c->cputype = CPU_SR71000; 1234 __cpu_name[cpu] = "Sandcraft SR71000"; 1235 c->scache.ways = 8; 1236 c->tlbsize = 64; 1237 break; 1238 } 1239 } 1240 1241 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1242 { 1243 decode_configs(c); 1244 switch (c->processor_id & PRID_IMP_MASK) { 1245 case PRID_IMP_PR4450: 1246 c->cputype = CPU_PR4450; 1247 __cpu_name[cpu] = "Philips PR4450"; 1248 set_isa(c, MIPS_CPU_ISA_M32R1); 1249 break; 1250 } 1251 } 1252 1253 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1254 { 1255 decode_configs(c); 1256 switch (c->processor_id & PRID_IMP_MASK) { 1257 case PRID_IMP_BMIPS32_REV4: 1258 case PRID_IMP_BMIPS32_REV8: 1259 c->cputype = CPU_BMIPS32; 1260 __cpu_name[cpu] = "Broadcom BMIPS32"; 1261 set_elf_platform(cpu, "bmips32"); 1262 break; 1263 case PRID_IMP_BMIPS3300: 1264 case PRID_IMP_BMIPS3300_ALT: 1265 case PRID_IMP_BMIPS3300_BUG: 1266 c->cputype = CPU_BMIPS3300; 1267 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1268 set_elf_platform(cpu, "bmips3300"); 1269 break; 1270 case PRID_IMP_BMIPS43XX: { 1271 int rev = c->processor_id & PRID_REV_MASK; 1272 1273 if (rev >= PRID_REV_BMIPS4380_LO && 1274 rev <= PRID_REV_BMIPS4380_HI) { 1275 c->cputype = CPU_BMIPS4380; 1276 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1277 set_elf_platform(cpu, "bmips4380"); 1278 } else { 1279 c->cputype = CPU_BMIPS4350; 1280 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1281 set_elf_platform(cpu, "bmips4350"); 1282 } 1283 break; 1284 } 1285 case PRID_IMP_BMIPS5000: 1286 case PRID_IMP_BMIPS5200: 1287 c->cputype = CPU_BMIPS5000; 1288 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1289 set_elf_platform(cpu, "bmips5000"); 1290 c->options |= MIPS_CPU_ULRI; 1291 break; 1292 } 1293 } 1294 1295 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1296 { 1297 decode_configs(c); 1298 switch (c->processor_id & PRID_IMP_MASK) { 1299 case PRID_IMP_CAVIUM_CN38XX: 1300 case PRID_IMP_CAVIUM_CN31XX: 1301 case PRID_IMP_CAVIUM_CN30XX: 1302 c->cputype = CPU_CAVIUM_OCTEON; 1303 __cpu_name[cpu] = "Cavium Octeon"; 1304 goto platform; 1305 case PRID_IMP_CAVIUM_CN58XX: 1306 case PRID_IMP_CAVIUM_CN56XX: 1307 case PRID_IMP_CAVIUM_CN50XX: 1308 case PRID_IMP_CAVIUM_CN52XX: 1309 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1310 __cpu_name[cpu] = "Cavium Octeon+"; 1311 platform: 1312 set_elf_platform(cpu, "octeon"); 1313 break; 1314 case PRID_IMP_CAVIUM_CN61XX: 1315 case PRID_IMP_CAVIUM_CN63XX: 1316 case PRID_IMP_CAVIUM_CN66XX: 1317 case PRID_IMP_CAVIUM_CN68XX: 1318 case PRID_IMP_CAVIUM_CNF71XX: 1319 c->cputype = CPU_CAVIUM_OCTEON2; 1320 __cpu_name[cpu] = "Cavium Octeon II"; 1321 set_elf_platform(cpu, "octeon2"); 1322 break; 1323 case PRID_IMP_CAVIUM_CN70XX: 1324 case PRID_IMP_CAVIUM_CN78XX: 1325 c->cputype = CPU_CAVIUM_OCTEON3; 1326 __cpu_name[cpu] = "Cavium Octeon III"; 1327 set_elf_platform(cpu, "octeon3"); 1328 break; 1329 default: 1330 printk(KERN_INFO "Unknown Octeon chip!\n"); 1331 c->cputype = CPU_UNKNOWN; 1332 break; 1333 } 1334 } 1335 1336 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1337 { 1338 decode_configs(c); 1339 /* JZRISC does not implement the CP0 counter. */ 1340 c->options &= ~MIPS_CPU_COUNTER; 1341 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1342 switch (c->processor_id & PRID_IMP_MASK) { 1343 case PRID_IMP_JZRISC: 1344 c->cputype = CPU_JZRISC; 1345 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1346 __cpu_name[cpu] = "Ingenic JZRISC"; 1347 break; 1348 default: 1349 panic("Unknown Ingenic Processor ID!"); 1350 break; 1351 } 1352 } 1353 1354 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1355 { 1356 decode_configs(c); 1357 1358 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1359 c->cputype = CPU_ALCHEMY; 1360 __cpu_name[cpu] = "Au1300"; 1361 /* following stuff is not for Alchemy */ 1362 return; 1363 } 1364 1365 c->options = (MIPS_CPU_TLB | 1366 MIPS_CPU_4KEX | 1367 MIPS_CPU_COUNTER | 1368 MIPS_CPU_DIVEC | 1369 MIPS_CPU_WATCH | 1370 MIPS_CPU_EJTAG | 1371 MIPS_CPU_LLSC); 1372 1373 switch (c->processor_id & PRID_IMP_MASK) { 1374 case PRID_IMP_NETLOGIC_XLP2XX: 1375 case PRID_IMP_NETLOGIC_XLP9XX: 1376 case PRID_IMP_NETLOGIC_XLP5XX: 1377 c->cputype = CPU_XLP; 1378 __cpu_name[cpu] = "Broadcom XLPII"; 1379 break; 1380 1381 case PRID_IMP_NETLOGIC_XLP8XX: 1382 case PRID_IMP_NETLOGIC_XLP3XX: 1383 c->cputype = CPU_XLP; 1384 __cpu_name[cpu] = "Netlogic XLP"; 1385 break; 1386 1387 case PRID_IMP_NETLOGIC_XLR732: 1388 case PRID_IMP_NETLOGIC_XLR716: 1389 case PRID_IMP_NETLOGIC_XLR532: 1390 case PRID_IMP_NETLOGIC_XLR308: 1391 case PRID_IMP_NETLOGIC_XLR532C: 1392 case PRID_IMP_NETLOGIC_XLR516C: 1393 case PRID_IMP_NETLOGIC_XLR508C: 1394 case PRID_IMP_NETLOGIC_XLR308C: 1395 c->cputype = CPU_XLR; 1396 __cpu_name[cpu] = "Netlogic XLR"; 1397 break; 1398 1399 case PRID_IMP_NETLOGIC_XLS608: 1400 case PRID_IMP_NETLOGIC_XLS408: 1401 case PRID_IMP_NETLOGIC_XLS404: 1402 case PRID_IMP_NETLOGIC_XLS208: 1403 case PRID_IMP_NETLOGIC_XLS204: 1404 case PRID_IMP_NETLOGIC_XLS108: 1405 case PRID_IMP_NETLOGIC_XLS104: 1406 case PRID_IMP_NETLOGIC_XLS616B: 1407 case PRID_IMP_NETLOGIC_XLS608B: 1408 case PRID_IMP_NETLOGIC_XLS416B: 1409 case PRID_IMP_NETLOGIC_XLS412B: 1410 case PRID_IMP_NETLOGIC_XLS408B: 1411 case PRID_IMP_NETLOGIC_XLS404B: 1412 c->cputype = CPU_XLR; 1413 __cpu_name[cpu] = "Netlogic XLS"; 1414 break; 1415 1416 default: 1417 pr_info("Unknown Netlogic chip id [%02x]!\n", 1418 c->processor_id); 1419 c->cputype = CPU_XLR; 1420 break; 1421 } 1422 1423 if (c->cputype == CPU_XLP) { 1424 set_isa(c, MIPS_CPU_ISA_M64R2); 1425 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1426 /* This will be updated again after all threads are woken up */ 1427 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1428 } else { 1429 set_isa(c, MIPS_CPU_ISA_M64R1); 1430 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1431 } 1432 c->kscratch_mask = 0xf; 1433 } 1434 1435 #ifdef CONFIG_64BIT 1436 /* For use by uaccess.h */ 1437 u64 __ua_limit; 1438 EXPORT_SYMBOL(__ua_limit); 1439 #endif 1440 1441 const char *__cpu_name[NR_CPUS]; 1442 const char *__elf_platform; 1443 1444 void cpu_probe(void) 1445 { 1446 struct cpuinfo_mips *c = ¤t_cpu_data; 1447 unsigned int cpu = smp_processor_id(); 1448 1449 c->processor_id = PRID_IMP_UNKNOWN; 1450 c->fpu_id = FPIR_IMP_NONE; 1451 c->cputype = CPU_UNKNOWN; 1452 c->writecombine = _CACHE_UNCACHED; 1453 1454 c->fpu_csr31 = FPU_CSR_RN; 1455 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1456 1457 c->processor_id = read_c0_prid(); 1458 switch (c->processor_id & PRID_COMP_MASK) { 1459 case PRID_COMP_LEGACY: 1460 cpu_probe_legacy(c, cpu); 1461 break; 1462 case PRID_COMP_MIPS: 1463 cpu_probe_mips(c, cpu); 1464 break; 1465 case PRID_COMP_ALCHEMY: 1466 cpu_probe_alchemy(c, cpu); 1467 break; 1468 case PRID_COMP_SIBYTE: 1469 cpu_probe_sibyte(c, cpu); 1470 break; 1471 case PRID_COMP_BROADCOM: 1472 cpu_probe_broadcom(c, cpu); 1473 break; 1474 case PRID_COMP_SANDCRAFT: 1475 cpu_probe_sandcraft(c, cpu); 1476 break; 1477 case PRID_COMP_NXP: 1478 cpu_probe_nxp(c, cpu); 1479 break; 1480 case PRID_COMP_CAVIUM: 1481 cpu_probe_cavium(c, cpu); 1482 break; 1483 case PRID_COMP_INGENIC_D0: 1484 case PRID_COMP_INGENIC_D1: 1485 case PRID_COMP_INGENIC_E1: 1486 cpu_probe_ingenic(c, cpu); 1487 break; 1488 case PRID_COMP_NETLOGIC: 1489 cpu_probe_netlogic(c, cpu); 1490 break; 1491 } 1492 1493 BUG_ON(!__cpu_name[cpu]); 1494 BUG_ON(c->cputype == CPU_UNKNOWN); 1495 1496 /* 1497 * Platform code can force the cpu type to optimize code 1498 * generation. In that case be sure the cpu type is correctly 1499 * manually setup otherwise it could trigger some nasty bugs. 1500 */ 1501 BUG_ON(current_cpu_type() != c->cputype); 1502 1503 if (mips_fpu_disabled) 1504 c->options &= ~MIPS_CPU_FPU; 1505 1506 if (mips_dsp_disabled) 1507 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1508 1509 if (mips_htw_disabled) { 1510 c->options &= ~MIPS_CPU_HTW; 1511 write_c0_pwctl(read_c0_pwctl() & 1512 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1513 } 1514 1515 if (c->options & MIPS_CPU_FPU) 1516 cpu_set_fpu_opts(c); 1517 else 1518 cpu_set_nofpu_opts(c); 1519 1520 if (cpu_has_bp_ghist) 1521 write_c0_r10k_diag(read_c0_r10k_diag() | 1522 R10K_DIAG_E_GHIST); 1523 1524 if (cpu_has_mips_r2_r6) { 1525 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1526 /* R2 has Performance Counter Interrupt indicator */ 1527 c->options |= MIPS_CPU_PCI; 1528 } 1529 else 1530 c->srsets = 1; 1531 1532 if (cpu_has_mips_r6) 1533 elf_hwcap |= HWCAP_MIPS_R6; 1534 1535 if (cpu_has_msa) { 1536 c->msa_id = cpu_get_msa_id(); 1537 WARN(c->msa_id & MSA_IR_WRPF, 1538 "Vector register partitioning unimplemented!"); 1539 elf_hwcap |= HWCAP_MIPS_MSA; 1540 } 1541 1542 cpu_probe_vmbits(c); 1543 1544 #ifdef CONFIG_64BIT 1545 if (cpu == 0) 1546 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1547 #endif 1548 } 1549 1550 void cpu_report(void) 1551 { 1552 struct cpuinfo_mips *c = ¤t_cpu_data; 1553 1554 pr_info("CPU%d revision is: %08x (%s)\n", 1555 smp_processor_id(), c->processor_id, cpu_name_string()); 1556 if (c->options & MIPS_CPU_FPU) 1557 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1558 if (cpu_has_msa) 1559 pr_info("MSA revision is: %08x\n", c->msa_id); 1560 } 1561