1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <linux/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 /* 40 * Get the FPU Implementation/Revision. 41 */ 42 static inline unsigned long cpu_get_fpu_id(void) 43 { 44 unsigned long tmp, fpu_id; 45 46 tmp = read_c0_status(); 47 __enable_fpu(FPU_AS_IS); 48 fpu_id = read_32bit_cp1_register(CP1_REVISION); 49 write_c0_status(tmp); 50 return fpu_id; 51 } 52 53 /* 54 * Check if the CPU has an external FPU. 55 */ 56 static inline int __cpu_has_fpu(void) 57 { 58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 59 } 60 61 static inline unsigned long cpu_get_msa_id(void) 62 { 63 unsigned long status, msa_id; 64 65 status = read_c0_status(); 66 __enable_fpu(FPU_64BIT); 67 enable_msa(); 68 msa_id = read_msa_ir(); 69 disable_msa(); 70 write_c0_status(status); 71 return msa_id; 72 } 73 74 /* 75 * Determine the FCSR mask for FPU hardware. 76 */ 77 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 78 { 79 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 80 81 fcsr = c->fpu_csr31; 82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 83 84 sr = read_c0_status(); 85 __enable_fpu(FPU_AS_IS); 86 87 fcsr0 = fcsr & mask; 88 write_32bit_cp1_register(CP1_STATUS, fcsr0); 89 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 90 91 fcsr1 = fcsr | ~mask; 92 write_32bit_cp1_register(CP1_STATUS, fcsr1); 93 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 94 95 write_32bit_cp1_register(CP1_STATUS, fcsr); 96 97 write_c0_status(sr); 98 99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 100 } 101 102 /* 103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 104 * supported by FPU hardware. 105 */ 106 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 107 { 108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 111 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 112 113 sr = read_c0_status(); 114 __enable_fpu(FPU_AS_IS); 115 116 fir = read_32bit_cp1_register(CP1_REVISION); 117 if (fir & MIPS_FPIR_HAS2008) { 118 fcsr = read_32bit_cp1_register(CP1_STATUS); 119 120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 121 write_32bit_cp1_register(CP1_STATUS, fcsr0); 122 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 123 124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 125 write_32bit_cp1_register(CP1_STATUS, fcsr1); 126 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 127 128 write_32bit_cp1_register(CP1_STATUS, fcsr); 129 130 if (!(fcsr0 & FPU_CSR_NAN2008)) 131 c->options |= MIPS_CPU_NAN_LEGACY; 132 if (fcsr1 & FPU_CSR_NAN2008) 133 c->options |= MIPS_CPU_NAN_2008; 134 135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 136 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 137 else 138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 139 140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 141 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 142 else 143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 144 } else { 145 c->options |= MIPS_CPU_NAN_LEGACY; 146 } 147 148 write_c0_status(sr); 149 } else { 150 c->options |= MIPS_CPU_NAN_LEGACY; 151 } 152 } 153 154 /* 155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 156 * ABS.fmt/NEG.fmt execution mode. 157 */ 158 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 159 160 /* 161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 162 * to support by the FPU emulator according to the IEEE 754 conformance 163 * mode selected. Note that "relaxed" straps the emulator so that it 164 * allows 2008-NaN binaries even for legacy processors. 165 */ 166 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 167 { 168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 171 172 switch (ieee754) { 173 case STRICT: 174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 178 } else { 179 c->options |= MIPS_CPU_NAN_LEGACY; 180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 181 } 182 break; 183 case LEGACY: 184 c->options |= MIPS_CPU_NAN_LEGACY; 185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 186 break; 187 case STD2008: 188 c->options |= MIPS_CPU_NAN_2008; 189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 191 break; 192 case RELAXED: 193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 194 break; 195 } 196 } 197 198 /* 199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 200 * according to the "ieee754=" parameter. 201 */ 202 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 203 { 204 switch (ieee754) { 205 case STRICT: 206 mips_use_nan_legacy = !!cpu_has_nan_legacy; 207 mips_use_nan_2008 = !!cpu_has_nan_2008; 208 break; 209 case LEGACY: 210 mips_use_nan_legacy = !!cpu_has_nan_legacy; 211 mips_use_nan_2008 = !cpu_has_nan_legacy; 212 break; 213 case STD2008: 214 mips_use_nan_legacy = !cpu_has_nan_2008; 215 mips_use_nan_2008 = !!cpu_has_nan_2008; 216 break; 217 case RELAXED: 218 mips_use_nan_legacy = true; 219 mips_use_nan_2008 = true; 220 break; 221 } 222 } 223 224 /* 225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 226 * settings: 227 * 228 * strict: accept binaries that request a NaN encoding supported by the FPU 229 * legacy: only accept legacy-NaN binaries 230 * 2008: only accept 2008-NaN binaries 231 * relaxed: accept any binaries regardless of whether supported by the FPU 232 */ 233 static int __init ieee754_setup(char *s) 234 { 235 if (!s) 236 return -1; 237 else if (!strcmp(s, "strict")) 238 ieee754 = STRICT; 239 else if (!strcmp(s, "legacy")) 240 ieee754 = LEGACY; 241 else if (!strcmp(s, "2008")) 242 ieee754 = STD2008; 243 else if (!strcmp(s, "relaxed")) 244 ieee754 = RELAXED; 245 else 246 return -1; 247 248 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 249 cpu_set_nofpu_2008(&boot_cpu_data); 250 cpu_set_nan_2008(&boot_cpu_data); 251 252 return 0; 253 } 254 255 early_param("ieee754", ieee754_setup); 256 257 /* 258 * Set the FIR feature flags for the FPU emulator. 259 */ 260 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 261 { 262 u32 value; 263 264 value = 0; 265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 268 value |= MIPS_FPIR_D | MIPS_FPIR_S; 269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 272 if (c->options & MIPS_CPU_NAN_2008) 273 value |= MIPS_FPIR_HAS2008; 274 c->fpu_id = value; 275 } 276 277 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 278 static unsigned int mips_nofpu_msk31; 279 280 /* 281 * Set options for FPU hardware. 282 */ 283 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 284 { 285 c->fpu_id = cpu_get_fpu_id(); 286 mips_nofpu_msk31 = c->fpu_msk31; 287 288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 291 if (c->fpu_id & MIPS_FPIR_3D) 292 c->ases |= MIPS_ASE_MIPS3D; 293 if (c->fpu_id & MIPS_FPIR_UFRP) 294 c->options |= MIPS_CPU_UFR; 295 if (c->fpu_id & MIPS_FPIR_FREP) 296 c->options |= MIPS_CPU_FRE; 297 } 298 299 cpu_set_fpu_fcsr_mask(c); 300 cpu_set_fpu_2008(c); 301 cpu_set_nan_2008(c); 302 } 303 304 /* 305 * Set options for the FPU emulator. 306 */ 307 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 308 { 309 c->options &= ~MIPS_CPU_FPU; 310 c->fpu_msk31 = mips_nofpu_msk31; 311 312 cpu_set_nofpu_2008(c); 313 cpu_set_nan_2008(c); 314 cpu_set_nofpu_id(c); 315 } 316 317 static int mips_fpu_disabled; 318 319 static int __init fpu_disable(char *s) 320 { 321 cpu_set_nofpu_opts(&boot_cpu_data); 322 mips_fpu_disabled = 1; 323 324 return 1; 325 } 326 327 __setup("nofpu", fpu_disable); 328 329 int mips_dsp_disabled; 330 331 static int __init dsp_disable(char *s) 332 { 333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 334 mips_dsp_disabled = 1; 335 336 return 1; 337 } 338 339 __setup("nodsp", dsp_disable); 340 341 static int mips_htw_disabled; 342 343 static int __init htw_disable(char *s) 344 { 345 mips_htw_disabled = 1; 346 cpu_data[0].options &= ~MIPS_CPU_HTW; 347 write_c0_pwctl(read_c0_pwctl() & 348 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 349 350 return 1; 351 } 352 353 __setup("nohtw", htw_disable); 354 355 static int mips_ftlb_disabled; 356 static int mips_has_ftlb_configured; 357 358 enum ftlb_flags { 359 FTLB_EN = 1 << 0, 360 FTLB_SET_PROB = 1 << 1, 361 }; 362 363 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 364 365 static int __init ftlb_disable(char *s) 366 { 367 unsigned int config4, mmuextdef; 368 369 /* 370 * If the core hasn't done any FTLB configuration, there is nothing 371 * for us to do here. 372 */ 373 if (!mips_has_ftlb_configured) 374 return 1; 375 376 /* Disable it in the boot cpu */ 377 if (set_ftlb_enable(&cpu_data[0], 0)) { 378 pr_warn("Can't turn FTLB off\n"); 379 return 1; 380 } 381 382 config4 = read_c0_config4(); 383 384 /* Check that FTLB has been disabled */ 385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 388 /* This should never happen */ 389 pr_warn("FTLB could not be disabled!\n"); 390 return 1; 391 } 392 393 mips_ftlb_disabled = 1; 394 mips_has_ftlb_configured = 0; 395 396 /* 397 * noftlb is mainly used for debug purposes so print 398 * an informative message instead of using pr_debug() 399 */ 400 pr_info("FTLB has been disabled\n"); 401 402 /* 403 * Some of these bits are duplicated in the decode_config4. 404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 405 * once FTLB has been disabled so undo what decode_config4 did. 406 */ 407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 408 cpu_data[0].tlbsizeftlbsets; 409 cpu_data[0].tlbsizeftlbsets = 0; 410 cpu_data[0].tlbsizeftlbways = 0; 411 412 return 1; 413 } 414 415 __setup("noftlb", ftlb_disable); 416 417 418 static inline void check_errata(void) 419 { 420 struct cpuinfo_mips *c = ¤t_cpu_data; 421 422 switch (current_cpu_type()) { 423 case CPU_34K: 424 /* 425 * Erratum "RPS May Cause Incorrect Instruction Execution" 426 * This code only handles VPE0, any SMP/RTOS code 427 * making use of VPE1 will be responsable for that VPE. 428 */ 429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 431 break; 432 default: 433 break; 434 } 435 } 436 437 void __init check_bugs32(void) 438 { 439 check_errata(); 440 } 441 442 /* 443 * Probe whether cpu has config register by trying to play with 444 * alternate cache bit and see whether it matters. 445 * It's used by cpu_probe to distinguish between R3000A and R3081. 446 */ 447 static inline int cpu_has_confreg(void) 448 { 449 #ifdef CONFIG_CPU_R3000 450 extern unsigned long r3k_cache_size(unsigned long); 451 unsigned long size1, size2; 452 unsigned long cfg = read_c0_conf(); 453 454 size1 = r3k_cache_size(ST0_ISC); 455 write_c0_conf(cfg ^ R30XX_CONF_AC); 456 size2 = r3k_cache_size(ST0_ISC); 457 write_c0_conf(cfg); 458 return size1 != size2; 459 #else 460 return 0; 461 #endif 462 } 463 464 static inline void set_elf_platform(int cpu, const char *plat) 465 { 466 if (cpu == 0) 467 __elf_platform = plat; 468 } 469 470 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 471 { 472 #ifdef __NEED_VMBITS_PROBE 473 write_c0_entryhi(0x3fffffffffffe000ULL); 474 back_to_back_c0_hazard(); 475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 476 #endif 477 } 478 479 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 480 { 481 switch (isa) { 482 case MIPS_CPU_ISA_M64R2: 483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 484 case MIPS_CPU_ISA_M64R1: 485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 486 case MIPS_CPU_ISA_V: 487 c->isa_level |= MIPS_CPU_ISA_V; 488 case MIPS_CPU_ISA_IV: 489 c->isa_level |= MIPS_CPU_ISA_IV; 490 case MIPS_CPU_ISA_III: 491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 492 break; 493 494 /* R6 incompatible with everything else */ 495 case MIPS_CPU_ISA_M64R6: 496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 497 case MIPS_CPU_ISA_M32R6: 498 c->isa_level |= MIPS_CPU_ISA_M32R6; 499 /* Break here so we don't add incompatible ISAs */ 500 break; 501 case MIPS_CPU_ISA_M32R2: 502 c->isa_level |= MIPS_CPU_ISA_M32R2; 503 case MIPS_CPU_ISA_M32R1: 504 c->isa_level |= MIPS_CPU_ISA_M32R1; 505 case MIPS_CPU_ISA_II: 506 c->isa_level |= MIPS_CPU_ISA_II; 507 break; 508 } 509 } 510 511 static char unknown_isa[] = KERN_ERR \ 512 "Unsupported ISA type, c0.config0: %d."; 513 514 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 515 { 516 517 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 518 519 /* 520 * 0 = All TLBWR instructions go to FTLB 521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 522 * FTLB and 1 goes to the VTLB. 523 * 2 = 7:1: As above with 7:1 ratio. 524 * 3 = 3:1: As above with 3:1 ratio. 525 * 526 * Use the linear midpoint as the probability threshold. 527 */ 528 if (probability >= 12) 529 return 1; 530 else if (probability >= 6) 531 return 2; 532 else 533 /* 534 * So FTLB is less than 4 times bigger than VTLB. 535 * A 3:1 ratio can still be useful though. 536 */ 537 return 3; 538 } 539 540 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 541 { 542 unsigned int config; 543 544 /* It's implementation dependent how the FTLB can be enabled */ 545 switch (c->cputype) { 546 case CPU_PROAPTIV: 547 case CPU_P5600: 548 case CPU_P6600: 549 /* proAptiv & related cores use Config6 to enable the FTLB */ 550 config = read_c0_config6(); 551 552 if (flags & FTLB_EN) 553 config |= MIPS_CONF6_FTLBEN; 554 else 555 config &= ~MIPS_CONF6_FTLBEN; 556 557 if (flags & FTLB_SET_PROB) { 558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 559 config |= calculate_ftlb_probability(c) 560 << MIPS_CONF6_FTLBP_SHIFT; 561 } 562 563 write_c0_config6(config); 564 back_to_back_c0_hazard(); 565 break; 566 case CPU_I6400: 567 case CPU_I6500: 568 /* There's no way to disable the FTLB */ 569 if (!(flags & FTLB_EN)) 570 return 1; 571 return 0; 572 case CPU_LOONGSON3: 573 /* Flush ITLB, DTLB, VTLB and FTLB */ 574 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 575 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 576 /* Loongson-3 cores use Config6 to enable the FTLB */ 577 config = read_c0_config6(); 578 if (flags & FTLB_EN) 579 /* Enable FTLB */ 580 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); 581 else 582 /* Disable FTLB */ 583 write_c0_config6(config | MIPS_CONF6_FTLBDIS); 584 break; 585 default: 586 return 1; 587 } 588 589 return 0; 590 } 591 592 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 593 { 594 unsigned int config0; 595 int isa, mt; 596 597 config0 = read_c0_config(); 598 599 /* 600 * Look for Standard TLB or Dual VTLB and FTLB 601 */ 602 mt = config0 & MIPS_CONF_MT; 603 if (mt == MIPS_CONF_MT_TLB) 604 c->options |= MIPS_CPU_TLB; 605 else if (mt == MIPS_CONF_MT_FTLB) 606 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 607 608 isa = (config0 & MIPS_CONF_AT) >> 13; 609 switch (isa) { 610 case 0: 611 switch ((config0 & MIPS_CONF_AR) >> 10) { 612 case 0: 613 set_isa(c, MIPS_CPU_ISA_M32R1); 614 break; 615 case 1: 616 set_isa(c, MIPS_CPU_ISA_M32R2); 617 break; 618 case 2: 619 set_isa(c, MIPS_CPU_ISA_M32R6); 620 break; 621 default: 622 goto unknown; 623 } 624 break; 625 case 2: 626 switch ((config0 & MIPS_CONF_AR) >> 10) { 627 case 0: 628 set_isa(c, MIPS_CPU_ISA_M64R1); 629 break; 630 case 1: 631 set_isa(c, MIPS_CPU_ISA_M64R2); 632 break; 633 case 2: 634 set_isa(c, MIPS_CPU_ISA_M64R6); 635 break; 636 default: 637 goto unknown; 638 } 639 break; 640 default: 641 goto unknown; 642 } 643 644 return config0 & MIPS_CONF_M; 645 646 unknown: 647 panic(unknown_isa, config0); 648 } 649 650 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 651 { 652 unsigned int config1; 653 654 config1 = read_c0_config1(); 655 656 if (config1 & MIPS_CONF1_MD) 657 c->ases |= MIPS_ASE_MDMX; 658 if (config1 & MIPS_CONF1_PC) 659 c->options |= MIPS_CPU_PERF; 660 if (config1 & MIPS_CONF1_WR) 661 c->options |= MIPS_CPU_WATCH; 662 if (config1 & MIPS_CONF1_CA) 663 c->ases |= MIPS_ASE_MIPS16; 664 if (config1 & MIPS_CONF1_EP) 665 c->options |= MIPS_CPU_EJTAG; 666 if (config1 & MIPS_CONF1_FP) { 667 c->options |= MIPS_CPU_FPU; 668 c->options |= MIPS_CPU_32FPR; 669 } 670 if (cpu_has_tlb) { 671 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 672 c->tlbsizevtlb = c->tlbsize; 673 c->tlbsizeftlbsets = 0; 674 } 675 676 return config1 & MIPS_CONF_M; 677 } 678 679 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 680 { 681 unsigned int config2; 682 683 config2 = read_c0_config2(); 684 685 if (config2 & MIPS_CONF2_SL) 686 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 687 688 return config2 & MIPS_CONF_M; 689 } 690 691 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 692 { 693 unsigned int config3; 694 695 config3 = read_c0_config3(); 696 697 if (config3 & MIPS_CONF3_SM) { 698 c->ases |= MIPS_ASE_SMARTMIPS; 699 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 700 } 701 if (config3 & MIPS_CONF3_RXI) 702 c->options |= MIPS_CPU_RIXI; 703 if (config3 & MIPS_CONF3_CTXTC) 704 c->options |= MIPS_CPU_CTXTC; 705 if (config3 & MIPS_CONF3_DSP) 706 c->ases |= MIPS_ASE_DSP; 707 if (config3 & MIPS_CONF3_DSP2P) { 708 c->ases |= MIPS_ASE_DSP2P; 709 if (cpu_has_mips_r6) 710 c->ases |= MIPS_ASE_DSP3; 711 } 712 if (config3 & MIPS_CONF3_VINT) 713 c->options |= MIPS_CPU_VINT; 714 if (config3 & MIPS_CONF3_VEIC) 715 c->options |= MIPS_CPU_VEIC; 716 if (config3 & MIPS_CONF3_LPA) 717 c->options |= MIPS_CPU_LPA; 718 if (config3 & MIPS_CONF3_MT) 719 c->ases |= MIPS_ASE_MIPSMT; 720 if (config3 & MIPS_CONF3_ULRI) 721 c->options |= MIPS_CPU_ULRI; 722 if (config3 & MIPS_CONF3_ISA) 723 c->options |= MIPS_CPU_MICROMIPS; 724 if (config3 & MIPS_CONF3_VZ) 725 c->ases |= MIPS_ASE_VZ; 726 if (config3 & MIPS_CONF3_SC) 727 c->options |= MIPS_CPU_SEGMENTS; 728 if (config3 & MIPS_CONF3_BI) 729 c->options |= MIPS_CPU_BADINSTR; 730 if (config3 & MIPS_CONF3_BP) 731 c->options |= MIPS_CPU_BADINSTRP; 732 if (config3 & MIPS_CONF3_MSA) 733 c->ases |= MIPS_ASE_MSA; 734 if (config3 & MIPS_CONF3_PW) { 735 c->htw_seq = 0; 736 c->options |= MIPS_CPU_HTW; 737 } 738 if (config3 & MIPS_CONF3_CDMM) 739 c->options |= MIPS_CPU_CDMM; 740 if (config3 & MIPS_CONF3_SP) 741 c->options |= MIPS_CPU_SP; 742 743 return config3 & MIPS_CONF_M; 744 } 745 746 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 747 { 748 unsigned int config4; 749 unsigned int newcf4; 750 unsigned int mmuextdef; 751 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 752 unsigned long asid_mask; 753 754 config4 = read_c0_config4(); 755 756 if (cpu_has_tlb) { 757 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 758 c->options |= MIPS_CPU_TLBINV; 759 760 /* 761 * R6 has dropped the MMUExtDef field from config4. 762 * On R6 the fields always describe the FTLB, and only if it is 763 * present according to Config.MT. 764 */ 765 if (!cpu_has_mips_r6) 766 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 767 else if (cpu_has_ftlb) 768 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 769 else 770 mmuextdef = 0; 771 772 switch (mmuextdef) { 773 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 774 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 775 c->tlbsizevtlb = c->tlbsize; 776 break; 777 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 778 c->tlbsizevtlb += 779 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 780 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 781 c->tlbsize = c->tlbsizevtlb; 782 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 783 /* fall through */ 784 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 785 if (mips_ftlb_disabled) 786 break; 787 newcf4 = (config4 & ~ftlb_page) | 788 (page_size_ftlb(mmuextdef) << 789 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 790 write_c0_config4(newcf4); 791 back_to_back_c0_hazard(); 792 config4 = read_c0_config4(); 793 if (config4 != newcf4) { 794 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 795 PAGE_SIZE, config4); 796 /* Switch FTLB off */ 797 set_ftlb_enable(c, 0); 798 mips_ftlb_disabled = 1; 799 break; 800 } 801 c->tlbsizeftlbsets = 1 << 802 ((config4 & MIPS_CONF4_FTLBSETS) >> 803 MIPS_CONF4_FTLBSETS_SHIFT); 804 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 805 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 806 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 807 mips_has_ftlb_configured = 1; 808 break; 809 } 810 } 811 812 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 813 >> MIPS_CONF4_KSCREXIST_SHIFT; 814 815 asid_mask = MIPS_ENTRYHI_ASID; 816 if (config4 & MIPS_CONF4_AE) 817 asid_mask |= MIPS_ENTRYHI_ASIDX; 818 set_cpu_asid_mask(c, asid_mask); 819 820 /* 821 * Warn if the computed ASID mask doesn't match the mask the kernel 822 * is built for. This may indicate either a serious problem or an 823 * easy optimisation opportunity, but either way should be addressed. 824 */ 825 WARN_ON(asid_mask != cpu_asid_mask(c)); 826 827 return config4 & MIPS_CONF_M; 828 } 829 830 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 831 { 832 unsigned int config5; 833 834 config5 = read_c0_config5(); 835 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 836 write_c0_config5(config5); 837 838 if (config5 & MIPS_CONF5_EVA) 839 c->options |= MIPS_CPU_EVA; 840 if (config5 & MIPS_CONF5_MRP) 841 c->options |= MIPS_CPU_MAAR; 842 if (config5 & MIPS_CONF5_LLB) 843 c->options |= MIPS_CPU_RW_LLB; 844 if (config5 & MIPS_CONF5_MVH) 845 c->options |= MIPS_CPU_MVH; 846 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 847 c->options |= MIPS_CPU_VP; 848 if (config5 & MIPS_CONF5_CA2) 849 c->ases |= MIPS_ASE_MIPS16E2; 850 851 return config5 & MIPS_CONF_M; 852 } 853 854 static void decode_configs(struct cpuinfo_mips *c) 855 { 856 int ok; 857 858 /* MIPS32 or MIPS64 compliant CPU. */ 859 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 860 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 861 862 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 863 864 /* Enable FTLB if present and not disabled */ 865 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 866 867 ok = decode_config0(c); /* Read Config registers. */ 868 BUG_ON(!ok); /* Arch spec violation! */ 869 if (ok) 870 ok = decode_config1(c); 871 if (ok) 872 ok = decode_config2(c); 873 if (ok) 874 ok = decode_config3(c); 875 if (ok) 876 ok = decode_config4(c); 877 if (ok) 878 ok = decode_config5(c); 879 880 /* Probe the EBase.WG bit */ 881 if (cpu_has_mips_r2_r6) { 882 u64 ebase; 883 unsigned int status; 884 885 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 886 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 887 : (s32)read_c0_ebase(); 888 if (ebase & MIPS_EBASE_WG) { 889 /* WG bit already set, we can avoid the clumsy probe */ 890 c->options |= MIPS_CPU_EBASE_WG; 891 } else { 892 /* Its UNDEFINED to change EBase while BEV=0 */ 893 status = read_c0_status(); 894 write_c0_status(status | ST0_BEV); 895 irq_enable_hazard(); 896 /* 897 * On pre-r6 cores, this may well clobber the upper bits 898 * of EBase. This is hard to avoid without potentially 899 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 900 */ 901 if (cpu_has_mips64r6) 902 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 903 else 904 write_c0_ebase(ebase | MIPS_EBASE_WG); 905 back_to_back_c0_hazard(); 906 /* Restore BEV */ 907 write_c0_status(status); 908 if (read_c0_ebase() & MIPS_EBASE_WG) { 909 c->options |= MIPS_CPU_EBASE_WG; 910 write_c0_ebase(ebase); 911 } 912 } 913 } 914 915 /* configure the FTLB write probability */ 916 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 917 918 mips_probe_watch_registers(c); 919 920 #ifndef CONFIG_MIPS_CPS 921 if (cpu_has_mips_r2_r6) { 922 c->core = get_ebase_cpunum(); 923 if (cpu_has_mipsmt) 924 c->core >>= fls(core_nvpes()) - 1; 925 } 926 #endif 927 } 928 929 /* 930 * Probe for certain guest capabilities by writing config bits and reading back. 931 * Finally write back the original value. 932 */ 933 #define probe_gc0_config(name, maxconf, bits) \ 934 do { \ 935 unsigned int tmp; \ 936 tmp = read_gc0_##name(); \ 937 write_gc0_##name(tmp | (bits)); \ 938 back_to_back_c0_hazard(); \ 939 maxconf = read_gc0_##name(); \ 940 write_gc0_##name(tmp); \ 941 } while (0) 942 943 /* 944 * Probe for dynamic guest capabilities by changing certain config bits and 945 * reading back to see if they change. Finally write back the original value. 946 */ 947 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 948 do { \ 949 maxconf = read_gc0_##name(); \ 950 write_gc0_##name(maxconf ^ (bits)); \ 951 back_to_back_c0_hazard(); \ 952 dynconf = maxconf ^ read_gc0_##name(); \ 953 write_gc0_##name(maxconf); \ 954 maxconf |= dynconf; \ 955 } while (0) 956 957 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 958 { 959 unsigned int config0; 960 961 probe_gc0_config(config, config0, MIPS_CONF_M); 962 963 if (config0 & MIPS_CONF_M) 964 c->guest.conf |= BIT(1); 965 return config0 & MIPS_CONF_M; 966 } 967 968 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 969 { 970 unsigned int config1, config1_dyn; 971 972 probe_gc0_config_dyn(config1, config1, config1_dyn, 973 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 974 MIPS_CONF1_FP); 975 976 if (config1 & MIPS_CONF1_FP) 977 c->guest.options |= MIPS_CPU_FPU; 978 if (config1_dyn & MIPS_CONF1_FP) 979 c->guest.options_dyn |= MIPS_CPU_FPU; 980 981 if (config1 & MIPS_CONF1_WR) 982 c->guest.options |= MIPS_CPU_WATCH; 983 if (config1_dyn & MIPS_CONF1_WR) 984 c->guest.options_dyn |= MIPS_CPU_WATCH; 985 986 if (config1 & MIPS_CONF1_PC) 987 c->guest.options |= MIPS_CPU_PERF; 988 if (config1_dyn & MIPS_CONF1_PC) 989 c->guest.options_dyn |= MIPS_CPU_PERF; 990 991 if (config1 & MIPS_CONF_M) 992 c->guest.conf |= BIT(2); 993 return config1 & MIPS_CONF_M; 994 } 995 996 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 997 { 998 unsigned int config2; 999 1000 probe_gc0_config(config2, config2, MIPS_CONF_M); 1001 1002 if (config2 & MIPS_CONF_M) 1003 c->guest.conf |= BIT(3); 1004 return config2 & MIPS_CONF_M; 1005 } 1006 1007 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 1008 { 1009 unsigned int config3, config3_dyn; 1010 1011 probe_gc0_config_dyn(config3, config3, config3_dyn, 1012 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 1013 MIPS_CONF3_CTXTC); 1014 1015 if (config3 & MIPS_CONF3_CTXTC) 1016 c->guest.options |= MIPS_CPU_CTXTC; 1017 if (config3_dyn & MIPS_CONF3_CTXTC) 1018 c->guest.options_dyn |= MIPS_CPU_CTXTC; 1019 1020 if (config3 & MIPS_CONF3_PW) 1021 c->guest.options |= MIPS_CPU_HTW; 1022 1023 if (config3 & MIPS_CONF3_ULRI) 1024 c->guest.options |= MIPS_CPU_ULRI; 1025 1026 if (config3 & MIPS_CONF3_SC) 1027 c->guest.options |= MIPS_CPU_SEGMENTS; 1028 1029 if (config3 & MIPS_CONF3_BI) 1030 c->guest.options |= MIPS_CPU_BADINSTR; 1031 if (config3 & MIPS_CONF3_BP) 1032 c->guest.options |= MIPS_CPU_BADINSTRP; 1033 1034 if (config3 & MIPS_CONF3_MSA) 1035 c->guest.ases |= MIPS_ASE_MSA; 1036 if (config3_dyn & MIPS_CONF3_MSA) 1037 c->guest.ases_dyn |= MIPS_ASE_MSA; 1038 1039 if (config3 & MIPS_CONF_M) 1040 c->guest.conf |= BIT(4); 1041 return config3 & MIPS_CONF_M; 1042 } 1043 1044 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 1045 { 1046 unsigned int config4; 1047 1048 probe_gc0_config(config4, config4, 1049 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 1050 1051 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 1052 >> MIPS_CONF4_KSCREXIST_SHIFT; 1053 1054 if (config4 & MIPS_CONF_M) 1055 c->guest.conf |= BIT(5); 1056 return config4 & MIPS_CONF_M; 1057 } 1058 1059 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 1060 { 1061 unsigned int config5, config5_dyn; 1062 1063 probe_gc0_config_dyn(config5, config5, config5_dyn, 1064 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 1065 1066 if (config5 & MIPS_CONF5_MRP) 1067 c->guest.options |= MIPS_CPU_MAAR; 1068 if (config5_dyn & MIPS_CONF5_MRP) 1069 c->guest.options_dyn |= MIPS_CPU_MAAR; 1070 1071 if (config5 & MIPS_CONF5_LLB) 1072 c->guest.options |= MIPS_CPU_RW_LLB; 1073 1074 if (config5 & MIPS_CONF5_MVH) 1075 c->guest.options |= MIPS_CPU_MVH; 1076 1077 if (config5 & MIPS_CONF_M) 1078 c->guest.conf |= BIT(6); 1079 return config5 & MIPS_CONF_M; 1080 } 1081 1082 static inline void decode_guest_configs(struct cpuinfo_mips *c) 1083 { 1084 unsigned int ok; 1085 1086 ok = decode_guest_config0(c); 1087 if (ok) 1088 ok = decode_guest_config1(c); 1089 if (ok) 1090 ok = decode_guest_config2(c); 1091 if (ok) 1092 ok = decode_guest_config3(c); 1093 if (ok) 1094 ok = decode_guest_config4(c); 1095 if (ok) 1096 decode_guest_config5(c); 1097 } 1098 1099 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 1100 { 1101 unsigned int guestctl0, temp; 1102 1103 guestctl0 = read_c0_guestctl0(); 1104 1105 if (guestctl0 & MIPS_GCTL0_G0E) 1106 c->options |= MIPS_CPU_GUESTCTL0EXT; 1107 if (guestctl0 & MIPS_GCTL0_G1) 1108 c->options |= MIPS_CPU_GUESTCTL1; 1109 if (guestctl0 & MIPS_GCTL0_G2) 1110 c->options |= MIPS_CPU_GUESTCTL2; 1111 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 1112 c->options |= MIPS_CPU_GUESTID; 1113 1114 /* 1115 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 1116 * first, otherwise all data accesses will be fully virtualised 1117 * as if they were performed by guest mode. 1118 */ 1119 write_c0_guestctl1(0); 1120 tlbw_use_hazard(); 1121 1122 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 1123 back_to_back_c0_hazard(); 1124 temp = read_c0_guestctl0(); 1125 1126 if (temp & MIPS_GCTL0_DRG) { 1127 write_c0_guestctl0(guestctl0); 1128 c->options |= MIPS_CPU_DRG; 1129 } 1130 } 1131 } 1132 1133 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1134 { 1135 if (cpu_has_guestid) { 1136 /* determine the number of bits of GuestID available */ 1137 write_c0_guestctl1(MIPS_GCTL1_ID); 1138 back_to_back_c0_hazard(); 1139 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1140 >> MIPS_GCTL1_ID_SHIFT; 1141 write_c0_guestctl1(0); 1142 } 1143 } 1144 1145 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1146 { 1147 /* determine the number of bits of GTOffset available */ 1148 write_c0_gtoffset(0xffffffff); 1149 back_to_back_c0_hazard(); 1150 c->gtoffset_mask = read_c0_gtoffset(); 1151 write_c0_gtoffset(0); 1152 } 1153 1154 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1155 { 1156 cpu_probe_guestctl0(c); 1157 if (cpu_has_guestctl1) 1158 cpu_probe_guestctl1(c); 1159 1160 cpu_probe_gtoffset(c); 1161 1162 decode_guest_configs(c); 1163 } 1164 1165 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1166 | MIPS_CPU_COUNTER) 1167 1168 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1169 { 1170 switch (c->processor_id & PRID_IMP_MASK) { 1171 case PRID_IMP_R2000: 1172 c->cputype = CPU_R2000; 1173 __cpu_name[cpu] = "R2000"; 1174 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1175 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1176 MIPS_CPU_NOFPUEX; 1177 if (__cpu_has_fpu()) 1178 c->options |= MIPS_CPU_FPU; 1179 c->tlbsize = 64; 1180 break; 1181 case PRID_IMP_R3000: 1182 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1183 if (cpu_has_confreg()) { 1184 c->cputype = CPU_R3081E; 1185 __cpu_name[cpu] = "R3081"; 1186 } else { 1187 c->cputype = CPU_R3000A; 1188 __cpu_name[cpu] = "R3000A"; 1189 } 1190 } else { 1191 c->cputype = CPU_R3000; 1192 __cpu_name[cpu] = "R3000"; 1193 } 1194 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1195 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1196 MIPS_CPU_NOFPUEX; 1197 if (__cpu_has_fpu()) 1198 c->options |= MIPS_CPU_FPU; 1199 c->tlbsize = 64; 1200 break; 1201 case PRID_IMP_R4000: 1202 if (read_c0_config() & CONF_SC) { 1203 if ((c->processor_id & PRID_REV_MASK) >= 1204 PRID_REV_R4400) { 1205 c->cputype = CPU_R4400PC; 1206 __cpu_name[cpu] = "R4400PC"; 1207 } else { 1208 c->cputype = CPU_R4000PC; 1209 __cpu_name[cpu] = "R4000PC"; 1210 } 1211 } else { 1212 int cca = read_c0_config() & CONF_CM_CMASK; 1213 int mc; 1214 1215 /* 1216 * SC and MC versions can't be reliably told apart, 1217 * but only the latter support coherent caching 1218 * modes so assume the firmware has set the KSEG0 1219 * coherency attribute reasonably (if uncached, we 1220 * assume SC). 1221 */ 1222 switch (cca) { 1223 case CONF_CM_CACHABLE_CE: 1224 case CONF_CM_CACHABLE_COW: 1225 case CONF_CM_CACHABLE_CUW: 1226 mc = 1; 1227 break; 1228 default: 1229 mc = 0; 1230 break; 1231 } 1232 if ((c->processor_id & PRID_REV_MASK) >= 1233 PRID_REV_R4400) { 1234 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1235 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1236 } else { 1237 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1238 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1239 } 1240 } 1241 1242 set_isa(c, MIPS_CPU_ISA_III); 1243 c->fpu_msk31 |= FPU_CSR_CONDX; 1244 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1245 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1246 MIPS_CPU_LLSC; 1247 c->tlbsize = 48; 1248 break; 1249 case PRID_IMP_VR41XX: 1250 set_isa(c, MIPS_CPU_ISA_III); 1251 c->fpu_msk31 |= FPU_CSR_CONDX; 1252 c->options = R4K_OPTS; 1253 c->tlbsize = 32; 1254 switch (c->processor_id & 0xf0) { 1255 case PRID_REV_VR4111: 1256 c->cputype = CPU_VR4111; 1257 __cpu_name[cpu] = "NEC VR4111"; 1258 break; 1259 case PRID_REV_VR4121: 1260 c->cputype = CPU_VR4121; 1261 __cpu_name[cpu] = "NEC VR4121"; 1262 break; 1263 case PRID_REV_VR4122: 1264 if ((c->processor_id & 0xf) < 0x3) { 1265 c->cputype = CPU_VR4122; 1266 __cpu_name[cpu] = "NEC VR4122"; 1267 } else { 1268 c->cputype = CPU_VR4181A; 1269 __cpu_name[cpu] = "NEC VR4181A"; 1270 } 1271 break; 1272 case PRID_REV_VR4130: 1273 if ((c->processor_id & 0xf) < 0x4) { 1274 c->cputype = CPU_VR4131; 1275 __cpu_name[cpu] = "NEC VR4131"; 1276 } else { 1277 c->cputype = CPU_VR4133; 1278 c->options |= MIPS_CPU_LLSC; 1279 __cpu_name[cpu] = "NEC VR4133"; 1280 } 1281 break; 1282 default: 1283 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1284 c->cputype = CPU_VR41XX; 1285 __cpu_name[cpu] = "NEC Vr41xx"; 1286 break; 1287 } 1288 break; 1289 case PRID_IMP_R4300: 1290 c->cputype = CPU_R4300; 1291 __cpu_name[cpu] = "R4300"; 1292 set_isa(c, MIPS_CPU_ISA_III); 1293 c->fpu_msk31 |= FPU_CSR_CONDX; 1294 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1295 MIPS_CPU_LLSC; 1296 c->tlbsize = 32; 1297 break; 1298 case PRID_IMP_R4600: 1299 c->cputype = CPU_R4600; 1300 __cpu_name[cpu] = "R4600"; 1301 set_isa(c, MIPS_CPU_ISA_III); 1302 c->fpu_msk31 |= FPU_CSR_CONDX; 1303 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1304 MIPS_CPU_LLSC; 1305 c->tlbsize = 48; 1306 break; 1307 #if 0 1308 case PRID_IMP_R4650: 1309 /* 1310 * This processor doesn't have an MMU, so it's not 1311 * "real easy" to run Linux on it. It is left purely 1312 * for documentation. Commented out because it shares 1313 * it's c0_prid id number with the TX3900. 1314 */ 1315 c->cputype = CPU_R4650; 1316 __cpu_name[cpu] = "R4650"; 1317 set_isa(c, MIPS_CPU_ISA_III); 1318 c->fpu_msk31 |= FPU_CSR_CONDX; 1319 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1320 c->tlbsize = 48; 1321 break; 1322 #endif 1323 case PRID_IMP_TX39: 1324 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1325 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1326 1327 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1328 c->cputype = CPU_TX3927; 1329 __cpu_name[cpu] = "TX3927"; 1330 c->tlbsize = 64; 1331 } else { 1332 switch (c->processor_id & PRID_REV_MASK) { 1333 case PRID_REV_TX3912: 1334 c->cputype = CPU_TX3912; 1335 __cpu_name[cpu] = "TX3912"; 1336 c->tlbsize = 32; 1337 break; 1338 case PRID_REV_TX3922: 1339 c->cputype = CPU_TX3922; 1340 __cpu_name[cpu] = "TX3922"; 1341 c->tlbsize = 64; 1342 break; 1343 } 1344 } 1345 break; 1346 case PRID_IMP_R4700: 1347 c->cputype = CPU_R4700; 1348 __cpu_name[cpu] = "R4700"; 1349 set_isa(c, MIPS_CPU_ISA_III); 1350 c->fpu_msk31 |= FPU_CSR_CONDX; 1351 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1352 MIPS_CPU_LLSC; 1353 c->tlbsize = 48; 1354 break; 1355 case PRID_IMP_TX49: 1356 c->cputype = CPU_TX49XX; 1357 __cpu_name[cpu] = "R49XX"; 1358 set_isa(c, MIPS_CPU_ISA_III); 1359 c->fpu_msk31 |= FPU_CSR_CONDX; 1360 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1361 if (!(c->processor_id & 0x08)) 1362 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1363 c->tlbsize = 48; 1364 break; 1365 case PRID_IMP_R5000: 1366 c->cputype = CPU_R5000; 1367 __cpu_name[cpu] = "R5000"; 1368 set_isa(c, MIPS_CPU_ISA_IV); 1369 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1370 MIPS_CPU_LLSC; 1371 c->tlbsize = 48; 1372 break; 1373 case PRID_IMP_R5432: 1374 c->cputype = CPU_R5432; 1375 __cpu_name[cpu] = "R5432"; 1376 set_isa(c, MIPS_CPU_ISA_IV); 1377 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1378 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1379 c->tlbsize = 48; 1380 break; 1381 case PRID_IMP_R5500: 1382 c->cputype = CPU_R5500; 1383 __cpu_name[cpu] = "R5500"; 1384 set_isa(c, MIPS_CPU_ISA_IV); 1385 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1386 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1387 c->tlbsize = 48; 1388 break; 1389 case PRID_IMP_NEVADA: 1390 c->cputype = CPU_NEVADA; 1391 __cpu_name[cpu] = "Nevada"; 1392 set_isa(c, MIPS_CPU_ISA_IV); 1393 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1394 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1395 c->tlbsize = 48; 1396 break; 1397 case PRID_IMP_R6000: 1398 c->cputype = CPU_R6000; 1399 __cpu_name[cpu] = "R6000"; 1400 set_isa(c, MIPS_CPU_ISA_II); 1401 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1402 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1403 MIPS_CPU_LLSC; 1404 c->tlbsize = 32; 1405 break; 1406 case PRID_IMP_R6000A: 1407 c->cputype = CPU_R6000A; 1408 __cpu_name[cpu] = "R6000A"; 1409 set_isa(c, MIPS_CPU_ISA_II); 1410 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1411 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1412 MIPS_CPU_LLSC; 1413 c->tlbsize = 32; 1414 break; 1415 case PRID_IMP_RM7000: 1416 c->cputype = CPU_RM7000; 1417 __cpu_name[cpu] = "RM7000"; 1418 set_isa(c, MIPS_CPU_ISA_IV); 1419 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1420 MIPS_CPU_LLSC; 1421 /* 1422 * Undocumented RM7000: Bit 29 in the info register of 1423 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1424 * entries. 1425 * 1426 * 29 1 => 64 entry JTLB 1427 * 0 => 48 entry JTLB 1428 */ 1429 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1430 break; 1431 case PRID_IMP_R8000: 1432 c->cputype = CPU_R8000; 1433 __cpu_name[cpu] = "RM8000"; 1434 set_isa(c, MIPS_CPU_ISA_IV); 1435 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 1436 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1437 MIPS_CPU_LLSC; 1438 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 1439 break; 1440 case PRID_IMP_R10000: 1441 c->cputype = CPU_R10000; 1442 __cpu_name[cpu] = "R10000"; 1443 set_isa(c, MIPS_CPU_ISA_IV); 1444 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1445 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1446 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1447 MIPS_CPU_LLSC; 1448 c->tlbsize = 64; 1449 break; 1450 case PRID_IMP_R12000: 1451 c->cputype = CPU_R12000; 1452 __cpu_name[cpu] = "R12000"; 1453 set_isa(c, MIPS_CPU_ISA_IV); 1454 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1455 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1456 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1457 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1458 c->tlbsize = 64; 1459 break; 1460 case PRID_IMP_R14000: 1461 if (((c->processor_id >> 4) & 0x0f) > 2) { 1462 c->cputype = CPU_R16000; 1463 __cpu_name[cpu] = "R16000"; 1464 } else { 1465 c->cputype = CPU_R14000; 1466 __cpu_name[cpu] = "R14000"; 1467 } 1468 set_isa(c, MIPS_CPU_ISA_IV); 1469 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1470 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1471 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1472 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1473 c->tlbsize = 64; 1474 break; 1475 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1476 switch (c->processor_id & PRID_REV_MASK) { 1477 case PRID_REV_LOONGSON2E: 1478 c->cputype = CPU_LOONGSON2; 1479 __cpu_name[cpu] = "ICT Loongson-2"; 1480 set_elf_platform(cpu, "loongson2e"); 1481 set_isa(c, MIPS_CPU_ISA_III); 1482 c->fpu_msk31 |= FPU_CSR_CONDX; 1483 break; 1484 case PRID_REV_LOONGSON2F: 1485 c->cputype = CPU_LOONGSON2; 1486 __cpu_name[cpu] = "ICT Loongson-2"; 1487 set_elf_platform(cpu, "loongson2f"); 1488 set_isa(c, MIPS_CPU_ISA_III); 1489 c->fpu_msk31 |= FPU_CSR_CONDX; 1490 break; 1491 case PRID_REV_LOONGSON3A_R1: 1492 c->cputype = CPU_LOONGSON3; 1493 __cpu_name[cpu] = "ICT Loongson-3"; 1494 set_elf_platform(cpu, "loongson3a"); 1495 set_isa(c, MIPS_CPU_ISA_M64R1); 1496 break; 1497 case PRID_REV_LOONGSON3B_R1: 1498 case PRID_REV_LOONGSON3B_R2: 1499 c->cputype = CPU_LOONGSON3; 1500 __cpu_name[cpu] = "ICT Loongson-3"; 1501 set_elf_platform(cpu, "loongson3b"); 1502 set_isa(c, MIPS_CPU_ISA_M64R1); 1503 break; 1504 } 1505 1506 c->options = R4K_OPTS | 1507 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1508 MIPS_CPU_32FPR; 1509 c->tlbsize = 64; 1510 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1511 break; 1512 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1513 decode_configs(c); 1514 1515 c->cputype = CPU_LOONGSON1; 1516 1517 switch (c->processor_id & PRID_REV_MASK) { 1518 case PRID_REV_LOONGSON1B: 1519 __cpu_name[cpu] = "Loongson 1B"; 1520 break; 1521 } 1522 1523 break; 1524 } 1525 } 1526 1527 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1528 { 1529 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1530 switch (c->processor_id & PRID_IMP_MASK) { 1531 case PRID_IMP_QEMU_GENERIC: 1532 c->writecombine = _CACHE_UNCACHED; 1533 c->cputype = CPU_QEMU_GENERIC; 1534 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1535 break; 1536 case PRID_IMP_4KC: 1537 c->cputype = CPU_4KC; 1538 c->writecombine = _CACHE_UNCACHED; 1539 __cpu_name[cpu] = "MIPS 4Kc"; 1540 break; 1541 case PRID_IMP_4KEC: 1542 case PRID_IMP_4KECR2: 1543 c->cputype = CPU_4KEC; 1544 c->writecombine = _CACHE_UNCACHED; 1545 __cpu_name[cpu] = "MIPS 4KEc"; 1546 break; 1547 case PRID_IMP_4KSC: 1548 case PRID_IMP_4KSD: 1549 c->cputype = CPU_4KSC; 1550 c->writecombine = _CACHE_UNCACHED; 1551 __cpu_name[cpu] = "MIPS 4KSc"; 1552 break; 1553 case PRID_IMP_5KC: 1554 c->cputype = CPU_5KC; 1555 c->writecombine = _CACHE_UNCACHED; 1556 __cpu_name[cpu] = "MIPS 5Kc"; 1557 break; 1558 case PRID_IMP_5KE: 1559 c->cputype = CPU_5KE; 1560 c->writecombine = _CACHE_UNCACHED; 1561 __cpu_name[cpu] = "MIPS 5KE"; 1562 break; 1563 case PRID_IMP_20KC: 1564 c->cputype = CPU_20KC; 1565 c->writecombine = _CACHE_UNCACHED; 1566 __cpu_name[cpu] = "MIPS 20Kc"; 1567 break; 1568 case PRID_IMP_24K: 1569 c->cputype = CPU_24K; 1570 c->writecombine = _CACHE_UNCACHED; 1571 __cpu_name[cpu] = "MIPS 24Kc"; 1572 break; 1573 case PRID_IMP_24KE: 1574 c->cputype = CPU_24K; 1575 c->writecombine = _CACHE_UNCACHED; 1576 __cpu_name[cpu] = "MIPS 24KEc"; 1577 break; 1578 case PRID_IMP_25KF: 1579 c->cputype = CPU_25KF; 1580 c->writecombine = _CACHE_UNCACHED; 1581 __cpu_name[cpu] = "MIPS 25Kc"; 1582 break; 1583 case PRID_IMP_34K: 1584 c->cputype = CPU_34K; 1585 c->writecombine = _CACHE_UNCACHED; 1586 __cpu_name[cpu] = "MIPS 34Kc"; 1587 break; 1588 case PRID_IMP_74K: 1589 c->cputype = CPU_74K; 1590 c->writecombine = _CACHE_UNCACHED; 1591 __cpu_name[cpu] = "MIPS 74Kc"; 1592 break; 1593 case PRID_IMP_M14KC: 1594 c->cputype = CPU_M14KC; 1595 c->writecombine = _CACHE_UNCACHED; 1596 __cpu_name[cpu] = "MIPS M14Kc"; 1597 break; 1598 case PRID_IMP_M14KEC: 1599 c->cputype = CPU_M14KEC; 1600 c->writecombine = _CACHE_UNCACHED; 1601 __cpu_name[cpu] = "MIPS M14KEc"; 1602 break; 1603 case PRID_IMP_1004K: 1604 c->cputype = CPU_1004K; 1605 c->writecombine = _CACHE_UNCACHED; 1606 __cpu_name[cpu] = "MIPS 1004Kc"; 1607 break; 1608 case PRID_IMP_1074K: 1609 c->cputype = CPU_1074K; 1610 c->writecombine = _CACHE_UNCACHED; 1611 __cpu_name[cpu] = "MIPS 1074Kc"; 1612 break; 1613 case PRID_IMP_INTERAPTIV_UP: 1614 c->cputype = CPU_INTERAPTIV; 1615 __cpu_name[cpu] = "MIPS interAptiv"; 1616 break; 1617 case PRID_IMP_INTERAPTIV_MP: 1618 c->cputype = CPU_INTERAPTIV; 1619 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1620 break; 1621 case PRID_IMP_PROAPTIV_UP: 1622 c->cputype = CPU_PROAPTIV; 1623 __cpu_name[cpu] = "MIPS proAptiv"; 1624 break; 1625 case PRID_IMP_PROAPTIV_MP: 1626 c->cputype = CPU_PROAPTIV; 1627 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1628 break; 1629 case PRID_IMP_P5600: 1630 c->cputype = CPU_P5600; 1631 __cpu_name[cpu] = "MIPS P5600"; 1632 break; 1633 case PRID_IMP_P6600: 1634 c->cputype = CPU_P6600; 1635 __cpu_name[cpu] = "MIPS P6600"; 1636 break; 1637 case PRID_IMP_I6400: 1638 c->cputype = CPU_I6400; 1639 __cpu_name[cpu] = "MIPS I6400"; 1640 break; 1641 case PRID_IMP_I6500: 1642 c->cputype = CPU_I6500; 1643 __cpu_name[cpu] = "MIPS I6500"; 1644 break; 1645 case PRID_IMP_M5150: 1646 c->cputype = CPU_M5150; 1647 __cpu_name[cpu] = "MIPS M5150"; 1648 break; 1649 case PRID_IMP_M6250: 1650 c->cputype = CPU_M6250; 1651 __cpu_name[cpu] = "MIPS M6250"; 1652 break; 1653 } 1654 1655 decode_configs(c); 1656 1657 spram_config(); 1658 1659 switch (__get_cpu_type(c->cputype)) { 1660 case CPU_I6500: 1661 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1662 /* fall-through */ 1663 case CPU_I6400: 1664 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1665 /* fall-through */ 1666 default: 1667 break; 1668 } 1669 } 1670 1671 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1672 { 1673 decode_configs(c); 1674 switch (c->processor_id & PRID_IMP_MASK) { 1675 case PRID_IMP_AU1_REV1: 1676 case PRID_IMP_AU1_REV2: 1677 c->cputype = CPU_ALCHEMY; 1678 switch ((c->processor_id >> 24) & 0xff) { 1679 case 0: 1680 __cpu_name[cpu] = "Au1000"; 1681 break; 1682 case 1: 1683 __cpu_name[cpu] = "Au1500"; 1684 break; 1685 case 2: 1686 __cpu_name[cpu] = "Au1100"; 1687 break; 1688 case 3: 1689 __cpu_name[cpu] = "Au1550"; 1690 break; 1691 case 4: 1692 __cpu_name[cpu] = "Au1200"; 1693 if ((c->processor_id & PRID_REV_MASK) == 2) 1694 __cpu_name[cpu] = "Au1250"; 1695 break; 1696 case 5: 1697 __cpu_name[cpu] = "Au1210"; 1698 break; 1699 default: 1700 __cpu_name[cpu] = "Au1xxx"; 1701 break; 1702 } 1703 break; 1704 } 1705 } 1706 1707 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1708 { 1709 decode_configs(c); 1710 1711 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1712 switch (c->processor_id & PRID_IMP_MASK) { 1713 case PRID_IMP_SB1: 1714 c->cputype = CPU_SB1; 1715 __cpu_name[cpu] = "SiByte SB1"; 1716 /* FPU in pass1 is known to have issues. */ 1717 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1718 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1719 break; 1720 case PRID_IMP_SB1A: 1721 c->cputype = CPU_SB1A; 1722 __cpu_name[cpu] = "SiByte SB1A"; 1723 break; 1724 } 1725 } 1726 1727 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1728 { 1729 decode_configs(c); 1730 switch (c->processor_id & PRID_IMP_MASK) { 1731 case PRID_IMP_SR71000: 1732 c->cputype = CPU_SR71000; 1733 __cpu_name[cpu] = "Sandcraft SR71000"; 1734 c->scache.ways = 8; 1735 c->tlbsize = 64; 1736 break; 1737 } 1738 } 1739 1740 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1741 { 1742 decode_configs(c); 1743 switch (c->processor_id & PRID_IMP_MASK) { 1744 case PRID_IMP_PR4450: 1745 c->cputype = CPU_PR4450; 1746 __cpu_name[cpu] = "Philips PR4450"; 1747 set_isa(c, MIPS_CPU_ISA_M32R1); 1748 break; 1749 } 1750 } 1751 1752 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1753 { 1754 decode_configs(c); 1755 switch (c->processor_id & PRID_IMP_MASK) { 1756 case PRID_IMP_BMIPS32_REV4: 1757 case PRID_IMP_BMIPS32_REV8: 1758 c->cputype = CPU_BMIPS32; 1759 __cpu_name[cpu] = "Broadcom BMIPS32"; 1760 set_elf_platform(cpu, "bmips32"); 1761 break; 1762 case PRID_IMP_BMIPS3300: 1763 case PRID_IMP_BMIPS3300_ALT: 1764 case PRID_IMP_BMIPS3300_BUG: 1765 c->cputype = CPU_BMIPS3300; 1766 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1767 set_elf_platform(cpu, "bmips3300"); 1768 break; 1769 case PRID_IMP_BMIPS43XX: { 1770 int rev = c->processor_id & PRID_REV_MASK; 1771 1772 if (rev >= PRID_REV_BMIPS4380_LO && 1773 rev <= PRID_REV_BMIPS4380_HI) { 1774 c->cputype = CPU_BMIPS4380; 1775 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1776 set_elf_platform(cpu, "bmips4380"); 1777 c->options |= MIPS_CPU_RIXI; 1778 } else { 1779 c->cputype = CPU_BMIPS4350; 1780 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1781 set_elf_platform(cpu, "bmips4350"); 1782 } 1783 break; 1784 } 1785 case PRID_IMP_BMIPS5000: 1786 case PRID_IMP_BMIPS5200: 1787 c->cputype = CPU_BMIPS5000; 1788 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1789 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1790 else 1791 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1792 set_elf_platform(cpu, "bmips5000"); 1793 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1794 break; 1795 } 1796 } 1797 1798 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1799 { 1800 decode_configs(c); 1801 switch (c->processor_id & PRID_IMP_MASK) { 1802 case PRID_IMP_CAVIUM_CN38XX: 1803 case PRID_IMP_CAVIUM_CN31XX: 1804 case PRID_IMP_CAVIUM_CN30XX: 1805 c->cputype = CPU_CAVIUM_OCTEON; 1806 __cpu_name[cpu] = "Cavium Octeon"; 1807 goto platform; 1808 case PRID_IMP_CAVIUM_CN58XX: 1809 case PRID_IMP_CAVIUM_CN56XX: 1810 case PRID_IMP_CAVIUM_CN50XX: 1811 case PRID_IMP_CAVIUM_CN52XX: 1812 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1813 __cpu_name[cpu] = "Cavium Octeon+"; 1814 platform: 1815 set_elf_platform(cpu, "octeon"); 1816 break; 1817 case PRID_IMP_CAVIUM_CN61XX: 1818 case PRID_IMP_CAVIUM_CN63XX: 1819 case PRID_IMP_CAVIUM_CN66XX: 1820 case PRID_IMP_CAVIUM_CN68XX: 1821 case PRID_IMP_CAVIUM_CNF71XX: 1822 c->cputype = CPU_CAVIUM_OCTEON2; 1823 __cpu_name[cpu] = "Cavium Octeon II"; 1824 set_elf_platform(cpu, "octeon2"); 1825 break; 1826 case PRID_IMP_CAVIUM_CN70XX: 1827 case PRID_IMP_CAVIUM_CN73XX: 1828 case PRID_IMP_CAVIUM_CNF75XX: 1829 case PRID_IMP_CAVIUM_CN78XX: 1830 c->cputype = CPU_CAVIUM_OCTEON3; 1831 __cpu_name[cpu] = "Cavium Octeon III"; 1832 set_elf_platform(cpu, "octeon3"); 1833 break; 1834 default: 1835 printk(KERN_INFO "Unknown Octeon chip!\n"); 1836 c->cputype = CPU_UNKNOWN; 1837 break; 1838 } 1839 } 1840 1841 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1842 { 1843 switch (c->processor_id & PRID_IMP_MASK) { 1844 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1845 switch (c->processor_id & PRID_REV_MASK) { 1846 case PRID_REV_LOONGSON3A_R2: 1847 c->cputype = CPU_LOONGSON3; 1848 __cpu_name[cpu] = "ICT Loongson-3"; 1849 set_elf_platform(cpu, "loongson3a"); 1850 set_isa(c, MIPS_CPU_ISA_M64R2); 1851 break; 1852 case PRID_REV_LOONGSON3A_R3: 1853 c->cputype = CPU_LOONGSON3; 1854 __cpu_name[cpu] = "ICT Loongson-3"; 1855 set_elf_platform(cpu, "loongson3a"); 1856 set_isa(c, MIPS_CPU_ISA_M64R2); 1857 break; 1858 } 1859 1860 decode_configs(c); 1861 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1862 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1863 break; 1864 default: 1865 panic("Unknown Loongson Processor ID!"); 1866 break; 1867 } 1868 } 1869 1870 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1871 { 1872 decode_configs(c); 1873 /* JZRISC does not implement the CP0 counter. */ 1874 c->options &= ~MIPS_CPU_COUNTER; 1875 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1876 switch (c->processor_id & PRID_IMP_MASK) { 1877 case PRID_IMP_JZRISC: 1878 c->cputype = CPU_JZRISC; 1879 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1880 __cpu_name[cpu] = "Ingenic JZRISC"; 1881 break; 1882 default: 1883 panic("Unknown Ingenic Processor ID!"); 1884 break; 1885 } 1886 } 1887 1888 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1889 { 1890 decode_configs(c); 1891 1892 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1893 c->cputype = CPU_ALCHEMY; 1894 __cpu_name[cpu] = "Au1300"; 1895 /* following stuff is not for Alchemy */ 1896 return; 1897 } 1898 1899 c->options = (MIPS_CPU_TLB | 1900 MIPS_CPU_4KEX | 1901 MIPS_CPU_COUNTER | 1902 MIPS_CPU_DIVEC | 1903 MIPS_CPU_WATCH | 1904 MIPS_CPU_EJTAG | 1905 MIPS_CPU_LLSC); 1906 1907 switch (c->processor_id & PRID_IMP_MASK) { 1908 case PRID_IMP_NETLOGIC_XLP2XX: 1909 case PRID_IMP_NETLOGIC_XLP9XX: 1910 case PRID_IMP_NETLOGIC_XLP5XX: 1911 c->cputype = CPU_XLP; 1912 __cpu_name[cpu] = "Broadcom XLPII"; 1913 break; 1914 1915 case PRID_IMP_NETLOGIC_XLP8XX: 1916 case PRID_IMP_NETLOGIC_XLP3XX: 1917 c->cputype = CPU_XLP; 1918 __cpu_name[cpu] = "Netlogic XLP"; 1919 break; 1920 1921 case PRID_IMP_NETLOGIC_XLR732: 1922 case PRID_IMP_NETLOGIC_XLR716: 1923 case PRID_IMP_NETLOGIC_XLR532: 1924 case PRID_IMP_NETLOGIC_XLR308: 1925 case PRID_IMP_NETLOGIC_XLR532C: 1926 case PRID_IMP_NETLOGIC_XLR516C: 1927 case PRID_IMP_NETLOGIC_XLR508C: 1928 case PRID_IMP_NETLOGIC_XLR308C: 1929 c->cputype = CPU_XLR; 1930 __cpu_name[cpu] = "Netlogic XLR"; 1931 break; 1932 1933 case PRID_IMP_NETLOGIC_XLS608: 1934 case PRID_IMP_NETLOGIC_XLS408: 1935 case PRID_IMP_NETLOGIC_XLS404: 1936 case PRID_IMP_NETLOGIC_XLS208: 1937 case PRID_IMP_NETLOGIC_XLS204: 1938 case PRID_IMP_NETLOGIC_XLS108: 1939 case PRID_IMP_NETLOGIC_XLS104: 1940 case PRID_IMP_NETLOGIC_XLS616B: 1941 case PRID_IMP_NETLOGIC_XLS608B: 1942 case PRID_IMP_NETLOGIC_XLS416B: 1943 case PRID_IMP_NETLOGIC_XLS412B: 1944 case PRID_IMP_NETLOGIC_XLS408B: 1945 case PRID_IMP_NETLOGIC_XLS404B: 1946 c->cputype = CPU_XLR; 1947 __cpu_name[cpu] = "Netlogic XLS"; 1948 break; 1949 1950 default: 1951 pr_info("Unknown Netlogic chip id [%02x]!\n", 1952 c->processor_id); 1953 c->cputype = CPU_XLR; 1954 break; 1955 } 1956 1957 if (c->cputype == CPU_XLP) { 1958 set_isa(c, MIPS_CPU_ISA_M64R2); 1959 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1960 /* This will be updated again after all threads are woken up */ 1961 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1962 } else { 1963 set_isa(c, MIPS_CPU_ISA_M64R1); 1964 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1965 } 1966 c->kscratch_mask = 0xf; 1967 } 1968 1969 #ifdef CONFIG_64BIT 1970 /* For use by uaccess.h */ 1971 u64 __ua_limit; 1972 EXPORT_SYMBOL(__ua_limit); 1973 #endif 1974 1975 const char *__cpu_name[NR_CPUS]; 1976 const char *__elf_platform; 1977 1978 void cpu_probe(void) 1979 { 1980 struct cpuinfo_mips *c = ¤t_cpu_data; 1981 unsigned int cpu = smp_processor_id(); 1982 1983 /* 1984 * Set a default elf platform, cpu probe may later 1985 * overwrite it with a more precise value 1986 */ 1987 set_elf_platform(cpu, "mips"); 1988 1989 c->processor_id = PRID_IMP_UNKNOWN; 1990 c->fpu_id = FPIR_IMP_NONE; 1991 c->cputype = CPU_UNKNOWN; 1992 c->writecombine = _CACHE_UNCACHED; 1993 1994 c->fpu_csr31 = FPU_CSR_RN; 1995 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1996 1997 c->processor_id = read_c0_prid(); 1998 switch (c->processor_id & PRID_COMP_MASK) { 1999 case PRID_COMP_LEGACY: 2000 cpu_probe_legacy(c, cpu); 2001 break; 2002 case PRID_COMP_MIPS: 2003 cpu_probe_mips(c, cpu); 2004 break; 2005 case PRID_COMP_ALCHEMY: 2006 cpu_probe_alchemy(c, cpu); 2007 break; 2008 case PRID_COMP_SIBYTE: 2009 cpu_probe_sibyte(c, cpu); 2010 break; 2011 case PRID_COMP_BROADCOM: 2012 cpu_probe_broadcom(c, cpu); 2013 break; 2014 case PRID_COMP_SANDCRAFT: 2015 cpu_probe_sandcraft(c, cpu); 2016 break; 2017 case PRID_COMP_NXP: 2018 cpu_probe_nxp(c, cpu); 2019 break; 2020 case PRID_COMP_CAVIUM: 2021 cpu_probe_cavium(c, cpu); 2022 break; 2023 case PRID_COMP_LOONGSON: 2024 cpu_probe_loongson(c, cpu); 2025 break; 2026 case PRID_COMP_INGENIC_D0: 2027 case PRID_COMP_INGENIC_D1: 2028 case PRID_COMP_INGENIC_E1: 2029 cpu_probe_ingenic(c, cpu); 2030 break; 2031 case PRID_COMP_NETLOGIC: 2032 cpu_probe_netlogic(c, cpu); 2033 break; 2034 } 2035 2036 BUG_ON(!__cpu_name[cpu]); 2037 BUG_ON(c->cputype == CPU_UNKNOWN); 2038 2039 /* 2040 * Platform code can force the cpu type to optimize code 2041 * generation. In that case be sure the cpu type is correctly 2042 * manually setup otherwise it could trigger some nasty bugs. 2043 */ 2044 BUG_ON(current_cpu_type() != c->cputype); 2045 2046 if (cpu_has_rixi) { 2047 /* Enable the RIXI exceptions */ 2048 set_c0_pagegrain(PG_IEC); 2049 back_to_back_c0_hazard(); 2050 /* Verify the IEC bit is set */ 2051 if (read_c0_pagegrain() & PG_IEC) 2052 c->options |= MIPS_CPU_RIXIEX; 2053 } 2054 2055 if (mips_fpu_disabled) 2056 c->options &= ~MIPS_CPU_FPU; 2057 2058 if (mips_dsp_disabled) 2059 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2060 2061 if (mips_htw_disabled) { 2062 c->options &= ~MIPS_CPU_HTW; 2063 write_c0_pwctl(read_c0_pwctl() & 2064 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2065 } 2066 2067 if (c->options & MIPS_CPU_FPU) 2068 cpu_set_fpu_opts(c); 2069 else 2070 cpu_set_nofpu_opts(c); 2071 2072 if (cpu_has_bp_ghist) 2073 write_c0_r10k_diag(read_c0_r10k_diag() | 2074 R10K_DIAG_E_GHIST); 2075 2076 if (cpu_has_mips_r2_r6) { 2077 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2078 /* R2 has Performance Counter Interrupt indicator */ 2079 c->options |= MIPS_CPU_PCI; 2080 } 2081 else 2082 c->srsets = 1; 2083 2084 if (cpu_has_mips_r6) 2085 elf_hwcap |= HWCAP_MIPS_R6; 2086 2087 if (cpu_has_msa) { 2088 c->msa_id = cpu_get_msa_id(); 2089 WARN(c->msa_id & MSA_IR_WRPF, 2090 "Vector register partitioning unimplemented!"); 2091 elf_hwcap |= HWCAP_MIPS_MSA; 2092 } 2093 2094 if (cpu_has_vz) 2095 cpu_probe_vz(c); 2096 2097 cpu_probe_vmbits(c); 2098 2099 #ifdef CONFIG_64BIT 2100 if (cpu == 0) 2101 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2102 #endif 2103 } 2104 2105 void cpu_report(void) 2106 { 2107 struct cpuinfo_mips *c = ¤t_cpu_data; 2108 2109 pr_info("CPU%d revision is: %08x (%s)\n", 2110 smp_processor_id(), c->processor_id, cpu_name_string()); 2111 if (c->options & MIPS_CPU_FPU) 2112 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2113 if (cpu_has_msa) 2114 pr_info("MSA revision is: %08x\n", c->msa_id); 2115 } 2116