1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/mipsmtregs.h> 27 #include <asm/msa.h> 28 #include <asm/watch.h> 29 #include <asm/elf.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/spram.h> 32 #include <asm/uaccess.h> 33 34 static int mips_fpu_disabled; 35 36 static int __init fpu_disable(char *s) 37 { 38 cpu_data[0].options &= ~MIPS_CPU_FPU; 39 mips_fpu_disabled = 1; 40 41 return 1; 42 } 43 44 __setup("nofpu", fpu_disable); 45 46 int mips_dsp_disabled; 47 48 static int __init dsp_disable(char *s) 49 { 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 51 mips_dsp_disabled = 1; 52 53 return 1; 54 } 55 56 __setup("nodsp", dsp_disable); 57 58 static int mips_htw_disabled; 59 60 static int __init htw_disable(char *s) 61 { 62 mips_htw_disabled = 1; 63 cpu_data[0].options &= ~MIPS_CPU_HTW; 64 write_c0_pwctl(read_c0_pwctl() & 65 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 66 67 return 1; 68 } 69 70 __setup("nohtw", htw_disable); 71 72 static int mips_ftlb_disabled; 73 static int mips_has_ftlb_configured; 74 75 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); 76 77 static int __init ftlb_disable(char *s) 78 { 79 unsigned int config4, mmuextdef; 80 81 /* 82 * If the core hasn't done any FTLB configuration, there is nothing 83 * for us to do here. 84 */ 85 if (!mips_has_ftlb_configured) 86 return 1; 87 88 /* Disable it in the boot cpu */ 89 set_ftlb_enable(&cpu_data[0], 0); 90 91 back_to_back_c0_hazard(); 92 93 config4 = read_c0_config4(); 94 95 /* Check that FTLB has been disabled */ 96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 99 /* This should never happen */ 100 pr_warn("FTLB could not be disabled!\n"); 101 return 1; 102 } 103 104 mips_ftlb_disabled = 1; 105 mips_has_ftlb_configured = 0; 106 107 /* 108 * noftlb is mainly used for debug purposes so print 109 * an informative message instead of using pr_debug() 110 */ 111 pr_info("FTLB has been disabled\n"); 112 113 /* 114 * Some of these bits are duplicated in the decode_config4. 115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 116 * once FTLB has been disabled so undo what decode_config4 did. 117 */ 118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 119 cpu_data[0].tlbsizeftlbsets; 120 cpu_data[0].tlbsizeftlbsets = 0; 121 cpu_data[0].tlbsizeftlbways = 0; 122 123 return 1; 124 } 125 126 __setup("noftlb", ftlb_disable); 127 128 129 static inline void check_errata(void) 130 { 131 struct cpuinfo_mips *c = ¤t_cpu_data; 132 133 switch (current_cpu_type()) { 134 case CPU_34K: 135 /* 136 * Erratum "RPS May Cause Incorrect Instruction Execution" 137 * This code only handles VPE0, any SMP/RTOS code 138 * making use of VPE1 will be responsable for that VPE. 139 */ 140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 142 break; 143 default: 144 break; 145 } 146 } 147 148 void __init check_bugs32(void) 149 { 150 check_errata(); 151 } 152 153 /* 154 * Probe whether cpu has config register by trying to play with 155 * alternate cache bit and see whether it matters. 156 * It's used by cpu_probe to distinguish between R3000A and R3081. 157 */ 158 static inline int cpu_has_confreg(void) 159 { 160 #ifdef CONFIG_CPU_R3000 161 extern unsigned long r3k_cache_size(unsigned long); 162 unsigned long size1, size2; 163 unsigned long cfg = read_c0_conf(); 164 165 size1 = r3k_cache_size(ST0_ISC); 166 write_c0_conf(cfg ^ R30XX_CONF_AC); 167 size2 = r3k_cache_size(ST0_ISC); 168 write_c0_conf(cfg); 169 return size1 != size2; 170 #else 171 return 0; 172 #endif 173 } 174 175 static inline void set_elf_platform(int cpu, const char *plat) 176 { 177 if (cpu == 0) 178 __elf_platform = plat; 179 } 180 181 /* 182 * Get the FPU Implementation/Revision. 183 */ 184 static inline unsigned long cpu_get_fpu_id(void) 185 { 186 unsigned long tmp, fpu_id; 187 188 tmp = read_c0_status(); 189 __enable_fpu(FPU_AS_IS); 190 fpu_id = read_32bit_cp1_register(CP1_REVISION); 191 write_c0_status(tmp); 192 return fpu_id; 193 } 194 195 /* 196 * Check the CPU has an FPU the official way. 197 */ 198 static inline int __cpu_has_fpu(void) 199 { 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 201 } 202 203 static inline unsigned long cpu_get_msa_id(void) 204 { 205 unsigned long status, msa_id; 206 207 status = read_c0_status(); 208 __enable_fpu(FPU_64BIT); 209 enable_msa(); 210 msa_id = read_msa_ir(); 211 disable_msa(); 212 write_c0_status(status); 213 return msa_id; 214 } 215 216 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 217 { 218 #ifdef __NEED_VMBITS_PROBE 219 write_c0_entryhi(0x3fffffffffffe000ULL); 220 back_to_back_c0_hazard(); 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 222 #endif 223 } 224 225 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 226 { 227 switch (isa) { 228 case MIPS_CPU_ISA_M64R2: 229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 230 case MIPS_CPU_ISA_M64R1: 231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 232 case MIPS_CPU_ISA_V: 233 c->isa_level |= MIPS_CPU_ISA_V; 234 case MIPS_CPU_ISA_IV: 235 c->isa_level |= MIPS_CPU_ISA_IV; 236 case MIPS_CPU_ISA_III: 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 238 break; 239 240 case MIPS_CPU_ISA_M32R2: 241 c->isa_level |= MIPS_CPU_ISA_M32R2; 242 case MIPS_CPU_ISA_M32R1: 243 c->isa_level |= MIPS_CPU_ISA_M32R1; 244 case MIPS_CPU_ISA_II: 245 c->isa_level |= MIPS_CPU_ISA_II; 246 break; 247 } 248 } 249 250 static char unknown_isa[] = KERN_ERR \ 251 "Unsupported ISA type, c0.config0: %d."; 252 253 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 254 { 255 256 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 257 258 /* 259 * 0 = All TLBWR instructions go to FTLB 260 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 261 * FTLB and 1 goes to the VTLB. 262 * 2 = 7:1: As above with 7:1 ratio. 263 * 3 = 3:1: As above with 3:1 ratio. 264 * 265 * Use the linear midpoint as the probability threshold. 266 */ 267 if (probability >= 12) 268 return 1; 269 else if (probability >= 6) 270 return 2; 271 else 272 /* 273 * So FTLB is less than 4 times bigger than VTLB. 274 * A 3:1 ratio can still be useful though. 275 */ 276 return 3; 277 } 278 279 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 280 { 281 unsigned int config6; 282 283 /* It's implementation dependent how the FTLB can be enabled */ 284 switch (c->cputype) { 285 case CPU_PROAPTIV: 286 case CPU_P5600: 287 /* proAptiv & related cores use Config6 to enable the FTLB */ 288 config6 = read_c0_config6(); 289 /* Clear the old probability value */ 290 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 291 if (enable) 292 /* Enable FTLB */ 293 write_c0_config6(config6 | 294 (calculate_ftlb_probability(c) 295 << MIPS_CONF6_FTLBP_SHIFT) 296 | MIPS_CONF6_FTLBEN); 297 else 298 /* Disable FTLB */ 299 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 300 back_to_back_c0_hazard(); 301 break; 302 } 303 } 304 305 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 306 { 307 unsigned int config0; 308 int isa; 309 310 config0 = read_c0_config(); 311 312 /* 313 * Look for Standard TLB or Dual VTLB and FTLB 314 */ 315 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 316 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 317 c->options |= MIPS_CPU_TLB; 318 319 isa = (config0 & MIPS_CONF_AT) >> 13; 320 switch (isa) { 321 case 0: 322 switch ((config0 & MIPS_CONF_AR) >> 10) { 323 case 0: 324 set_isa(c, MIPS_CPU_ISA_M32R1); 325 break; 326 case 1: 327 set_isa(c, MIPS_CPU_ISA_M32R2); 328 break; 329 default: 330 goto unknown; 331 } 332 break; 333 case 2: 334 switch ((config0 & MIPS_CONF_AR) >> 10) { 335 case 0: 336 set_isa(c, MIPS_CPU_ISA_M64R1); 337 break; 338 case 1: 339 set_isa(c, MIPS_CPU_ISA_M64R2); 340 break; 341 default: 342 goto unknown; 343 } 344 break; 345 default: 346 goto unknown; 347 } 348 349 return config0 & MIPS_CONF_M; 350 351 unknown: 352 panic(unknown_isa, config0); 353 } 354 355 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 356 { 357 unsigned int config1; 358 359 config1 = read_c0_config1(); 360 361 if (config1 & MIPS_CONF1_MD) 362 c->ases |= MIPS_ASE_MDMX; 363 if (config1 & MIPS_CONF1_WR) 364 c->options |= MIPS_CPU_WATCH; 365 if (config1 & MIPS_CONF1_CA) 366 c->ases |= MIPS_ASE_MIPS16; 367 if (config1 & MIPS_CONF1_EP) 368 c->options |= MIPS_CPU_EJTAG; 369 if (config1 & MIPS_CONF1_FP) { 370 c->options |= MIPS_CPU_FPU; 371 c->options |= MIPS_CPU_32FPR; 372 } 373 if (cpu_has_tlb) { 374 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 375 c->tlbsizevtlb = c->tlbsize; 376 c->tlbsizeftlbsets = 0; 377 } 378 379 return config1 & MIPS_CONF_M; 380 } 381 382 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 383 { 384 unsigned int config2; 385 386 config2 = read_c0_config2(); 387 388 if (config2 & MIPS_CONF2_SL) 389 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 390 391 return config2 & MIPS_CONF_M; 392 } 393 394 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 395 { 396 unsigned int config3; 397 398 config3 = read_c0_config3(); 399 400 if (config3 & MIPS_CONF3_SM) { 401 c->ases |= MIPS_ASE_SMARTMIPS; 402 c->options |= MIPS_CPU_RIXI; 403 } 404 if (config3 & MIPS_CONF3_RXI) 405 c->options |= MIPS_CPU_RIXI; 406 if (config3 & MIPS_CONF3_DSP) 407 c->ases |= MIPS_ASE_DSP; 408 if (config3 & MIPS_CONF3_DSP2P) 409 c->ases |= MIPS_ASE_DSP2P; 410 if (config3 & MIPS_CONF3_VINT) 411 c->options |= MIPS_CPU_VINT; 412 if (config3 & MIPS_CONF3_VEIC) 413 c->options |= MIPS_CPU_VEIC; 414 if (config3 & MIPS_CONF3_MT) 415 c->ases |= MIPS_ASE_MIPSMT; 416 if (config3 & MIPS_CONF3_ULRI) 417 c->options |= MIPS_CPU_ULRI; 418 if (config3 & MIPS_CONF3_ISA) 419 c->options |= MIPS_CPU_MICROMIPS; 420 if (config3 & MIPS_CONF3_VZ) 421 c->ases |= MIPS_ASE_VZ; 422 if (config3 & MIPS_CONF3_SC) 423 c->options |= MIPS_CPU_SEGMENTS; 424 if (config3 & MIPS_CONF3_MSA) 425 c->ases |= MIPS_ASE_MSA; 426 /* Only tested on 32-bit cores */ 427 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) 428 c->options |= MIPS_CPU_HTW; 429 430 return config3 & MIPS_CONF_M; 431 } 432 433 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 434 { 435 unsigned int config4; 436 unsigned int newcf4; 437 unsigned int mmuextdef; 438 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 439 440 config4 = read_c0_config4(); 441 442 if (cpu_has_tlb) { 443 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 444 c->options |= MIPS_CPU_TLBINV; 445 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 446 switch (mmuextdef) { 447 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 448 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 449 c->tlbsizevtlb = c->tlbsize; 450 break; 451 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 452 c->tlbsizevtlb += 453 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 454 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 455 c->tlbsize = c->tlbsizevtlb; 456 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 457 /* fall through */ 458 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 459 if (mips_ftlb_disabled) 460 break; 461 newcf4 = (config4 & ~ftlb_page) | 462 (page_size_ftlb(mmuextdef) << 463 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 464 write_c0_config4(newcf4); 465 back_to_back_c0_hazard(); 466 config4 = read_c0_config4(); 467 if (config4 != newcf4) { 468 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 469 PAGE_SIZE, config4); 470 /* Switch FTLB off */ 471 set_ftlb_enable(c, 0); 472 break; 473 } 474 c->tlbsizeftlbsets = 1 << 475 ((config4 & MIPS_CONF4_FTLBSETS) >> 476 MIPS_CONF4_FTLBSETS_SHIFT); 477 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 478 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 479 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 480 mips_has_ftlb_configured = 1; 481 break; 482 } 483 } 484 485 c->kscratch_mask = (config4 >> 16) & 0xff; 486 487 return config4 & MIPS_CONF_M; 488 } 489 490 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 491 { 492 unsigned int config5; 493 494 config5 = read_c0_config5(); 495 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 496 write_c0_config5(config5); 497 498 if (config5 & MIPS_CONF5_EVA) 499 c->options |= MIPS_CPU_EVA; 500 if (config5 & MIPS_CONF5_MRP) 501 c->options |= MIPS_CPU_MAAR; 502 503 return config5 & MIPS_CONF_M; 504 } 505 506 static void decode_configs(struct cpuinfo_mips *c) 507 { 508 int ok; 509 510 /* MIPS32 or MIPS64 compliant CPU. */ 511 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 512 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 513 514 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 515 516 /* Enable FTLB if present and not disabled */ 517 set_ftlb_enable(c, !mips_ftlb_disabled); 518 519 ok = decode_config0(c); /* Read Config registers. */ 520 BUG_ON(!ok); /* Arch spec violation! */ 521 if (ok) 522 ok = decode_config1(c); 523 if (ok) 524 ok = decode_config2(c); 525 if (ok) 526 ok = decode_config3(c); 527 if (ok) 528 ok = decode_config4(c); 529 if (ok) 530 ok = decode_config5(c); 531 532 mips_probe_watch_registers(c); 533 534 if (cpu_has_rixi) { 535 /* Enable the RIXI exceptions */ 536 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); 537 back_to_back_c0_hazard(); 538 /* Verify the IEC bit is set */ 539 if (read_c0_pagegrain() & PG_IEC) 540 c->options |= MIPS_CPU_RIXIEX; 541 } 542 543 #ifndef CONFIG_MIPS_CPS 544 if (cpu_has_mips_r2) { 545 c->core = get_ebase_cpunum(); 546 if (cpu_has_mipsmt) 547 c->core >>= fls(core_nvpes()) - 1; 548 } 549 #endif 550 } 551 552 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 553 | MIPS_CPU_COUNTER) 554 555 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 556 { 557 switch (c->processor_id & PRID_IMP_MASK) { 558 case PRID_IMP_R2000: 559 c->cputype = CPU_R2000; 560 __cpu_name[cpu] = "R2000"; 561 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 562 MIPS_CPU_NOFPUEX; 563 if (__cpu_has_fpu()) 564 c->options |= MIPS_CPU_FPU; 565 c->tlbsize = 64; 566 break; 567 case PRID_IMP_R3000: 568 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 569 if (cpu_has_confreg()) { 570 c->cputype = CPU_R3081E; 571 __cpu_name[cpu] = "R3081"; 572 } else { 573 c->cputype = CPU_R3000A; 574 __cpu_name[cpu] = "R3000A"; 575 } 576 } else { 577 c->cputype = CPU_R3000; 578 __cpu_name[cpu] = "R3000"; 579 } 580 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 581 MIPS_CPU_NOFPUEX; 582 if (__cpu_has_fpu()) 583 c->options |= MIPS_CPU_FPU; 584 c->tlbsize = 64; 585 break; 586 case PRID_IMP_R4000: 587 if (read_c0_config() & CONF_SC) { 588 if ((c->processor_id & PRID_REV_MASK) >= 589 PRID_REV_R4400) { 590 c->cputype = CPU_R4400PC; 591 __cpu_name[cpu] = "R4400PC"; 592 } else { 593 c->cputype = CPU_R4000PC; 594 __cpu_name[cpu] = "R4000PC"; 595 } 596 } else { 597 int cca = read_c0_config() & CONF_CM_CMASK; 598 int mc; 599 600 /* 601 * SC and MC versions can't be reliably told apart, 602 * but only the latter support coherent caching 603 * modes so assume the firmware has set the KSEG0 604 * coherency attribute reasonably (if uncached, we 605 * assume SC). 606 */ 607 switch (cca) { 608 case CONF_CM_CACHABLE_CE: 609 case CONF_CM_CACHABLE_COW: 610 case CONF_CM_CACHABLE_CUW: 611 mc = 1; 612 break; 613 default: 614 mc = 0; 615 break; 616 } 617 if ((c->processor_id & PRID_REV_MASK) >= 618 PRID_REV_R4400) { 619 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 620 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 621 } else { 622 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 623 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 624 } 625 } 626 627 set_isa(c, MIPS_CPU_ISA_III); 628 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 629 MIPS_CPU_WATCH | MIPS_CPU_VCE | 630 MIPS_CPU_LLSC; 631 c->tlbsize = 48; 632 break; 633 case PRID_IMP_VR41XX: 634 set_isa(c, MIPS_CPU_ISA_III); 635 c->options = R4K_OPTS; 636 c->tlbsize = 32; 637 switch (c->processor_id & 0xf0) { 638 case PRID_REV_VR4111: 639 c->cputype = CPU_VR4111; 640 __cpu_name[cpu] = "NEC VR4111"; 641 break; 642 case PRID_REV_VR4121: 643 c->cputype = CPU_VR4121; 644 __cpu_name[cpu] = "NEC VR4121"; 645 break; 646 case PRID_REV_VR4122: 647 if ((c->processor_id & 0xf) < 0x3) { 648 c->cputype = CPU_VR4122; 649 __cpu_name[cpu] = "NEC VR4122"; 650 } else { 651 c->cputype = CPU_VR4181A; 652 __cpu_name[cpu] = "NEC VR4181A"; 653 } 654 break; 655 case PRID_REV_VR4130: 656 if ((c->processor_id & 0xf) < 0x4) { 657 c->cputype = CPU_VR4131; 658 __cpu_name[cpu] = "NEC VR4131"; 659 } else { 660 c->cputype = CPU_VR4133; 661 c->options |= MIPS_CPU_LLSC; 662 __cpu_name[cpu] = "NEC VR4133"; 663 } 664 break; 665 default: 666 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 667 c->cputype = CPU_VR41XX; 668 __cpu_name[cpu] = "NEC Vr41xx"; 669 break; 670 } 671 break; 672 case PRID_IMP_R4300: 673 c->cputype = CPU_R4300; 674 __cpu_name[cpu] = "R4300"; 675 set_isa(c, MIPS_CPU_ISA_III); 676 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 677 MIPS_CPU_LLSC; 678 c->tlbsize = 32; 679 break; 680 case PRID_IMP_R4600: 681 c->cputype = CPU_R4600; 682 __cpu_name[cpu] = "R4600"; 683 set_isa(c, MIPS_CPU_ISA_III); 684 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 685 MIPS_CPU_LLSC; 686 c->tlbsize = 48; 687 break; 688 #if 0 689 case PRID_IMP_R4650: 690 /* 691 * This processor doesn't have an MMU, so it's not 692 * "real easy" to run Linux on it. It is left purely 693 * for documentation. Commented out because it shares 694 * it's c0_prid id number with the TX3900. 695 */ 696 c->cputype = CPU_R4650; 697 __cpu_name[cpu] = "R4650"; 698 set_isa(c, MIPS_CPU_ISA_III); 699 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 700 c->tlbsize = 48; 701 break; 702 #endif 703 case PRID_IMP_TX39: 704 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 705 706 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 707 c->cputype = CPU_TX3927; 708 __cpu_name[cpu] = "TX3927"; 709 c->tlbsize = 64; 710 } else { 711 switch (c->processor_id & PRID_REV_MASK) { 712 case PRID_REV_TX3912: 713 c->cputype = CPU_TX3912; 714 __cpu_name[cpu] = "TX3912"; 715 c->tlbsize = 32; 716 break; 717 case PRID_REV_TX3922: 718 c->cputype = CPU_TX3922; 719 __cpu_name[cpu] = "TX3922"; 720 c->tlbsize = 64; 721 break; 722 } 723 } 724 break; 725 case PRID_IMP_R4700: 726 c->cputype = CPU_R4700; 727 __cpu_name[cpu] = "R4700"; 728 set_isa(c, MIPS_CPU_ISA_III); 729 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 730 MIPS_CPU_LLSC; 731 c->tlbsize = 48; 732 break; 733 case PRID_IMP_TX49: 734 c->cputype = CPU_TX49XX; 735 __cpu_name[cpu] = "R49XX"; 736 set_isa(c, MIPS_CPU_ISA_III); 737 c->options = R4K_OPTS | MIPS_CPU_LLSC; 738 if (!(c->processor_id & 0x08)) 739 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 740 c->tlbsize = 48; 741 break; 742 case PRID_IMP_R5000: 743 c->cputype = CPU_R5000; 744 __cpu_name[cpu] = "R5000"; 745 set_isa(c, MIPS_CPU_ISA_IV); 746 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 747 MIPS_CPU_LLSC; 748 c->tlbsize = 48; 749 break; 750 case PRID_IMP_R5432: 751 c->cputype = CPU_R5432; 752 __cpu_name[cpu] = "R5432"; 753 set_isa(c, MIPS_CPU_ISA_IV); 754 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 755 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 756 c->tlbsize = 48; 757 break; 758 case PRID_IMP_R5500: 759 c->cputype = CPU_R5500; 760 __cpu_name[cpu] = "R5500"; 761 set_isa(c, MIPS_CPU_ISA_IV); 762 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 763 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 764 c->tlbsize = 48; 765 break; 766 case PRID_IMP_NEVADA: 767 c->cputype = CPU_NEVADA; 768 __cpu_name[cpu] = "Nevada"; 769 set_isa(c, MIPS_CPU_ISA_IV); 770 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 771 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 772 c->tlbsize = 48; 773 break; 774 case PRID_IMP_R6000: 775 c->cputype = CPU_R6000; 776 __cpu_name[cpu] = "R6000"; 777 set_isa(c, MIPS_CPU_ISA_II); 778 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 779 MIPS_CPU_LLSC; 780 c->tlbsize = 32; 781 break; 782 case PRID_IMP_R6000A: 783 c->cputype = CPU_R6000A; 784 __cpu_name[cpu] = "R6000A"; 785 set_isa(c, MIPS_CPU_ISA_II); 786 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 787 MIPS_CPU_LLSC; 788 c->tlbsize = 32; 789 break; 790 case PRID_IMP_RM7000: 791 c->cputype = CPU_RM7000; 792 __cpu_name[cpu] = "RM7000"; 793 set_isa(c, MIPS_CPU_ISA_IV); 794 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 795 MIPS_CPU_LLSC; 796 /* 797 * Undocumented RM7000: Bit 29 in the info register of 798 * the RM7000 v2.0 indicates if the TLB has 48 or 64 799 * entries. 800 * 801 * 29 1 => 64 entry JTLB 802 * 0 => 48 entry JTLB 803 */ 804 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 805 break; 806 case PRID_IMP_R8000: 807 c->cputype = CPU_R8000; 808 __cpu_name[cpu] = "RM8000"; 809 set_isa(c, MIPS_CPU_ISA_IV); 810 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 811 MIPS_CPU_FPU | MIPS_CPU_32FPR | 812 MIPS_CPU_LLSC; 813 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 814 break; 815 case PRID_IMP_R10000: 816 c->cputype = CPU_R10000; 817 __cpu_name[cpu] = "R10000"; 818 set_isa(c, MIPS_CPU_ISA_IV); 819 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 820 MIPS_CPU_FPU | MIPS_CPU_32FPR | 821 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 822 MIPS_CPU_LLSC; 823 c->tlbsize = 64; 824 break; 825 case PRID_IMP_R12000: 826 c->cputype = CPU_R12000; 827 __cpu_name[cpu] = "R12000"; 828 set_isa(c, MIPS_CPU_ISA_IV); 829 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 830 MIPS_CPU_FPU | MIPS_CPU_32FPR | 831 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 832 MIPS_CPU_LLSC; 833 c->tlbsize = 64; 834 break; 835 case PRID_IMP_R14000: 836 c->cputype = CPU_R14000; 837 __cpu_name[cpu] = "R14000"; 838 set_isa(c, MIPS_CPU_ISA_IV); 839 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 840 MIPS_CPU_FPU | MIPS_CPU_32FPR | 841 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 842 MIPS_CPU_LLSC; 843 c->tlbsize = 64; 844 break; 845 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 846 switch (c->processor_id & PRID_REV_MASK) { 847 case PRID_REV_LOONGSON2E: 848 c->cputype = CPU_LOONGSON2; 849 __cpu_name[cpu] = "ICT Loongson-2"; 850 set_elf_platform(cpu, "loongson2e"); 851 set_isa(c, MIPS_CPU_ISA_III); 852 break; 853 case PRID_REV_LOONGSON2F: 854 c->cputype = CPU_LOONGSON2; 855 __cpu_name[cpu] = "ICT Loongson-2"; 856 set_elf_platform(cpu, "loongson2f"); 857 set_isa(c, MIPS_CPU_ISA_III); 858 break; 859 case PRID_REV_LOONGSON3A: 860 c->cputype = CPU_LOONGSON3; 861 __cpu_name[cpu] = "ICT Loongson-3"; 862 set_elf_platform(cpu, "loongson3a"); 863 set_isa(c, MIPS_CPU_ISA_M64R1); 864 break; 865 case PRID_REV_LOONGSON3B_R1: 866 case PRID_REV_LOONGSON3B_R2: 867 c->cputype = CPU_LOONGSON3; 868 __cpu_name[cpu] = "ICT Loongson-3"; 869 set_elf_platform(cpu, "loongson3b"); 870 set_isa(c, MIPS_CPU_ISA_M64R1); 871 break; 872 } 873 874 c->options = R4K_OPTS | 875 MIPS_CPU_FPU | MIPS_CPU_LLSC | 876 MIPS_CPU_32FPR; 877 c->tlbsize = 64; 878 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 879 break; 880 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 881 decode_configs(c); 882 883 c->cputype = CPU_LOONGSON1; 884 885 switch (c->processor_id & PRID_REV_MASK) { 886 case PRID_REV_LOONGSON1B: 887 __cpu_name[cpu] = "Loongson 1B"; 888 break; 889 } 890 891 break; 892 } 893 } 894 895 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 896 { 897 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 898 switch (c->processor_id & PRID_IMP_MASK) { 899 case PRID_IMP_4KC: 900 c->cputype = CPU_4KC; 901 c->writecombine = _CACHE_UNCACHED; 902 __cpu_name[cpu] = "MIPS 4Kc"; 903 break; 904 case PRID_IMP_4KEC: 905 case PRID_IMP_4KECR2: 906 c->cputype = CPU_4KEC; 907 c->writecombine = _CACHE_UNCACHED; 908 __cpu_name[cpu] = "MIPS 4KEc"; 909 break; 910 case PRID_IMP_4KSC: 911 case PRID_IMP_4KSD: 912 c->cputype = CPU_4KSC; 913 c->writecombine = _CACHE_UNCACHED; 914 __cpu_name[cpu] = "MIPS 4KSc"; 915 break; 916 case PRID_IMP_5KC: 917 c->cputype = CPU_5KC; 918 c->writecombine = _CACHE_UNCACHED; 919 __cpu_name[cpu] = "MIPS 5Kc"; 920 break; 921 case PRID_IMP_5KE: 922 c->cputype = CPU_5KE; 923 c->writecombine = _CACHE_UNCACHED; 924 __cpu_name[cpu] = "MIPS 5KE"; 925 break; 926 case PRID_IMP_20KC: 927 c->cputype = CPU_20KC; 928 c->writecombine = _CACHE_UNCACHED; 929 __cpu_name[cpu] = "MIPS 20Kc"; 930 break; 931 case PRID_IMP_24K: 932 c->cputype = CPU_24K; 933 c->writecombine = _CACHE_UNCACHED; 934 __cpu_name[cpu] = "MIPS 24Kc"; 935 break; 936 case PRID_IMP_24KE: 937 c->cputype = CPU_24K; 938 c->writecombine = _CACHE_UNCACHED; 939 __cpu_name[cpu] = "MIPS 24KEc"; 940 break; 941 case PRID_IMP_25KF: 942 c->cputype = CPU_25KF; 943 c->writecombine = _CACHE_UNCACHED; 944 __cpu_name[cpu] = "MIPS 25Kc"; 945 break; 946 case PRID_IMP_34K: 947 c->cputype = CPU_34K; 948 c->writecombine = _CACHE_UNCACHED; 949 __cpu_name[cpu] = "MIPS 34Kc"; 950 break; 951 case PRID_IMP_74K: 952 c->cputype = CPU_74K; 953 c->writecombine = _CACHE_UNCACHED; 954 __cpu_name[cpu] = "MIPS 74Kc"; 955 break; 956 case PRID_IMP_M14KC: 957 c->cputype = CPU_M14KC; 958 c->writecombine = _CACHE_UNCACHED; 959 __cpu_name[cpu] = "MIPS M14Kc"; 960 break; 961 case PRID_IMP_M14KEC: 962 c->cputype = CPU_M14KEC; 963 c->writecombine = _CACHE_UNCACHED; 964 __cpu_name[cpu] = "MIPS M14KEc"; 965 break; 966 case PRID_IMP_1004K: 967 c->cputype = CPU_1004K; 968 c->writecombine = _CACHE_UNCACHED; 969 __cpu_name[cpu] = "MIPS 1004Kc"; 970 break; 971 case PRID_IMP_1074K: 972 c->cputype = CPU_1074K; 973 c->writecombine = _CACHE_UNCACHED; 974 __cpu_name[cpu] = "MIPS 1074Kc"; 975 break; 976 case PRID_IMP_INTERAPTIV_UP: 977 c->cputype = CPU_INTERAPTIV; 978 __cpu_name[cpu] = "MIPS interAptiv"; 979 break; 980 case PRID_IMP_INTERAPTIV_MP: 981 c->cputype = CPU_INTERAPTIV; 982 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 983 break; 984 case PRID_IMP_PROAPTIV_UP: 985 c->cputype = CPU_PROAPTIV; 986 __cpu_name[cpu] = "MIPS proAptiv"; 987 break; 988 case PRID_IMP_PROAPTIV_MP: 989 c->cputype = CPU_PROAPTIV; 990 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 991 break; 992 case PRID_IMP_P5600: 993 c->cputype = CPU_P5600; 994 __cpu_name[cpu] = "MIPS P5600"; 995 break; 996 case PRID_IMP_M5150: 997 c->cputype = CPU_M5150; 998 __cpu_name[cpu] = "MIPS M5150"; 999 break; 1000 } 1001 1002 decode_configs(c); 1003 1004 spram_config(); 1005 } 1006 1007 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1008 { 1009 decode_configs(c); 1010 switch (c->processor_id & PRID_IMP_MASK) { 1011 case PRID_IMP_AU1_REV1: 1012 case PRID_IMP_AU1_REV2: 1013 c->cputype = CPU_ALCHEMY; 1014 switch ((c->processor_id >> 24) & 0xff) { 1015 case 0: 1016 __cpu_name[cpu] = "Au1000"; 1017 break; 1018 case 1: 1019 __cpu_name[cpu] = "Au1500"; 1020 break; 1021 case 2: 1022 __cpu_name[cpu] = "Au1100"; 1023 break; 1024 case 3: 1025 __cpu_name[cpu] = "Au1550"; 1026 break; 1027 case 4: 1028 __cpu_name[cpu] = "Au1200"; 1029 if ((c->processor_id & PRID_REV_MASK) == 2) 1030 __cpu_name[cpu] = "Au1250"; 1031 break; 1032 case 5: 1033 __cpu_name[cpu] = "Au1210"; 1034 break; 1035 default: 1036 __cpu_name[cpu] = "Au1xxx"; 1037 break; 1038 } 1039 break; 1040 } 1041 } 1042 1043 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1044 { 1045 decode_configs(c); 1046 1047 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1048 switch (c->processor_id & PRID_IMP_MASK) { 1049 case PRID_IMP_SB1: 1050 c->cputype = CPU_SB1; 1051 __cpu_name[cpu] = "SiByte SB1"; 1052 /* FPU in pass1 is known to have issues. */ 1053 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1054 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1055 break; 1056 case PRID_IMP_SB1A: 1057 c->cputype = CPU_SB1A; 1058 __cpu_name[cpu] = "SiByte SB1A"; 1059 break; 1060 } 1061 } 1062 1063 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1064 { 1065 decode_configs(c); 1066 switch (c->processor_id & PRID_IMP_MASK) { 1067 case PRID_IMP_SR71000: 1068 c->cputype = CPU_SR71000; 1069 __cpu_name[cpu] = "Sandcraft SR71000"; 1070 c->scache.ways = 8; 1071 c->tlbsize = 64; 1072 break; 1073 } 1074 } 1075 1076 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1077 { 1078 decode_configs(c); 1079 switch (c->processor_id & PRID_IMP_MASK) { 1080 case PRID_IMP_PR4450: 1081 c->cputype = CPU_PR4450; 1082 __cpu_name[cpu] = "Philips PR4450"; 1083 set_isa(c, MIPS_CPU_ISA_M32R1); 1084 break; 1085 } 1086 } 1087 1088 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1089 { 1090 decode_configs(c); 1091 switch (c->processor_id & PRID_IMP_MASK) { 1092 case PRID_IMP_BMIPS32_REV4: 1093 case PRID_IMP_BMIPS32_REV8: 1094 c->cputype = CPU_BMIPS32; 1095 __cpu_name[cpu] = "Broadcom BMIPS32"; 1096 set_elf_platform(cpu, "bmips32"); 1097 break; 1098 case PRID_IMP_BMIPS3300: 1099 case PRID_IMP_BMIPS3300_ALT: 1100 case PRID_IMP_BMIPS3300_BUG: 1101 c->cputype = CPU_BMIPS3300; 1102 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1103 set_elf_platform(cpu, "bmips3300"); 1104 break; 1105 case PRID_IMP_BMIPS43XX: { 1106 int rev = c->processor_id & PRID_REV_MASK; 1107 1108 if (rev >= PRID_REV_BMIPS4380_LO && 1109 rev <= PRID_REV_BMIPS4380_HI) { 1110 c->cputype = CPU_BMIPS4380; 1111 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1112 set_elf_platform(cpu, "bmips4380"); 1113 } else { 1114 c->cputype = CPU_BMIPS4350; 1115 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1116 set_elf_platform(cpu, "bmips4350"); 1117 } 1118 break; 1119 } 1120 case PRID_IMP_BMIPS5000: 1121 case PRID_IMP_BMIPS5200: 1122 c->cputype = CPU_BMIPS5000; 1123 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1124 set_elf_platform(cpu, "bmips5000"); 1125 c->options |= MIPS_CPU_ULRI; 1126 break; 1127 } 1128 } 1129 1130 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1131 { 1132 decode_configs(c); 1133 switch (c->processor_id & PRID_IMP_MASK) { 1134 case PRID_IMP_CAVIUM_CN38XX: 1135 case PRID_IMP_CAVIUM_CN31XX: 1136 case PRID_IMP_CAVIUM_CN30XX: 1137 c->cputype = CPU_CAVIUM_OCTEON; 1138 __cpu_name[cpu] = "Cavium Octeon"; 1139 goto platform; 1140 case PRID_IMP_CAVIUM_CN58XX: 1141 case PRID_IMP_CAVIUM_CN56XX: 1142 case PRID_IMP_CAVIUM_CN50XX: 1143 case PRID_IMP_CAVIUM_CN52XX: 1144 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1145 __cpu_name[cpu] = "Cavium Octeon+"; 1146 platform: 1147 set_elf_platform(cpu, "octeon"); 1148 break; 1149 case PRID_IMP_CAVIUM_CN61XX: 1150 case PRID_IMP_CAVIUM_CN63XX: 1151 case PRID_IMP_CAVIUM_CN66XX: 1152 case PRID_IMP_CAVIUM_CN68XX: 1153 case PRID_IMP_CAVIUM_CNF71XX: 1154 c->cputype = CPU_CAVIUM_OCTEON2; 1155 __cpu_name[cpu] = "Cavium Octeon II"; 1156 set_elf_platform(cpu, "octeon2"); 1157 break; 1158 case PRID_IMP_CAVIUM_CN70XX: 1159 case PRID_IMP_CAVIUM_CN78XX: 1160 c->cputype = CPU_CAVIUM_OCTEON3; 1161 __cpu_name[cpu] = "Cavium Octeon III"; 1162 set_elf_platform(cpu, "octeon3"); 1163 break; 1164 default: 1165 printk(KERN_INFO "Unknown Octeon chip!\n"); 1166 c->cputype = CPU_UNKNOWN; 1167 break; 1168 } 1169 } 1170 1171 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1172 { 1173 decode_configs(c); 1174 /* JZRISC does not implement the CP0 counter. */ 1175 c->options &= ~MIPS_CPU_COUNTER; 1176 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1177 switch (c->processor_id & PRID_IMP_MASK) { 1178 case PRID_IMP_JZRISC: 1179 c->cputype = CPU_JZRISC; 1180 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1181 __cpu_name[cpu] = "Ingenic JZRISC"; 1182 break; 1183 default: 1184 panic("Unknown Ingenic Processor ID!"); 1185 break; 1186 } 1187 } 1188 1189 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1190 { 1191 decode_configs(c); 1192 1193 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1194 c->cputype = CPU_ALCHEMY; 1195 __cpu_name[cpu] = "Au1300"; 1196 /* following stuff is not for Alchemy */ 1197 return; 1198 } 1199 1200 c->options = (MIPS_CPU_TLB | 1201 MIPS_CPU_4KEX | 1202 MIPS_CPU_COUNTER | 1203 MIPS_CPU_DIVEC | 1204 MIPS_CPU_WATCH | 1205 MIPS_CPU_EJTAG | 1206 MIPS_CPU_LLSC); 1207 1208 switch (c->processor_id & PRID_IMP_MASK) { 1209 case PRID_IMP_NETLOGIC_XLP2XX: 1210 case PRID_IMP_NETLOGIC_XLP9XX: 1211 case PRID_IMP_NETLOGIC_XLP5XX: 1212 c->cputype = CPU_XLP; 1213 __cpu_name[cpu] = "Broadcom XLPII"; 1214 break; 1215 1216 case PRID_IMP_NETLOGIC_XLP8XX: 1217 case PRID_IMP_NETLOGIC_XLP3XX: 1218 c->cputype = CPU_XLP; 1219 __cpu_name[cpu] = "Netlogic XLP"; 1220 break; 1221 1222 case PRID_IMP_NETLOGIC_XLR732: 1223 case PRID_IMP_NETLOGIC_XLR716: 1224 case PRID_IMP_NETLOGIC_XLR532: 1225 case PRID_IMP_NETLOGIC_XLR308: 1226 case PRID_IMP_NETLOGIC_XLR532C: 1227 case PRID_IMP_NETLOGIC_XLR516C: 1228 case PRID_IMP_NETLOGIC_XLR508C: 1229 case PRID_IMP_NETLOGIC_XLR308C: 1230 c->cputype = CPU_XLR; 1231 __cpu_name[cpu] = "Netlogic XLR"; 1232 break; 1233 1234 case PRID_IMP_NETLOGIC_XLS608: 1235 case PRID_IMP_NETLOGIC_XLS408: 1236 case PRID_IMP_NETLOGIC_XLS404: 1237 case PRID_IMP_NETLOGIC_XLS208: 1238 case PRID_IMP_NETLOGIC_XLS204: 1239 case PRID_IMP_NETLOGIC_XLS108: 1240 case PRID_IMP_NETLOGIC_XLS104: 1241 case PRID_IMP_NETLOGIC_XLS616B: 1242 case PRID_IMP_NETLOGIC_XLS608B: 1243 case PRID_IMP_NETLOGIC_XLS416B: 1244 case PRID_IMP_NETLOGIC_XLS412B: 1245 case PRID_IMP_NETLOGIC_XLS408B: 1246 case PRID_IMP_NETLOGIC_XLS404B: 1247 c->cputype = CPU_XLR; 1248 __cpu_name[cpu] = "Netlogic XLS"; 1249 break; 1250 1251 default: 1252 pr_info("Unknown Netlogic chip id [%02x]!\n", 1253 c->processor_id); 1254 c->cputype = CPU_XLR; 1255 break; 1256 } 1257 1258 if (c->cputype == CPU_XLP) { 1259 set_isa(c, MIPS_CPU_ISA_M64R2); 1260 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1261 /* This will be updated again after all threads are woken up */ 1262 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1263 } else { 1264 set_isa(c, MIPS_CPU_ISA_M64R1); 1265 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1266 } 1267 c->kscratch_mask = 0xf; 1268 } 1269 1270 #ifdef CONFIG_64BIT 1271 /* For use by uaccess.h */ 1272 u64 __ua_limit; 1273 EXPORT_SYMBOL(__ua_limit); 1274 #endif 1275 1276 const char *__cpu_name[NR_CPUS]; 1277 const char *__elf_platform; 1278 1279 void cpu_probe(void) 1280 { 1281 struct cpuinfo_mips *c = ¤t_cpu_data; 1282 unsigned int cpu = smp_processor_id(); 1283 1284 c->processor_id = PRID_IMP_UNKNOWN; 1285 c->fpu_id = FPIR_IMP_NONE; 1286 c->cputype = CPU_UNKNOWN; 1287 c->writecombine = _CACHE_UNCACHED; 1288 1289 c->processor_id = read_c0_prid(); 1290 switch (c->processor_id & PRID_COMP_MASK) { 1291 case PRID_COMP_LEGACY: 1292 cpu_probe_legacy(c, cpu); 1293 break; 1294 case PRID_COMP_MIPS: 1295 cpu_probe_mips(c, cpu); 1296 break; 1297 case PRID_COMP_ALCHEMY: 1298 cpu_probe_alchemy(c, cpu); 1299 break; 1300 case PRID_COMP_SIBYTE: 1301 cpu_probe_sibyte(c, cpu); 1302 break; 1303 case PRID_COMP_BROADCOM: 1304 cpu_probe_broadcom(c, cpu); 1305 break; 1306 case PRID_COMP_SANDCRAFT: 1307 cpu_probe_sandcraft(c, cpu); 1308 break; 1309 case PRID_COMP_NXP: 1310 cpu_probe_nxp(c, cpu); 1311 break; 1312 case PRID_COMP_CAVIUM: 1313 cpu_probe_cavium(c, cpu); 1314 break; 1315 case PRID_COMP_INGENIC: 1316 cpu_probe_ingenic(c, cpu); 1317 break; 1318 case PRID_COMP_NETLOGIC: 1319 cpu_probe_netlogic(c, cpu); 1320 break; 1321 } 1322 1323 BUG_ON(!__cpu_name[cpu]); 1324 BUG_ON(c->cputype == CPU_UNKNOWN); 1325 1326 /* 1327 * Platform code can force the cpu type to optimize code 1328 * generation. In that case be sure the cpu type is correctly 1329 * manually setup otherwise it could trigger some nasty bugs. 1330 */ 1331 BUG_ON(current_cpu_type() != c->cputype); 1332 1333 if (mips_fpu_disabled) 1334 c->options &= ~MIPS_CPU_FPU; 1335 1336 if (mips_dsp_disabled) 1337 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1338 1339 if (mips_htw_disabled) { 1340 c->options &= ~MIPS_CPU_HTW; 1341 write_c0_pwctl(read_c0_pwctl() & 1342 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1343 } 1344 1345 if (c->options & MIPS_CPU_FPU) { 1346 c->fpu_id = cpu_get_fpu_id(); 1347 1348 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1349 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1350 if (c->fpu_id & MIPS_FPIR_3D) 1351 c->ases |= MIPS_ASE_MIPS3D; 1352 if (c->fpu_id & MIPS_FPIR_FREP) 1353 c->options |= MIPS_CPU_FRE; 1354 } 1355 } 1356 1357 if (cpu_has_mips_r2) { 1358 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1359 /* R2 has Performance Counter Interrupt indicator */ 1360 c->options |= MIPS_CPU_PCI; 1361 } 1362 else 1363 c->srsets = 1; 1364 1365 if (cpu_has_msa) { 1366 c->msa_id = cpu_get_msa_id(); 1367 WARN(c->msa_id & MSA_IR_WRPF, 1368 "Vector register partitioning unimplemented!"); 1369 } 1370 1371 cpu_probe_vmbits(c); 1372 1373 #ifdef CONFIG_64BIT 1374 if (cpu == 0) 1375 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1376 #endif 1377 } 1378 1379 void cpu_report(void) 1380 { 1381 struct cpuinfo_mips *c = ¤t_cpu_data; 1382 1383 pr_info("CPU%d revision is: %08x (%s)\n", 1384 smp_processor_id(), c->processor_id, cpu_name_string()); 1385 if (c->options & MIPS_CPU_FPU) 1386 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1387 if (cpu_has_msa) 1388 pr_info("MSA revision is: %08x\n", c->msa_id); 1389 } 1390