1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <asm/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 38 /* 39 * Get the FPU Implementation/Revision. 40 */ 41 static inline unsigned long cpu_get_fpu_id(void) 42 { 43 unsigned long tmp, fpu_id; 44 45 tmp = read_c0_status(); 46 __enable_fpu(FPU_AS_IS); 47 fpu_id = read_32bit_cp1_register(CP1_REVISION); 48 write_c0_status(tmp); 49 return fpu_id; 50 } 51 52 /* 53 * Check if the CPU has an external FPU. 54 */ 55 static inline int __cpu_has_fpu(void) 56 { 57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 58 } 59 60 static inline unsigned long cpu_get_msa_id(void) 61 { 62 unsigned long status, msa_id; 63 64 status = read_c0_status(); 65 __enable_fpu(FPU_64BIT); 66 enable_msa(); 67 msa_id = read_msa_ir(); 68 disable_msa(); 69 write_c0_status(status); 70 return msa_id; 71 } 72 73 /* 74 * Determine the FCSR mask for FPU hardware. 75 */ 76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 77 { 78 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 79 80 fcsr = c->fpu_csr31; 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 82 83 sr = read_c0_status(); 84 __enable_fpu(FPU_AS_IS); 85 86 fcsr0 = fcsr & mask; 87 write_32bit_cp1_register(CP1_STATUS, fcsr0); 88 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 89 90 fcsr1 = fcsr | ~mask; 91 write_32bit_cp1_register(CP1_STATUS, fcsr1); 92 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 93 94 write_32bit_cp1_register(CP1_STATUS, fcsr); 95 96 write_c0_status(sr); 97 98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 99 } 100 101 /* 102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 103 * supported by FPU hardware. 104 */ 105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 106 { 107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 110 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 111 112 sr = read_c0_status(); 113 __enable_fpu(FPU_AS_IS); 114 115 fir = read_32bit_cp1_register(CP1_REVISION); 116 if (fir & MIPS_FPIR_HAS2008) { 117 fcsr = read_32bit_cp1_register(CP1_STATUS); 118 119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 120 write_32bit_cp1_register(CP1_STATUS, fcsr0); 121 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 122 123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 124 write_32bit_cp1_register(CP1_STATUS, fcsr1); 125 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 126 127 write_32bit_cp1_register(CP1_STATUS, fcsr); 128 129 if (!(fcsr0 & FPU_CSR_NAN2008)) 130 c->options |= MIPS_CPU_NAN_LEGACY; 131 if (fcsr1 & FPU_CSR_NAN2008) 132 c->options |= MIPS_CPU_NAN_2008; 133 134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 135 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 136 else 137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 138 139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 140 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 141 else 142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 143 } else { 144 c->options |= MIPS_CPU_NAN_LEGACY; 145 } 146 147 write_c0_status(sr); 148 } else { 149 c->options |= MIPS_CPU_NAN_LEGACY; 150 } 151 } 152 153 /* 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 155 * ABS.fmt/NEG.fmt execution mode. 156 */ 157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 158 159 /* 160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 161 * to support by the FPU emulator according to the IEEE 754 conformance 162 * mode selected. Note that "relaxed" straps the emulator so that it 163 * allows 2008-NaN binaries even for legacy processors. 164 */ 165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 166 { 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 171 switch (ieee754) { 172 case STRICT: 173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 177 } else { 178 c->options |= MIPS_CPU_NAN_LEGACY; 179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 180 } 181 break; 182 case LEGACY: 183 c->options |= MIPS_CPU_NAN_LEGACY; 184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 185 break; 186 case STD2008: 187 c->options |= MIPS_CPU_NAN_2008; 188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 break; 191 case RELAXED: 192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 193 break; 194 } 195 } 196 197 /* 198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 199 * according to the "ieee754=" parameter. 200 */ 201 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 202 { 203 switch (ieee754) { 204 case STRICT: 205 mips_use_nan_legacy = !!cpu_has_nan_legacy; 206 mips_use_nan_2008 = !!cpu_has_nan_2008; 207 break; 208 case LEGACY: 209 mips_use_nan_legacy = !!cpu_has_nan_legacy; 210 mips_use_nan_2008 = !cpu_has_nan_legacy; 211 break; 212 case STD2008: 213 mips_use_nan_legacy = !cpu_has_nan_2008; 214 mips_use_nan_2008 = !!cpu_has_nan_2008; 215 break; 216 case RELAXED: 217 mips_use_nan_legacy = true; 218 mips_use_nan_2008 = true; 219 break; 220 } 221 } 222 223 /* 224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 225 * settings: 226 * 227 * strict: accept binaries that request a NaN encoding supported by the FPU 228 * legacy: only accept legacy-NaN binaries 229 * 2008: only accept 2008-NaN binaries 230 * relaxed: accept any binaries regardless of whether supported by the FPU 231 */ 232 static int __init ieee754_setup(char *s) 233 { 234 if (!s) 235 return -1; 236 else if (!strcmp(s, "strict")) 237 ieee754 = STRICT; 238 else if (!strcmp(s, "legacy")) 239 ieee754 = LEGACY; 240 else if (!strcmp(s, "2008")) 241 ieee754 = STD2008; 242 else if (!strcmp(s, "relaxed")) 243 ieee754 = RELAXED; 244 else 245 return -1; 246 247 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 248 cpu_set_nofpu_2008(&boot_cpu_data); 249 cpu_set_nan_2008(&boot_cpu_data); 250 251 return 0; 252 } 253 254 early_param("ieee754", ieee754_setup); 255 256 /* 257 * Set the FIR feature flags for the FPU emulator. 258 */ 259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 260 { 261 u32 value; 262 263 value = 0; 264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 267 value |= MIPS_FPIR_D | MIPS_FPIR_S; 268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 271 if (c->options & MIPS_CPU_NAN_2008) 272 value |= MIPS_FPIR_HAS2008; 273 c->fpu_id = value; 274 } 275 276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 277 static unsigned int mips_nofpu_msk31; 278 279 /* 280 * Set options for FPU hardware. 281 */ 282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 283 { 284 c->fpu_id = cpu_get_fpu_id(); 285 mips_nofpu_msk31 = c->fpu_msk31; 286 287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 290 if (c->fpu_id & MIPS_FPIR_3D) 291 c->ases |= MIPS_ASE_MIPS3D; 292 if (c->fpu_id & MIPS_FPIR_FREP) 293 c->options |= MIPS_CPU_FRE; 294 } 295 296 cpu_set_fpu_fcsr_mask(c); 297 cpu_set_fpu_2008(c); 298 cpu_set_nan_2008(c); 299 } 300 301 /* 302 * Set options for the FPU emulator. 303 */ 304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 305 { 306 c->options &= ~MIPS_CPU_FPU; 307 c->fpu_msk31 = mips_nofpu_msk31; 308 309 cpu_set_nofpu_2008(c); 310 cpu_set_nan_2008(c); 311 cpu_set_nofpu_id(c); 312 } 313 314 static int mips_fpu_disabled; 315 316 static int __init fpu_disable(char *s) 317 { 318 cpu_set_nofpu_opts(&boot_cpu_data); 319 mips_fpu_disabled = 1; 320 321 return 1; 322 } 323 324 __setup("nofpu", fpu_disable); 325 326 int mips_dsp_disabled; 327 328 static int __init dsp_disable(char *s) 329 { 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 331 mips_dsp_disabled = 1; 332 333 return 1; 334 } 335 336 __setup("nodsp", dsp_disable); 337 338 static int mips_htw_disabled; 339 340 static int __init htw_disable(char *s) 341 { 342 mips_htw_disabled = 1; 343 cpu_data[0].options &= ~MIPS_CPU_HTW; 344 write_c0_pwctl(read_c0_pwctl() & 345 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 346 347 return 1; 348 } 349 350 __setup("nohtw", htw_disable); 351 352 static int mips_ftlb_disabled; 353 static int mips_has_ftlb_configured; 354 355 enum ftlb_flags { 356 FTLB_EN = 1 << 0, 357 FTLB_SET_PROB = 1 << 1, 358 }; 359 360 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 361 362 static int __init ftlb_disable(char *s) 363 { 364 unsigned int config4, mmuextdef; 365 366 /* 367 * If the core hasn't done any FTLB configuration, there is nothing 368 * for us to do here. 369 */ 370 if (!mips_has_ftlb_configured) 371 return 1; 372 373 /* Disable it in the boot cpu */ 374 if (set_ftlb_enable(&cpu_data[0], 0)) { 375 pr_warn("Can't turn FTLB off\n"); 376 return 1; 377 } 378 379 config4 = read_c0_config4(); 380 381 /* Check that FTLB has been disabled */ 382 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 383 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 384 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 385 /* This should never happen */ 386 pr_warn("FTLB could not be disabled!\n"); 387 return 1; 388 } 389 390 mips_ftlb_disabled = 1; 391 mips_has_ftlb_configured = 0; 392 393 /* 394 * noftlb is mainly used for debug purposes so print 395 * an informative message instead of using pr_debug() 396 */ 397 pr_info("FTLB has been disabled\n"); 398 399 /* 400 * Some of these bits are duplicated in the decode_config4. 401 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 402 * once FTLB has been disabled so undo what decode_config4 did. 403 */ 404 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 405 cpu_data[0].tlbsizeftlbsets; 406 cpu_data[0].tlbsizeftlbsets = 0; 407 cpu_data[0].tlbsizeftlbways = 0; 408 409 return 1; 410 } 411 412 __setup("noftlb", ftlb_disable); 413 414 415 static inline void check_errata(void) 416 { 417 struct cpuinfo_mips *c = ¤t_cpu_data; 418 419 switch (current_cpu_type()) { 420 case CPU_34K: 421 /* 422 * Erratum "RPS May Cause Incorrect Instruction Execution" 423 * This code only handles VPE0, any SMP/RTOS code 424 * making use of VPE1 will be responsable for that VPE. 425 */ 426 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 427 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 428 break; 429 default: 430 break; 431 } 432 } 433 434 void __init check_bugs32(void) 435 { 436 check_errata(); 437 } 438 439 /* 440 * Probe whether cpu has config register by trying to play with 441 * alternate cache bit and see whether it matters. 442 * It's used by cpu_probe to distinguish between R3000A and R3081. 443 */ 444 static inline int cpu_has_confreg(void) 445 { 446 #ifdef CONFIG_CPU_R3000 447 extern unsigned long r3k_cache_size(unsigned long); 448 unsigned long size1, size2; 449 unsigned long cfg = read_c0_conf(); 450 451 size1 = r3k_cache_size(ST0_ISC); 452 write_c0_conf(cfg ^ R30XX_CONF_AC); 453 size2 = r3k_cache_size(ST0_ISC); 454 write_c0_conf(cfg); 455 return size1 != size2; 456 #else 457 return 0; 458 #endif 459 } 460 461 static inline void set_elf_platform(int cpu, const char *plat) 462 { 463 if (cpu == 0) 464 __elf_platform = plat; 465 } 466 467 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 468 { 469 #ifdef __NEED_VMBITS_PROBE 470 write_c0_entryhi(0x3fffffffffffe000ULL); 471 back_to_back_c0_hazard(); 472 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 473 #endif 474 } 475 476 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 477 { 478 switch (isa) { 479 case MIPS_CPU_ISA_M64R2: 480 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 481 case MIPS_CPU_ISA_M64R1: 482 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 483 case MIPS_CPU_ISA_V: 484 c->isa_level |= MIPS_CPU_ISA_V; 485 case MIPS_CPU_ISA_IV: 486 c->isa_level |= MIPS_CPU_ISA_IV; 487 case MIPS_CPU_ISA_III: 488 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 489 break; 490 491 /* R6 incompatible with everything else */ 492 case MIPS_CPU_ISA_M64R6: 493 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 494 case MIPS_CPU_ISA_M32R6: 495 c->isa_level |= MIPS_CPU_ISA_M32R6; 496 /* Break here so we don't add incompatible ISAs */ 497 break; 498 case MIPS_CPU_ISA_M32R2: 499 c->isa_level |= MIPS_CPU_ISA_M32R2; 500 case MIPS_CPU_ISA_M32R1: 501 c->isa_level |= MIPS_CPU_ISA_M32R1; 502 case MIPS_CPU_ISA_II: 503 c->isa_level |= MIPS_CPU_ISA_II; 504 break; 505 } 506 } 507 508 static char unknown_isa[] = KERN_ERR \ 509 "Unsupported ISA type, c0.config0: %d."; 510 511 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 512 { 513 514 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 515 516 /* 517 * 0 = All TLBWR instructions go to FTLB 518 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 519 * FTLB and 1 goes to the VTLB. 520 * 2 = 7:1: As above with 7:1 ratio. 521 * 3 = 3:1: As above with 3:1 ratio. 522 * 523 * Use the linear midpoint as the probability threshold. 524 */ 525 if (probability >= 12) 526 return 1; 527 else if (probability >= 6) 528 return 2; 529 else 530 /* 531 * So FTLB is less than 4 times bigger than VTLB. 532 * A 3:1 ratio can still be useful though. 533 */ 534 return 3; 535 } 536 537 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 538 { 539 unsigned int config; 540 541 /* It's implementation dependent how the FTLB can be enabled */ 542 switch (c->cputype) { 543 case CPU_PROAPTIV: 544 case CPU_P5600: 545 case CPU_P6600: 546 /* proAptiv & related cores use Config6 to enable the FTLB */ 547 config = read_c0_config6(); 548 549 if (flags & FTLB_EN) 550 config |= MIPS_CONF6_FTLBEN; 551 else 552 config &= ~MIPS_CONF6_FTLBEN; 553 554 if (flags & FTLB_SET_PROB) { 555 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 556 config |= calculate_ftlb_probability(c) 557 << MIPS_CONF6_FTLBP_SHIFT; 558 } 559 560 write_c0_config6(config); 561 back_to_back_c0_hazard(); 562 break; 563 case CPU_I6400: 564 /* There's no way to disable the FTLB */ 565 if (!(flags & FTLB_EN)) 566 return 1; 567 return 0; 568 case CPU_LOONGSON3: 569 /* Flush ITLB, DTLB, VTLB and FTLB */ 570 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 571 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 572 /* Loongson-3 cores use Config6 to enable the FTLB */ 573 config = read_c0_config6(); 574 if (flags & FTLB_EN) 575 /* Enable FTLB */ 576 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); 577 else 578 /* Disable FTLB */ 579 write_c0_config6(config | MIPS_CONF6_FTLBDIS); 580 break; 581 default: 582 return 1; 583 } 584 585 return 0; 586 } 587 588 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 589 { 590 unsigned int config0; 591 int isa, mt; 592 593 config0 = read_c0_config(); 594 595 /* 596 * Look for Standard TLB or Dual VTLB and FTLB 597 */ 598 mt = config0 & MIPS_CONF_MT; 599 if (mt == MIPS_CONF_MT_TLB) 600 c->options |= MIPS_CPU_TLB; 601 else if (mt == MIPS_CONF_MT_FTLB) 602 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 603 604 isa = (config0 & MIPS_CONF_AT) >> 13; 605 switch (isa) { 606 case 0: 607 switch ((config0 & MIPS_CONF_AR) >> 10) { 608 case 0: 609 set_isa(c, MIPS_CPU_ISA_M32R1); 610 break; 611 case 1: 612 set_isa(c, MIPS_CPU_ISA_M32R2); 613 break; 614 case 2: 615 set_isa(c, MIPS_CPU_ISA_M32R6); 616 break; 617 default: 618 goto unknown; 619 } 620 break; 621 case 2: 622 switch ((config0 & MIPS_CONF_AR) >> 10) { 623 case 0: 624 set_isa(c, MIPS_CPU_ISA_M64R1); 625 break; 626 case 1: 627 set_isa(c, MIPS_CPU_ISA_M64R2); 628 break; 629 case 2: 630 set_isa(c, MIPS_CPU_ISA_M64R6); 631 break; 632 default: 633 goto unknown; 634 } 635 break; 636 default: 637 goto unknown; 638 } 639 640 return config0 & MIPS_CONF_M; 641 642 unknown: 643 panic(unknown_isa, config0); 644 } 645 646 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 647 { 648 unsigned int config1; 649 650 config1 = read_c0_config1(); 651 652 if (config1 & MIPS_CONF1_MD) 653 c->ases |= MIPS_ASE_MDMX; 654 if (config1 & MIPS_CONF1_PC) 655 c->options |= MIPS_CPU_PERF; 656 if (config1 & MIPS_CONF1_WR) 657 c->options |= MIPS_CPU_WATCH; 658 if (config1 & MIPS_CONF1_CA) 659 c->ases |= MIPS_ASE_MIPS16; 660 if (config1 & MIPS_CONF1_EP) 661 c->options |= MIPS_CPU_EJTAG; 662 if (config1 & MIPS_CONF1_FP) { 663 c->options |= MIPS_CPU_FPU; 664 c->options |= MIPS_CPU_32FPR; 665 } 666 if (cpu_has_tlb) { 667 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 668 c->tlbsizevtlb = c->tlbsize; 669 c->tlbsizeftlbsets = 0; 670 } 671 672 return config1 & MIPS_CONF_M; 673 } 674 675 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 676 { 677 unsigned int config2; 678 679 config2 = read_c0_config2(); 680 681 if (config2 & MIPS_CONF2_SL) 682 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 683 684 return config2 & MIPS_CONF_M; 685 } 686 687 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 688 { 689 unsigned int config3; 690 691 config3 = read_c0_config3(); 692 693 if (config3 & MIPS_CONF3_SM) { 694 c->ases |= MIPS_ASE_SMARTMIPS; 695 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 696 } 697 if (config3 & MIPS_CONF3_RXI) 698 c->options |= MIPS_CPU_RIXI; 699 if (config3 & MIPS_CONF3_CTXTC) 700 c->options |= MIPS_CPU_CTXTC; 701 if (config3 & MIPS_CONF3_DSP) 702 c->ases |= MIPS_ASE_DSP; 703 if (config3 & MIPS_CONF3_DSP2P) { 704 c->ases |= MIPS_ASE_DSP2P; 705 if (cpu_has_mips_r6) 706 c->ases |= MIPS_ASE_DSP3; 707 } 708 if (config3 & MIPS_CONF3_VINT) 709 c->options |= MIPS_CPU_VINT; 710 if (config3 & MIPS_CONF3_VEIC) 711 c->options |= MIPS_CPU_VEIC; 712 if (config3 & MIPS_CONF3_LPA) 713 c->options |= MIPS_CPU_LPA; 714 if (config3 & MIPS_CONF3_MT) 715 c->ases |= MIPS_ASE_MIPSMT; 716 if (config3 & MIPS_CONF3_ULRI) 717 c->options |= MIPS_CPU_ULRI; 718 if (config3 & MIPS_CONF3_ISA) 719 c->options |= MIPS_CPU_MICROMIPS; 720 if (config3 & MIPS_CONF3_VZ) 721 c->ases |= MIPS_ASE_VZ; 722 if (config3 & MIPS_CONF3_SC) 723 c->options |= MIPS_CPU_SEGMENTS; 724 if (config3 & MIPS_CONF3_BI) 725 c->options |= MIPS_CPU_BADINSTR; 726 if (config3 & MIPS_CONF3_BP) 727 c->options |= MIPS_CPU_BADINSTRP; 728 if (config3 & MIPS_CONF3_MSA) 729 c->ases |= MIPS_ASE_MSA; 730 if (config3 & MIPS_CONF3_PW) { 731 c->htw_seq = 0; 732 c->options |= MIPS_CPU_HTW; 733 } 734 if (config3 & MIPS_CONF3_CDMM) 735 c->options |= MIPS_CPU_CDMM; 736 if (config3 & MIPS_CONF3_SP) 737 c->options |= MIPS_CPU_SP; 738 739 return config3 & MIPS_CONF_M; 740 } 741 742 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 743 { 744 unsigned int config4; 745 unsigned int newcf4; 746 unsigned int mmuextdef; 747 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 748 unsigned long asid_mask; 749 750 config4 = read_c0_config4(); 751 752 if (cpu_has_tlb) { 753 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 754 c->options |= MIPS_CPU_TLBINV; 755 756 /* 757 * R6 has dropped the MMUExtDef field from config4. 758 * On R6 the fields always describe the FTLB, and only if it is 759 * present according to Config.MT. 760 */ 761 if (!cpu_has_mips_r6) 762 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 763 else if (cpu_has_ftlb) 764 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 765 else 766 mmuextdef = 0; 767 768 switch (mmuextdef) { 769 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 770 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 771 c->tlbsizevtlb = c->tlbsize; 772 break; 773 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 774 c->tlbsizevtlb += 775 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 776 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 777 c->tlbsize = c->tlbsizevtlb; 778 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 779 /* fall through */ 780 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 781 if (mips_ftlb_disabled) 782 break; 783 newcf4 = (config4 & ~ftlb_page) | 784 (page_size_ftlb(mmuextdef) << 785 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 786 write_c0_config4(newcf4); 787 back_to_back_c0_hazard(); 788 config4 = read_c0_config4(); 789 if (config4 != newcf4) { 790 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 791 PAGE_SIZE, config4); 792 /* Switch FTLB off */ 793 set_ftlb_enable(c, 0); 794 mips_ftlb_disabled = 1; 795 break; 796 } 797 c->tlbsizeftlbsets = 1 << 798 ((config4 & MIPS_CONF4_FTLBSETS) >> 799 MIPS_CONF4_FTLBSETS_SHIFT); 800 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 801 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 802 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 803 mips_has_ftlb_configured = 1; 804 break; 805 } 806 } 807 808 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 809 >> MIPS_CONF4_KSCREXIST_SHIFT; 810 811 asid_mask = MIPS_ENTRYHI_ASID; 812 if (config4 & MIPS_CONF4_AE) 813 asid_mask |= MIPS_ENTRYHI_ASIDX; 814 set_cpu_asid_mask(c, asid_mask); 815 816 /* 817 * Warn if the computed ASID mask doesn't match the mask the kernel 818 * is built for. This may indicate either a serious problem or an 819 * easy optimisation opportunity, but either way should be addressed. 820 */ 821 WARN_ON(asid_mask != cpu_asid_mask(c)); 822 823 return config4 & MIPS_CONF_M; 824 } 825 826 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 827 { 828 unsigned int config5; 829 830 config5 = read_c0_config5(); 831 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 832 write_c0_config5(config5); 833 834 if (config5 & MIPS_CONF5_EVA) 835 c->options |= MIPS_CPU_EVA; 836 if (config5 & MIPS_CONF5_MRP) 837 c->options |= MIPS_CPU_MAAR; 838 if (config5 & MIPS_CONF5_LLB) 839 c->options |= MIPS_CPU_RW_LLB; 840 if (config5 & MIPS_CONF5_MVH) 841 c->options |= MIPS_CPU_MVH; 842 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 843 c->options |= MIPS_CPU_VP; 844 845 return config5 & MIPS_CONF_M; 846 } 847 848 static void decode_configs(struct cpuinfo_mips *c) 849 { 850 int ok; 851 852 /* MIPS32 or MIPS64 compliant CPU. */ 853 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 854 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 855 856 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 857 858 /* Enable FTLB if present and not disabled */ 859 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 860 861 ok = decode_config0(c); /* Read Config registers. */ 862 BUG_ON(!ok); /* Arch spec violation! */ 863 if (ok) 864 ok = decode_config1(c); 865 if (ok) 866 ok = decode_config2(c); 867 if (ok) 868 ok = decode_config3(c); 869 if (ok) 870 ok = decode_config4(c); 871 if (ok) 872 ok = decode_config5(c); 873 874 /* Probe the EBase.WG bit */ 875 if (cpu_has_mips_r2_r6) { 876 u64 ebase; 877 unsigned int status; 878 879 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 880 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 881 : (s32)read_c0_ebase(); 882 if (ebase & MIPS_EBASE_WG) { 883 /* WG bit already set, we can avoid the clumsy probe */ 884 c->options |= MIPS_CPU_EBASE_WG; 885 } else { 886 /* Its UNDEFINED to change EBase while BEV=0 */ 887 status = read_c0_status(); 888 write_c0_status(status | ST0_BEV); 889 irq_enable_hazard(); 890 /* 891 * On pre-r6 cores, this may well clobber the upper bits 892 * of EBase. This is hard to avoid without potentially 893 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 894 */ 895 if (cpu_has_mips64r6) 896 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 897 else 898 write_c0_ebase(ebase | MIPS_EBASE_WG); 899 back_to_back_c0_hazard(); 900 /* Restore BEV */ 901 write_c0_status(status); 902 if (read_c0_ebase() & MIPS_EBASE_WG) { 903 c->options |= MIPS_CPU_EBASE_WG; 904 write_c0_ebase(ebase); 905 } 906 } 907 } 908 909 /* configure the FTLB write probability */ 910 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 911 912 mips_probe_watch_registers(c); 913 914 #ifndef CONFIG_MIPS_CPS 915 if (cpu_has_mips_r2_r6) { 916 c->core = get_ebase_cpunum(); 917 if (cpu_has_mipsmt) 918 c->core >>= fls(core_nvpes()) - 1; 919 } 920 #endif 921 } 922 923 /* 924 * Probe for certain guest capabilities by writing config bits and reading back. 925 * Finally write back the original value. 926 */ 927 #define probe_gc0_config(name, maxconf, bits) \ 928 do { \ 929 unsigned int tmp; \ 930 tmp = read_gc0_##name(); \ 931 write_gc0_##name(tmp | (bits)); \ 932 back_to_back_c0_hazard(); \ 933 maxconf = read_gc0_##name(); \ 934 write_gc0_##name(tmp); \ 935 } while (0) 936 937 /* 938 * Probe for dynamic guest capabilities by changing certain config bits and 939 * reading back to see if they change. Finally write back the original value. 940 */ 941 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 942 do { \ 943 maxconf = read_gc0_##name(); \ 944 write_gc0_##name(maxconf ^ (bits)); \ 945 back_to_back_c0_hazard(); \ 946 dynconf = maxconf ^ read_gc0_##name(); \ 947 write_gc0_##name(maxconf); \ 948 maxconf |= dynconf; \ 949 } while (0) 950 951 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 952 { 953 unsigned int config0; 954 955 probe_gc0_config(config, config0, MIPS_CONF_M); 956 957 if (config0 & MIPS_CONF_M) 958 c->guest.conf |= BIT(1); 959 return config0 & MIPS_CONF_M; 960 } 961 962 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 963 { 964 unsigned int config1, config1_dyn; 965 966 probe_gc0_config_dyn(config1, config1, config1_dyn, 967 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 968 MIPS_CONF1_FP); 969 970 if (config1 & MIPS_CONF1_FP) 971 c->guest.options |= MIPS_CPU_FPU; 972 if (config1_dyn & MIPS_CONF1_FP) 973 c->guest.options_dyn |= MIPS_CPU_FPU; 974 975 if (config1 & MIPS_CONF1_WR) 976 c->guest.options |= MIPS_CPU_WATCH; 977 if (config1_dyn & MIPS_CONF1_WR) 978 c->guest.options_dyn |= MIPS_CPU_WATCH; 979 980 if (config1 & MIPS_CONF1_PC) 981 c->guest.options |= MIPS_CPU_PERF; 982 if (config1_dyn & MIPS_CONF1_PC) 983 c->guest.options_dyn |= MIPS_CPU_PERF; 984 985 if (config1 & MIPS_CONF_M) 986 c->guest.conf |= BIT(2); 987 return config1 & MIPS_CONF_M; 988 } 989 990 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 991 { 992 unsigned int config2; 993 994 probe_gc0_config(config2, config2, MIPS_CONF_M); 995 996 if (config2 & MIPS_CONF_M) 997 c->guest.conf |= BIT(3); 998 return config2 & MIPS_CONF_M; 999 } 1000 1001 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 1002 { 1003 unsigned int config3, config3_dyn; 1004 1005 probe_gc0_config_dyn(config3, config3, config3_dyn, 1006 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC); 1007 1008 if (config3 & MIPS_CONF3_CTXTC) 1009 c->guest.options |= MIPS_CPU_CTXTC; 1010 if (config3_dyn & MIPS_CONF3_CTXTC) 1011 c->guest.options_dyn |= MIPS_CPU_CTXTC; 1012 1013 if (config3 & MIPS_CONF3_PW) 1014 c->guest.options |= MIPS_CPU_HTW; 1015 1016 if (config3 & MIPS_CONF3_SC) 1017 c->guest.options |= MIPS_CPU_SEGMENTS; 1018 1019 if (config3 & MIPS_CONF3_BI) 1020 c->guest.options |= MIPS_CPU_BADINSTR; 1021 if (config3 & MIPS_CONF3_BP) 1022 c->guest.options |= MIPS_CPU_BADINSTRP; 1023 1024 if (config3 & MIPS_CONF3_MSA) 1025 c->guest.ases |= MIPS_ASE_MSA; 1026 if (config3_dyn & MIPS_CONF3_MSA) 1027 c->guest.ases_dyn |= MIPS_ASE_MSA; 1028 1029 if (config3 & MIPS_CONF_M) 1030 c->guest.conf |= BIT(4); 1031 return config3 & MIPS_CONF_M; 1032 } 1033 1034 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 1035 { 1036 unsigned int config4; 1037 1038 probe_gc0_config(config4, config4, 1039 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 1040 1041 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 1042 >> MIPS_CONF4_KSCREXIST_SHIFT; 1043 1044 if (config4 & MIPS_CONF_M) 1045 c->guest.conf |= BIT(5); 1046 return config4 & MIPS_CONF_M; 1047 } 1048 1049 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 1050 { 1051 unsigned int config5, config5_dyn; 1052 1053 probe_gc0_config_dyn(config5, config5, config5_dyn, 1054 MIPS_CONF_M | MIPS_CONF5_MRP); 1055 1056 if (config5 & MIPS_CONF5_MRP) 1057 c->guest.options |= MIPS_CPU_MAAR; 1058 if (config5_dyn & MIPS_CONF5_MRP) 1059 c->guest.options_dyn |= MIPS_CPU_MAAR; 1060 1061 if (config5 & MIPS_CONF5_LLB) 1062 c->guest.options |= MIPS_CPU_RW_LLB; 1063 1064 if (config5 & MIPS_CONF_M) 1065 c->guest.conf |= BIT(6); 1066 return config5 & MIPS_CONF_M; 1067 } 1068 1069 static inline void decode_guest_configs(struct cpuinfo_mips *c) 1070 { 1071 unsigned int ok; 1072 1073 ok = decode_guest_config0(c); 1074 if (ok) 1075 ok = decode_guest_config1(c); 1076 if (ok) 1077 ok = decode_guest_config2(c); 1078 if (ok) 1079 ok = decode_guest_config3(c); 1080 if (ok) 1081 ok = decode_guest_config4(c); 1082 if (ok) 1083 decode_guest_config5(c); 1084 } 1085 1086 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 1087 { 1088 unsigned int guestctl0, temp; 1089 1090 guestctl0 = read_c0_guestctl0(); 1091 1092 if (guestctl0 & MIPS_GCTL0_G0E) 1093 c->options |= MIPS_CPU_GUESTCTL0EXT; 1094 if (guestctl0 & MIPS_GCTL0_G1) 1095 c->options |= MIPS_CPU_GUESTCTL1; 1096 if (guestctl0 & MIPS_GCTL0_G2) 1097 c->options |= MIPS_CPU_GUESTCTL2; 1098 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 1099 c->options |= MIPS_CPU_GUESTID; 1100 1101 /* 1102 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 1103 * first, otherwise all data accesses will be fully virtualised 1104 * as if they were performed by guest mode. 1105 */ 1106 write_c0_guestctl1(0); 1107 tlbw_use_hazard(); 1108 1109 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 1110 back_to_back_c0_hazard(); 1111 temp = read_c0_guestctl0(); 1112 1113 if (temp & MIPS_GCTL0_DRG) { 1114 write_c0_guestctl0(guestctl0); 1115 c->options |= MIPS_CPU_DRG; 1116 } 1117 } 1118 } 1119 1120 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1121 { 1122 if (cpu_has_guestid) { 1123 /* determine the number of bits of GuestID available */ 1124 write_c0_guestctl1(MIPS_GCTL1_ID); 1125 back_to_back_c0_hazard(); 1126 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1127 >> MIPS_GCTL1_ID_SHIFT; 1128 write_c0_guestctl1(0); 1129 } 1130 } 1131 1132 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1133 { 1134 /* determine the number of bits of GTOffset available */ 1135 write_c0_gtoffset(0xffffffff); 1136 back_to_back_c0_hazard(); 1137 c->gtoffset_mask = read_c0_gtoffset(); 1138 write_c0_gtoffset(0); 1139 } 1140 1141 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1142 { 1143 cpu_probe_guestctl0(c); 1144 if (cpu_has_guestctl1) 1145 cpu_probe_guestctl1(c); 1146 1147 cpu_probe_gtoffset(c); 1148 1149 decode_guest_configs(c); 1150 } 1151 1152 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1153 | MIPS_CPU_COUNTER) 1154 1155 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1156 { 1157 switch (c->processor_id & PRID_IMP_MASK) { 1158 case PRID_IMP_R2000: 1159 c->cputype = CPU_R2000; 1160 __cpu_name[cpu] = "R2000"; 1161 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1162 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1163 MIPS_CPU_NOFPUEX; 1164 if (__cpu_has_fpu()) 1165 c->options |= MIPS_CPU_FPU; 1166 c->tlbsize = 64; 1167 break; 1168 case PRID_IMP_R3000: 1169 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1170 if (cpu_has_confreg()) { 1171 c->cputype = CPU_R3081E; 1172 __cpu_name[cpu] = "R3081"; 1173 } else { 1174 c->cputype = CPU_R3000A; 1175 __cpu_name[cpu] = "R3000A"; 1176 } 1177 } else { 1178 c->cputype = CPU_R3000; 1179 __cpu_name[cpu] = "R3000"; 1180 } 1181 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1182 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1183 MIPS_CPU_NOFPUEX; 1184 if (__cpu_has_fpu()) 1185 c->options |= MIPS_CPU_FPU; 1186 c->tlbsize = 64; 1187 break; 1188 case PRID_IMP_R4000: 1189 if (read_c0_config() & CONF_SC) { 1190 if ((c->processor_id & PRID_REV_MASK) >= 1191 PRID_REV_R4400) { 1192 c->cputype = CPU_R4400PC; 1193 __cpu_name[cpu] = "R4400PC"; 1194 } else { 1195 c->cputype = CPU_R4000PC; 1196 __cpu_name[cpu] = "R4000PC"; 1197 } 1198 } else { 1199 int cca = read_c0_config() & CONF_CM_CMASK; 1200 int mc; 1201 1202 /* 1203 * SC and MC versions can't be reliably told apart, 1204 * but only the latter support coherent caching 1205 * modes so assume the firmware has set the KSEG0 1206 * coherency attribute reasonably (if uncached, we 1207 * assume SC). 1208 */ 1209 switch (cca) { 1210 case CONF_CM_CACHABLE_CE: 1211 case CONF_CM_CACHABLE_COW: 1212 case CONF_CM_CACHABLE_CUW: 1213 mc = 1; 1214 break; 1215 default: 1216 mc = 0; 1217 break; 1218 } 1219 if ((c->processor_id & PRID_REV_MASK) >= 1220 PRID_REV_R4400) { 1221 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1222 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1223 } else { 1224 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1225 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1226 } 1227 } 1228 1229 set_isa(c, MIPS_CPU_ISA_III); 1230 c->fpu_msk31 |= FPU_CSR_CONDX; 1231 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1232 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1233 MIPS_CPU_LLSC; 1234 c->tlbsize = 48; 1235 break; 1236 case PRID_IMP_VR41XX: 1237 set_isa(c, MIPS_CPU_ISA_III); 1238 c->fpu_msk31 |= FPU_CSR_CONDX; 1239 c->options = R4K_OPTS; 1240 c->tlbsize = 32; 1241 switch (c->processor_id & 0xf0) { 1242 case PRID_REV_VR4111: 1243 c->cputype = CPU_VR4111; 1244 __cpu_name[cpu] = "NEC VR4111"; 1245 break; 1246 case PRID_REV_VR4121: 1247 c->cputype = CPU_VR4121; 1248 __cpu_name[cpu] = "NEC VR4121"; 1249 break; 1250 case PRID_REV_VR4122: 1251 if ((c->processor_id & 0xf) < 0x3) { 1252 c->cputype = CPU_VR4122; 1253 __cpu_name[cpu] = "NEC VR4122"; 1254 } else { 1255 c->cputype = CPU_VR4181A; 1256 __cpu_name[cpu] = "NEC VR4181A"; 1257 } 1258 break; 1259 case PRID_REV_VR4130: 1260 if ((c->processor_id & 0xf) < 0x4) { 1261 c->cputype = CPU_VR4131; 1262 __cpu_name[cpu] = "NEC VR4131"; 1263 } else { 1264 c->cputype = CPU_VR4133; 1265 c->options |= MIPS_CPU_LLSC; 1266 __cpu_name[cpu] = "NEC VR4133"; 1267 } 1268 break; 1269 default: 1270 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1271 c->cputype = CPU_VR41XX; 1272 __cpu_name[cpu] = "NEC Vr41xx"; 1273 break; 1274 } 1275 break; 1276 case PRID_IMP_R4300: 1277 c->cputype = CPU_R4300; 1278 __cpu_name[cpu] = "R4300"; 1279 set_isa(c, MIPS_CPU_ISA_III); 1280 c->fpu_msk31 |= FPU_CSR_CONDX; 1281 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1282 MIPS_CPU_LLSC; 1283 c->tlbsize = 32; 1284 break; 1285 case PRID_IMP_R4600: 1286 c->cputype = CPU_R4600; 1287 __cpu_name[cpu] = "R4600"; 1288 set_isa(c, MIPS_CPU_ISA_III); 1289 c->fpu_msk31 |= FPU_CSR_CONDX; 1290 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1291 MIPS_CPU_LLSC; 1292 c->tlbsize = 48; 1293 break; 1294 #if 0 1295 case PRID_IMP_R4650: 1296 /* 1297 * This processor doesn't have an MMU, so it's not 1298 * "real easy" to run Linux on it. It is left purely 1299 * for documentation. Commented out because it shares 1300 * it's c0_prid id number with the TX3900. 1301 */ 1302 c->cputype = CPU_R4650; 1303 __cpu_name[cpu] = "R4650"; 1304 set_isa(c, MIPS_CPU_ISA_III); 1305 c->fpu_msk31 |= FPU_CSR_CONDX; 1306 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1307 c->tlbsize = 48; 1308 break; 1309 #endif 1310 case PRID_IMP_TX39: 1311 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1312 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1313 1314 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1315 c->cputype = CPU_TX3927; 1316 __cpu_name[cpu] = "TX3927"; 1317 c->tlbsize = 64; 1318 } else { 1319 switch (c->processor_id & PRID_REV_MASK) { 1320 case PRID_REV_TX3912: 1321 c->cputype = CPU_TX3912; 1322 __cpu_name[cpu] = "TX3912"; 1323 c->tlbsize = 32; 1324 break; 1325 case PRID_REV_TX3922: 1326 c->cputype = CPU_TX3922; 1327 __cpu_name[cpu] = "TX3922"; 1328 c->tlbsize = 64; 1329 break; 1330 } 1331 } 1332 break; 1333 case PRID_IMP_R4700: 1334 c->cputype = CPU_R4700; 1335 __cpu_name[cpu] = "R4700"; 1336 set_isa(c, MIPS_CPU_ISA_III); 1337 c->fpu_msk31 |= FPU_CSR_CONDX; 1338 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1339 MIPS_CPU_LLSC; 1340 c->tlbsize = 48; 1341 break; 1342 case PRID_IMP_TX49: 1343 c->cputype = CPU_TX49XX; 1344 __cpu_name[cpu] = "R49XX"; 1345 set_isa(c, MIPS_CPU_ISA_III); 1346 c->fpu_msk31 |= FPU_CSR_CONDX; 1347 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1348 if (!(c->processor_id & 0x08)) 1349 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1350 c->tlbsize = 48; 1351 break; 1352 case PRID_IMP_R5000: 1353 c->cputype = CPU_R5000; 1354 __cpu_name[cpu] = "R5000"; 1355 set_isa(c, MIPS_CPU_ISA_IV); 1356 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1357 MIPS_CPU_LLSC; 1358 c->tlbsize = 48; 1359 break; 1360 case PRID_IMP_R5432: 1361 c->cputype = CPU_R5432; 1362 __cpu_name[cpu] = "R5432"; 1363 set_isa(c, MIPS_CPU_ISA_IV); 1364 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1365 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1366 c->tlbsize = 48; 1367 break; 1368 case PRID_IMP_R5500: 1369 c->cputype = CPU_R5500; 1370 __cpu_name[cpu] = "R5500"; 1371 set_isa(c, MIPS_CPU_ISA_IV); 1372 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1373 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1374 c->tlbsize = 48; 1375 break; 1376 case PRID_IMP_NEVADA: 1377 c->cputype = CPU_NEVADA; 1378 __cpu_name[cpu] = "Nevada"; 1379 set_isa(c, MIPS_CPU_ISA_IV); 1380 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1381 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1382 c->tlbsize = 48; 1383 break; 1384 case PRID_IMP_R6000: 1385 c->cputype = CPU_R6000; 1386 __cpu_name[cpu] = "R6000"; 1387 set_isa(c, MIPS_CPU_ISA_II); 1388 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1389 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1390 MIPS_CPU_LLSC; 1391 c->tlbsize = 32; 1392 break; 1393 case PRID_IMP_R6000A: 1394 c->cputype = CPU_R6000A; 1395 __cpu_name[cpu] = "R6000A"; 1396 set_isa(c, MIPS_CPU_ISA_II); 1397 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1398 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1399 MIPS_CPU_LLSC; 1400 c->tlbsize = 32; 1401 break; 1402 case PRID_IMP_RM7000: 1403 c->cputype = CPU_RM7000; 1404 __cpu_name[cpu] = "RM7000"; 1405 set_isa(c, MIPS_CPU_ISA_IV); 1406 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1407 MIPS_CPU_LLSC; 1408 /* 1409 * Undocumented RM7000: Bit 29 in the info register of 1410 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1411 * entries. 1412 * 1413 * 29 1 => 64 entry JTLB 1414 * 0 => 48 entry JTLB 1415 */ 1416 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1417 break; 1418 case PRID_IMP_R8000: 1419 c->cputype = CPU_R8000; 1420 __cpu_name[cpu] = "RM8000"; 1421 set_isa(c, MIPS_CPU_ISA_IV); 1422 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 1423 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1424 MIPS_CPU_LLSC; 1425 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 1426 break; 1427 case PRID_IMP_R10000: 1428 c->cputype = CPU_R10000; 1429 __cpu_name[cpu] = "R10000"; 1430 set_isa(c, MIPS_CPU_ISA_IV); 1431 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1432 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1433 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1434 MIPS_CPU_LLSC; 1435 c->tlbsize = 64; 1436 break; 1437 case PRID_IMP_R12000: 1438 c->cputype = CPU_R12000; 1439 __cpu_name[cpu] = "R12000"; 1440 set_isa(c, MIPS_CPU_ISA_IV); 1441 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1442 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1443 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1444 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1445 c->tlbsize = 64; 1446 break; 1447 case PRID_IMP_R14000: 1448 if (((c->processor_id >> 4) & 0x0f) > 2) { 1449 c->cputype = CPU_R16000; 1450 __cpu_name[cpu] = "R16000"; 1451 } else { 1452 c->cputype = CPU_R14000; 1453 __cpu_name[cpu] = "R14000"; 1454 } 1455 set_isa(c, MIPS_CPU_ISA_IV); 1456 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1457 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1458 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1459 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1460 c->tlbsize = 64; 1461 break; 1462 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1463 switch (c->processor_id & PRID_REV_MASK) { 1464 case PRID_REV_LOONGSON2E: 1465 c->cputype = CPU_LOONGSON2; 1466 __cpu_name[cpu] = "ICT Loongson-2"; 1467 set_elf_platform(cpu, "loongson2e"); 1468 set_isa(c, MIPS_CPU_ISA_III); 1469 c->fpu_msk31 |= FPU_CSR_CONDX; 1470 break; 1471 case PRID_REV_LOONGSON2F: 1472 c->cputype = CPU_LOONGSON2; 1473 __cpu_name[cpu] = "ICT Loongson-2"; 1474 set_elf_platform(cpu, "loongson2f"); 1475 set_isa(c, MIPS_CPU_ISA_III); 1476 c->fpu_msk31 |= FPU_CSR_CONDX; 1477 break; 1478 case PRID_REV_LOONGSON3A_R1: 1479 c->cputype = CPU_LOONGSON3; 1480 __cpu_name[cpu] = "ICT Loongson-3"; 1481 set_elf_platform(cpu, "loongson3a"); 1482 set_isa(c, MIPS_CPU_ISA_M64R1); 1483 break; 1484 case PRID_REV_LOONGSON3B_R1: 1485 case PRID_REV_LOONGSON3B_R2: 1486 c->cputype = CPU_LOONGSON3; 1487 __cpu_name[cpu] = "ICT Loongson-3"; 1488 set_elf_platform(cpu, "loongson3b"); 1489 set_isa(c, MIPS_CPU_ISA_M64R1); 1490 break; 1491 } 1492 1493 c->options = R4K_OPTS | 1494 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1495 MIPS_CPU_32FPR; 1496 c->tlbsize = 64; 1497 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1498 break; 1499 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1500 decode_configs(c); 1501 1502 c->cputype = CPU_LOONGSON1; 1503 1504 switch (c->processor_id & PRID_REV_MASK) { 1505 case PRID_REV_LOONGSON1B: 1506 __cpu_name[cpu] = "Loongson 1B"; 1507 break; 1508 } 1509 1510 break; 1511 } 1512 } 1513 1514 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1515 { 1516 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1517 switch (c->processor_id & PRID_IMP_MASK) { 1518 case PRID_IMP_QEMU_GENERIC: 1519 c->writecombine = _CACHE_UNCACHED; 1520 c->cputype = CPU_QEMU_GENERIC; 1521 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1522 break; 1523 case PRID_IMP_4KC: 1524 c->cputype = CPU_4KC; 1525 c->writecombine = _CACHE_UNCACHED; 1526 __cpu_name[cpu] = "MIPS 4Kc"; 1527 break; 1528 case PRID_IMP_4KEC: 1529 case PRID_IMP_4KECR2: 1530 c->cputype = CPU_4KEC; 1531 c->writecombine = _CACHE_UNCACHED; 1532 __cpu_name[cpu] = "MIPS 4KEc"; 1533 break; 1534 case PRID_IMP_4KSC: 1535 case PRID_IMP_4KSD: 1536 c->cputype = CPU_4KSC; 1537 c->writecombine = _CACHE_UNCACHED; 1538 __cpu_name[cpu] = "MIPS 4KSc"; 1539 break; 1540 case PRID_IMP_5KC: 1541 c->cputype = CPU_5KC; 1542 c->writecombine = _CACHE_UNCACHED; 1543 __cpu_name[cpu] = "MIPS 5Kc"; 1544 break; 1545 case PRID_IMP_5KE: 1546 c->cputype = CPU_5KE; 1547 c->writecombine = _CACHE_UNCACHED; 1548 __cpu_name[cpu] = "MIPS 5KE"; 1549 break; 1550 case PRID_IMP_20KC: 1551 c->cputype = CPU_20KC; 1552 c->writecombine = _CACHE_UNCACHED; 1553 __cpu_name[cpu] = "MIPS 20Kc"; 1554 break; 1555 case PRID_IMP_24K: 1556 c->cputype = CPU_24K; 1557 c->writecombine = _CACHE_UNCACHED; 1558 __cpu_name[cpu] = "MIPS 24Kc"; 1559 break; 1560 case PRID_IMP_24KE: 1561 c->cputype = CPU_24K; 1562 c->writecombine = _CACHE_UNCACHED; 1563 __cpu_name[cpu] = "MIPS 24KEc"; 1564 break; 1565 case PRID_IMP_25KF: 1566 c->cputype = CPU_25KF; 1567 c->writecombine = _CACHE_UNCACHED; 1568 __cpu_name[cpu] = "MIPS 25Kc"; 1569 break; 1570 case PRID_IMP_34K: 1571 c->cputype = CPU_34K; 1572 c->writecombine = _CACHE_UNCACHED; 1573 __cpu_name[cpu] = "MIPS 34Kc"; 1574 break; 1575 case PRID_IMP_74K: 1576 c->cputype = CPU_74K; 1577 c->writecombine = _CACHE_UNCACHED; 1578 __cpu_name[cpu] = "MIPS 74Kc"; 1579 break; 1580 case PRID_IMP_M14KC: 1581 c->cputype = CPU_M14KC; 1582 c->writecombine = _CACHE_UNCACHED; 1583 __cpu_name[cpu] = "MIPS M14Kc"; 1584 break; 1585 case PRID_IMP_M14KEC: 1586 c->cputype = CPU_M14KEC; 1587 c->writecombine = _CACHE_UNCACHED; 1588 __cpu_name[cpu] = "MIPS M14KEc"; 1589 break; 1590 case PRID_IMP_1004K: 1591 c->cputype = CPU_1004K; 1592 c->writecombine = _CACHE_UNCACHED; 1593 __cpu_name[cpu] = "MIPS 1004Kc"; 1594 break; 1595 case PRID_IMP_1074K: 1596 c->cputype = CPU_1074K; 1597 c->writecombine = _CACHE_UNCACHED; 1598 __cpu_name[cpu] = "MIPS 1074Kc"; 1599 break; 1600 case PRID_IMP_INTERAPTIV_UP: 1601 c->cputype = CPU_INTERAPTIV; 1602 __cpu_name[cpu] = "MIPS interAptiv"; 1603 break; 1604 case PRID_IMP_INTERAPTIV_MP: 1605 c->cputype = CPU_INTERAPTIV; 1606 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1607 break; 1608 case PRID_IMP_PROAPTIV_UP: 1609 c->cputype = CPU_PROAPTIV; 1610 __cpu_name[cpu] = "MIPS proAptiv"; 1611 break; 1612 case PRID_IMP_PROAPTIV_MP: 1613 c->cputype = CPU_PROAPTIV; 1614 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1615 break; 1616 case PRID_IMP_P5600: 1617 c->cputype = CPU_P5600; 1618 __cpu_name[cpu] = "MIPS P5600"; 1619 break; 1620 case PRID_IMP_P6600: 1621 c->cputype = CPU_P6600; 1622 __cpu_name[cpu] = "MIPS P6600"; 1623 break; 1624 case PRID_IMP_I6400: 1625 c->cputype = CPU_I6400; 1626 __cpu_name[cpu] = "MIPS I6400"; 1627 break; 1628 case PRID_IMP_M5150: 1629 c->cputype = CPU_M5150; 1630 __cpu_name[cpu] = "MIPS M5150"; 1631 break; 1632 case PRID_IMP_M6250: 1633 c->cputype = CPU_M6250; 1634 __cpu_name[cpu] = "MIPS M6250"; 1635 break; 1636 } 1637 1638 decode_configs(c); 1639 1640 spram_config(); 1641 } 1642 1643 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1644 { 1645 decode_configs(c); 1646 switch (c->processor_id & PRID_IMP_MASK) { 1647 case PRID_IMP_AU1_REV1: 1648 case PRID_IMP_AU1_REV2: 1649 c->cputype = CPU_ALCHEMY; 1650 switch ((c->processor_id >> 24) & 0xff) { 1651 case 0: 1652 __cpu_name[cpu] = "Au1000"; 1653 break; 1654 case 1: 1655 __cpu_name[cpu] = "Au1500"; 1656 break; 1657 case 2: 1658 __cpu_name[cpu] = "Au1100"; 1659 break; 1660 case 3: 1661 __cpu_name[cpu] = "Au1550"; 1662 break; 1663 case 4: 1664 __cpu_name[cpu] = "Au1200"; 1665 if ((c->processor_id & PRID_REV_MASK) == 2) 1666 __cpu_name[cpu] = "Au1250"; 1667 break; 1668 case 5: 1669 __cpu_name[cpu] = "Au1210"; 1670 break; 1671 default: 1672 __cpu_name[cpu] = "Au1xxx"; 1673 break; 1674 } 1675 break; 1676 } 1677 } 1678 1679 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1680 { 1681 decode_configs(c); 1682 1683 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1684 switch (c->processor_id & PRID_IMP_MASK) { 1685 case PRID_IMP_SB1: 1686 c->cputype = CPU_SB1; 1687 __cpu_name[cpu] = "SiByte SB1"; 1688 /* FPU in pass1 is known to have issues. */ 1689 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1690 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1691 break; 1692 case PRID_IMP_SB1A: 1693 c->cputype = CPU_SB1A; 1694 __cpu_name[cpu] = "SiByte SB1A"; 1695 break; 1696 } 1697 } 1698 1699 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1700 { 1701 decode_configs(c); 1702 switch (c->processor_id & PRID_IMP_MASK) { 1703 case PRID_IMP_SR71000: 1704 c->cputype = CPU_SR71000; 1705 __cpu_name[cpu] = "Sandcraft SR71000"; 1706 c->scache.ways = 8; 1707 c->tlbsize = 64; 1708 break; 1709 } 1710 } 1711 1712 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1713 { 1714 decode_configs(c); 1715 switch (c->processor_id & PRID_IMP_MASK) { 1716 case PRID_IMP_PR4450: 1717 c->cputype = CPU_PR4450; 1718 __cpu_name[cpu] = "Philips PR4450"; 1719 set_isa(c, MIPS_CPU_ISA_M32R1); 1720 break; 1721 } 1722 } 1723 1724 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1725 { 1726 decode_configs(c); 1727 switch (c->processor_id & PRID_IMP_MASK) { 1728 case PRID_IMP_BMIPS32_REV4: 1729 case PRID_IMP_BMIPS32_REV8: 1730 c->cputype = CPU_BMIPS32; 1731 __cpu_name[cpu] = "Broadcom BMIPS32"; 1732 set_elf_platform(cpu, "bmips32"); 1733 break; 1734 case PRID_IMP_BMIPS3300: 1735 case PRID_IMP_BMIPS3300_ALT: 1736 case PRID_IMP_BMIPS3300_BUG: 1737 c->cputype = CPU_BMIPS3300; 1738 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1739 set_elf_platform(cpu, "bmips3300"); 1740 break; 1741 case PRID_IMP_BMIPS43XX: { 1742 int rev = c->processor_id & PRID_REV_MASK; 1743 1744 if (rev >= PRID_REV_BMIPS4380_LO && 1745 rev <= PRID_REV_BMIPS4380_HI) { 1746 c->cputype = CPU_BMIPS4380; 1747 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1748 set_elf_platform(cpu, "bmips4380"); 1749 c->options |= MIPS_CPU_RIXI; 1750 } else { 1751 c->cputype = CPU_BMIPS4350; 1752 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1753 set_elf_platform(cpu, "bmips4350"); 1754 } 1755 break; 1756 } 1757 case PRID_IMP_BMIPS5000: 1758 case PRID_IMP_BMIPS5200: 1759 c->cputype = CPU_BMIPS5000; 1760 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1761 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1762 else 1763 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1764 set_elf_platform(cpu, "bmips5000"); 1765 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1766 break; 1767 } 1768 } 1769 1770 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1771 { 1772 decode_configs(c); 1773 switch (c->processor_id & PRID_IMP_MASK) { 1774 case PRID_IMP_CAVIUM_CN38XX: 1775 case PRID_IMP_CAVIUM_CN31XX: 1776 case PRID_IMP_CAVIUM_CN30XX: 1777 c->cputype = CPU_CAVIUM_OCTEON; 1778 __cpu_name[cpu] = "Cavium Octeon"; 1779 goto platform; 1780 case PRID_IMP_CAVIUM_CN58XX: 1781 case PRID_IMP_CAVIUM_CN56XX: 1782 case PRID_IMP_CAVIUM_CN50XX: 1783 case PRID_IMP_CAVIUM_CN52XX: 1784 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1785 __cpu_name[cpu] = "Cavium Octeon+"; 1786 platform: 1787 set_elf_platform(cpu, "octeon"); 1788 break; 1789 case PRID_IMP_CAVIUM_CN61XX: 1790 case PRID_IMP_CAVIUM_CN63XX: 1791 case PRID_IMP_CAVIUM_CN66XX: 1792 case PRID_IMP_CAVIUM_CN68XX: 1793 case PRID_IMP_CAVIUM_CNF71XX: 1794 c->cputype = CPU_CAVIUM_OCTEON2; 1795 __cpu_name[cpu] = "Cavium Octeon II"; 1796 set_elf_platform(cpu, "octeon2"); 1797 break; 1798 case PRID_IMP_CAVIUM_CN70XX: 1799 case PRID_IMP_CAVIUM_CN73XX: 1800 case PRID_IMP_CAVIUM_CNF75XX: 1801 case PRID_IMP_CAVIUM_CN78XX: 1802 c->cputype = CPU_CAVIUM_OCTEON3; 1803 __cpu_name[cpu] = "Cavium Octeon III"; 1804 set_elf_platform(cpu, "octeon3"); 1805 break; 1806 default: 1807 printk(KERN_INFO "Unknown Octeon chip!\n"); 1808 c->cputype = CPU_UNKNOWN; 1809 break; 1810 } 1811 } 1812 1813 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1814 { 1815 switch (c->processor_id & PRID_IMP_MASK) { 1816 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1817 switch (c->processor_id & PRID_REV_MASK) { 1818 case PRID_REV_LOONGSON3A_R2: 1819 c->cputype = CPU_LOONGSON3; 1820 __cpu_name[cpu] = "ICT Loongson-3"; 1821 set_elf_platform(cpu, "loongson3a"); 1822 set_isa(c, MIPS_CPU_ISA_M64R2); 1823 break; 1824 } 1825 1826 decode_configs(c); 1827 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1828 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1829 break; 1830 default: 1831 panic("Unknown Loongson Processor ID!"); 1832 break; 1833 } 1834 } 1835 1836 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1837 { 1838 decode_configs(c); 1839 /* JZRISC does not implement the CP0 counter. */ 1840 c->options &= ~MIPS_CPU_COUNTER; 1841 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1842 switch (c->processor_id & PRID_IMP_MASK) { 1843 case PRID_IMP_JZRISC: 1844 c->cputype = CPU_JZRISC; 1845 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1846 __cpu_name[cpu] = "Ingenic JZRISC"; 1847 break; 1848 default: 1849 panic("Unknown Ingenic Processor ID!"); 1850 break; 1851 } 1852 } 1853 1854 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1855 { 1856 decode_configs(c); 1857 1858 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1859 c->cputype = CPU_ALCHEMY; 1860 __cpu_name[cpu] = "Au1300"; 1861 /* following stuff is not for Alchemy */ 1862 return; 1863 } 1864 1865 c->options = (MIPS_CPU_TLB | 1866 MIPS_CPU_4KEX | 1867 MIPS_CPU_COUNTER | 1868 MIPS_CPU_DIVEC | 1869 MIPS_CPU_WATCH | 1870 MIPS_CPU_EJTAG | 1871 MIPS_CPU_LLSC); 1872 1873 switch (c->processor_id & PRID_IMP_MASK) { 1874 case PRID_IMP_NETLOGIC_XLP2XX: 1875 case PRID_IMP_NETLOGIC_XLP9XX: 1876 case PRID_IMP_NETLOGIC_XLP5XX: 1877 c->cputype = CPU_XLP; 1878 __cpu_name[cpu] = "Broadcom XLPII"; 1879 break; 1880 1881 case PRID_IMP_NETLOGIC_XLP8XX: 1882 case PRID_IMP_NETLOGIC_XLP3XX: 1883 c->cputype = CPU_XLP; 1884 __cpu_name[cpu] = "Netlogic XLP"; 1885 break; 1886 1887 case PRID_IMP_NETLOGIC_XLR732: 1888 case PRID_IMP_NETLOGIC_XLR716: 1889 case PRID_IMP_NETLOGIC_XLR532: 1890 case PRID_IMP_NETLOGIC_XLR308: 1891 case PRID_IMP_NETLOGIC_XLR532C: 1892 case PRID_IMP_NETLOGIC_XLR516C: 1893 case PRID_IMP_NETLOGIC_XLR508C: 1894 case PRID_IMP_NETLOGIC_XLR308C: 1895 c->cputype = CPU_XLR; 1896 __cpu_name[cpu] = "Netlogic XLR"; 1897 break; 1898 1899 case PRID_IMP_NETLOGIC_XLS608: 1900 case PRID_IMP_NETLOGIC_XLS408: 1901 case PRID_IMP_NETLOGIC_XLS404: 1902 case PRID_IMP_NETLOGIC_XLS208: 1903 case PRID_IMP_NETLOGIC_XLS204: 1904 case PRID_IMP_NETLOGIC_XLS108: 1905 case PRID_IMP_NETLOGIC_XLS104: 1906 case PRID_IMP_NETLOGIC_XLS616B: 1907 case PRID_IMP_NETLOGIC_XLS608B: 1908 case PRID_IMP_NETLOGIC_XLS416B: 1909 case PRID_IMP_NETLOGIC_XLS412B: 1910 case PRID_IMP_NETLOGIC_XLS408B: 1911 case PRID_IMP_NETLOGIC_XLS404B: 1912 c->cputype = CPU_XLR; 1913 __cpu_name[cpu] = "Netlogic XLS"; 1914 break; 1915 1916 default: 1917 pr_info("Unknown Netlogic chip id [%02x]!\n", 1918 c->processor_id); 1919 c->cputype = CPU_XLR; 1920 break; 1921 } 1922 1923 if (c->cputype == CPU_XLP) { 1924 set_isa(c, MIPS_CPU_ISA_M64R2); 1925 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1926 /* This will be updated again after all threads are woken up */ 1927 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1928 } else { 1929 set_isa(c, MIPS_CPU_ISA_M64R1); 1930 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1931 } 1932 c->kscratch_mask = 0xf; 1933 } 1934 1935 #ifdef CONFIG_64BIT 1936 /* For use by uaccess.h */ 1937 u64 __ua_limit; 1938 EXPORT_SYMBOL(__ua_limit); 1939 #endif 1940 1941 const char *__cpu_name[NR_CPUS]; 1942 const char *__elf_platform; 1943 1944 void cpu_probe(void) 1945 { 1946 struct cpuinfo_mips *c = ¤t_cpu_data; 1947 unsigned int cpu = smp_processor_id(); 1948 1949 c->processor_id = PRID_IMP_UNKNOWN; 1950 c->fpu_id = FPIR_IMP_NONE; 1951 c->cputype = CPU_UNKNOWN; 1952 c->writecombine = _CACHE_UNCACHED; 1953 1954 c->fpu_csr31 = FPU_CSR_RN; 1955 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1956 1957 c->processor_id = read_c0_prid(); 1958 switch (c->processor_id & PRID_COMP_MASK) { 1959 case PRID_COMP_LEGACY: 1960 cpu_probe_legacy(c, cpu); 1961 break; 1962 case PRID_COMP_MIPS: 1963 cpu_probe_mips(c, cpu); 1964 break; 1965 case PRID_COMP_ALCHEMY: 1966 cpu_probe_alchemy(c, cpu); 1967 break; 1968 case PRID_COMP_SIBYTE: 1969 cpu_probe_sibyte(c, cpu); 1970 break; 1971 case PRID_COMP_BROADCOM: 1972 cpu_probe_broadcom(c, cpu); 1973 break; 1974 case PRID_COMP_SANDCRAFT: 1975 cpu_probe_sandcraft(c, cpu); 1976 break; 1977 case PRID_COMP_NXP: 1978 cpu_probe_nxp(c, cpu); 1979 break; 1980 case PRID_COMP_CAVIUM: 1981 cpu_probe_cavium(c, cpu); 1982 break; 1983 case PRID_COMP_LOONGSON: 1984 cpu_probe_loongson(c, cpu); 1985 break; 1986 case PRID_COMP_INGENIC_D0: 1987 case PRID_COMP_INGENIC_D1: 1988 case PRID_COMP_INGENIC_E1: 1989 cpu_probe_ingenic(c, cpu); 1990 break; 1991 case PRID_COMP_NETLOGIC: 1992 cpu_probe_netlogic(c, cpu); 1993 break; 1994 } 1995 1996 BUG_ON(!__cpu_name[cpu]); 1997 BUG_ON(c->cputype == CPU_UNKNOWN); 1998 1999 /* 2000 * Platform code can force the cpu type to optimize code 2001 * generation. In that case be sure the cpu type is correctly 2002 * manually setup otherwise it could trigger some nasty bugs. 2003 */ 2004 BUG_ON(current_cpu_type() != c->cputype); 2005 2006 if (cpu_has_rixi) { 2007 /* Enable the RIXI exceptions */ 2008 set_c0_pagegrain(PG_IEC); 2009 back_to_back_c0_hazard(); 2010 /* Verify the IEC bit is set */ 2011 if (read_c0_pagegrain() & PG_IEC) 2012 c->options |= MIPS_CPU_RIXIEX; 2013 } 2014 2015 if (mips_fpu_disabled) 2016 c->options &= ~MIPS_CPU_FPU; 2017 2018 if (mips_dsp_disabled) 2019 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2020 2021 if (mips_htw_disabled) { 2022 c->options &= ~MIPS_CPU_HTW; 2023 write_c0_pwctl(read_c0_pwctl() & 2024 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2025 } 2026 2027 if (c->options & MIPS_CPU_FPU) 2028 cpu_set_fpu_opts(c); 2029 else 2030 cpu_set_nofpu_opts(c); 2031 2032 if (cpu_has_bp_ghist) 2033 write_c0_r10k_diag(read_c0_r10k_diag() | 2034 R10K_DIAG_E_GHIST); 2035 2036 if (cpu_has_mips_r2_r6) { 2037 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2038 /* R2 has Performance Counter Interrupt indicator */ 2039 c->options |= MIPS_CPU_PCI; 2040 } 2041 else 2042 c->srsets = 1; 2043 2044 if (cpu_has_mips_r6) 2045 elf_hwcap |= HWCAP_MIPS_R6; 2046 2047 if (cpu_has_msa) { 2048 c->msa_id = cpu_get_msa_id(); 2049 WARN(c->msa_id & MSA_IR_WRPF, 2050 "Vector register partitioning unimplemented!"); 2051 elf_hwcap |= HWCAP_MIPS_MSA; 2052 } 2053 2054 if (cpu_has_vz) 2055 cpu_probe_vz(c); 2056 2057 cpu_probe_vmbits(c); 2058 2059 #ifdef CONFIG_64BIT 2060 if (cpu == 0) 2061 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2062 #endif 2063 } 2064 2065 void cpu_report(void) 2066 { 2067 struct cpuinfo_mips *c = ¤t_cpu_data; 2068 2069 pr_info("CPU%d revision is: %08x (%s)\n", 2070 smp_processor_id(), c->processor_id, cpu_name_string()); 2071 if (c->options & MIPS_CPU_FPU) 2072 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2073 if (cpu_has_msa) 2074 pr_info("MSA revision is: %08x\n", c->msa_id); 2075 } 2076