1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void) = NULL; 33 34 static void r3081_wait(void) 35 { 36 unsigned long cfg = read_c0_conf(); 37 write_c0_conf(cfg | R30XX_CONF_HALT); 38 } 39 40 static void r39xx_wait(void) 41 { 42 local_irq_disable(); 43 if (!need_resched()) 44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 45 local_irq_enable(); 46 } 47 48 /* 49 * There is a race when WAIT instruction executed with interrupt 50 * enabled. 51 * But it is implementation-dependent wheter the pipelie restarts when 52 * a non-enabled interrupt is requested. 53 */ 54 static void r4k_wait(void) 55 { 56 __asm__(" .set mips3 \n" 57 " wait \n" 58 " .set mips0 \n"); 59 } 60 61 /* 62 * This variant is preferable as it allows testing need_resched and going to 63 * sleep depending on the outcome atomically. Unfortunately the "It is 64 * implementation-dependent whether the pipeline restarts when a non-enabled 65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 66 * using this version a gamble. 67 */ 68 static void r4k_wait_irqoff(void) 69 { 70 local_irq_disable(); 71 if (!need_resched()) 72 __asm__(" .set mips3 \n" 73 " wait \n" 74 " .set mips0 \n"); 75 local_irq_enable(); 76 } 77 78 /* 79 * The RM7000 variant has to handle erratum 38. The workaround is to not 80 * have any pending stores when the WAIT instruction is executed. 81 */ 82 static void rm7k_wait_irqoff(void) 83 { 84 local_irq_disable(); 85 if (!need_resched()) 86 __asm__( 87 " .set push \n" 88 " .set mips3 \n" 89 " .set noat \n" 90 " mfc0 $1, $12 \n" 91 " sync \n" 92 " mtc0 $1, $12 # stalls until W stage \n" 93 " wait \n" 94 " mtc0 $1, $12 # stalls until W stage \n" 95 " .set pop \n"); 96 local_irq_enable(); 97 } 98 99 /* The Au1xxx wait is available only if using 32khz counter or 100 * external timer source, but specifically not CP0 Counter. */ 101 int allow_au1k_wait; 102 103 static void au1k_wait(void) 104 { 105 /* using the wait instruction makes CP0 counter unusable */ 106 __asm__(" .set mips3 \n" 107 " cache 0x14, 0(%0) \n" 108 " cache 0x14, 32(%0) \n" 109 " sync \n" 110 " nop \n" 111 " wait \n" 112 " nop \n" 113 " nop \n" 114 " nop \n" 115 " nop \n" 116 " .set mips0 \n" 117 : : "r" (au1k_wait)); 118 } 119 120 static int __initdata nowait = 0; 121 122 static int __init wait_disable(char *s) 123 { 124 nowait = 1; 125 126 return 1; 127 } 128 129 __setup("nowait", wait_disable); 130 131 static inline void check_wait(void) 132 { 133 struct cpuinfo_mips *c = ¤t_cpu_data; 134 135 if (nowait) { 136 printk("Wait instruction disabled.\n"); 137 return; 138 } 139 140 switch (c->cputype) { 141 case CPU_R3081: 142 case CPU_R3081E: 143 cpu_wait = r3081_wait; 144 break; 145 case CPU_TX3927: 146 cpu_wait = r39xx_wait; 147 break; 148 case CPU_R4200: 149 /* case CPU_R4300: */ 150 case CPU_R4600: 151 case CPU_R4640: 152 case CPU_R4650: 153 case CPU_R4700: 154 case CPU_R5000: 155 case CPU_NEVADA: 156 case CPU_4KC: 157 case CPU_4KEC: 158 case CPU_4KSC: 159 case CPU_5KC: 160 case CPU_25KF: 161 case CPU_PR4450: 162 cpu_wait = r4k_wait; 163 break; 164 165 case CPU_RM7000: 166 cpu_wait = rm7k_wait_irqoff; 167 break; 168 169 case CPU_24K: 170 case CPU_34K: 171 cpu_wait = r4k_wait; 172 if (read_c0_config7() & MIPS_CONF7_WII) 173 cpu_wait = r4k_wait_irqoff; 174 break; 175 176 case CPU_74K: 177 cpu_wait = r4k_wait; 178 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 179 cpu_wait = r4k_wait_irqoff; 180 break; 181 182 case CPU_TX49XX: 183 cpu_wait = r4k_wait_irqoff; 184 break; 185 case CPU_AU1000: 186 case CPU_AU1100: 187 case CPU_AU1500: 188 case CPU_AU1550: 189 case CPU_AU1200: 190 if (allow_au1k_wait) 191 cpu_wait = au1k_wait; 192 break; 193 case CPU_20KC: 194 /* 195 * WAIT on Rev1.0 has E1, E2, E3 and E16. 196 * WAIT on Rev2.0 and Rev3.0 has E16. 197 * Rev3.1 WAIT is nop, why bother 198 */ 199 if ((c->processor_id & 0xff) <= 0x64) 200 break; 201 202 cpu_wait = r4k_wait; 203 break; 204 case CPU_RM9000: 205 if ((c->processor_id & 0x00ff) >= 0x40) 206 cpu_wait = r4k_wait; 207 break; 208 default: 209 break; 210 } 211 } 212 213 static inline void check_errata(void) 214 { 215 struct cpuinfo_mips *c = ¤t_cpu_data; 216 217 switch (c->cputype) { 218 case CPU_34K: 219 /* 220 * Erratum "RPS May Cause Incorrect Instruction Execution" 221 * This code only handles VPE0, any SMP/SMTC/RTOS code 222 * making use of VPE1 will be responsable for that VPE. 223 */ 224 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 225 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 226 break; 227 default: 228 break; 229 } 230 } 231 232 void __init check_bugs32(void) 233 { 234 check_wait(); 235 check_errata(); 236 } 237 238 /* 239 * Probe whether cpu has config register by trying to play with 240 * alternate cache bit and see whether it matters. 241 * It's used by cpu_probe to distinguish between R3000A and R3081. 242 */ 243 static inline int cpu_has_confreg(void) 244 { 245 #ifdef CONFIG_CPU_R3000 246 extern unsigned long r3k_cache_size(unsigned long); 247 unsigned long size1, size2; 248 unsigned long cfg = read_c0_conf(); 249 250 size1 = r3k_cache_size(ST0_ISC); 251 write_c0_conf(cfg ^ R30XX_CONF_AC); 252 size2 = r3k_cache_size(ST0_ISC); 253 write_c0_conf(cfg); 254 return size1 != size2; 255 #else 256 return 0; 257 #endif 258 } 259 260 /* 261 * Get the FPU Implementation/Revision. 262 */ 263 static inline unsigned long cpu_get_fpu_id(void) 264 { 265 unsigned long tmp, fpu_id; 266 267 tmp = read_c0_status(); 268 __enable_fpu(); 269 fpu_id = read_32bit_cp1_register(CP1_REVISION); 270 write_c0_status(tmp); 271 return fpu_id; 272 } 273 274 /* 275 * Check the CPU has an FPU the official way. 276 */ 277 static inline int __cpu_has_fpu(void) 278 { 279 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 280 } 281 282 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 283 | MIPS_CPU_COUNTER) 284 285 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 286 { 287 switch (c->processor_id & 0xff00) { 288 case PRID_IMP_R2000: 289 c->cputype = CPU_R2000; 290 c->isa_level = MIPS_CPU_ISA_I; 291 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 292 MIPS_CPU_NOFPUEX; 293 if (__cpu_has_fpu()) 294 c->options |= MIPS_CPU_FPU; 295 c->tlbsize = 64; 296 break; 297 case PRID_IMP_R3000: 298 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 299 if (cpu_has_confreg()) 300 c->cputype = CPU_R3081E; 301 else 302 c->cputype = CPU_R3000A; 303 else 304 c->cputype = CPU_R3000; 305 c->isa_level = MIPS_CPU_ISA_I; 306 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 307 MIPS_CPU_NOFPUEX; 308 if (__cpu_has_fpu()) 309 c->options |= MIPS_CPU_FPU; 310 c->tlbsize = 64; 311 break; 312 case PRID_IMP_R4000: 313 if (read_c0_config() & CONF_SC) { 314 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 315 c->cputype = CPU_R4400PC; 316 else 317 c->cputype = CPU_R4000PC; 318 } else { 319 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 320 c->cputype = CPU_R4400SC; 321 else 322 c->cputype = CPU_R4000SC; 323 } 324 325 c->isa_level = MIPS_CPU_ISA_III; 326 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 327 MIPS_CPU_WATCH | MIPS_CPU_VCE | 328 MIPS_CPU_LLSC; 329 c->tlbsize = 48; 330 break; 331 case PRID_IMP_VR41XX: 332 switch (c->processor_id & 0xf0) { 333 case PRID_REV_VR4111: 334 c->cputype = CPU_VR4111; 335 break; 336 case PRID_REV_VR4121: 337 c->cputype = CPU_VR4121; 338 break; 339 case PRID_REV_VR4122: 340 if ((c->processor_id & 0xf) < 0x3) 341 c->cputype = CPU_VR4122; 342 else 343 c->cputype = CPU_VR4181A; 344 break; 345 case PRID_REV_VR4130: 346 if ((c->processor_id & 0xf) < 0x4) 347 c->cputype = CPU_VR4131; 348 else 349 c->cputype = CPU_VR4133; 350 break; 351 default: 352 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 353 c->cputype = CPU_VR41XX; 354 break; 355 } 356 c->isa_level = MIPS_CPU_ISA_III; 357 c->options = R4K_OPTS; 358 c->tlbsize = 32; 359 break; 360 case PRID_IMP_R4300: 361 c->cputype = CPU_R4300; 362 c->isa_level = MIPS_CPU_ISA_III; 363 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 364 MIPS_CPU_LLSC; 365 c->tlbsize = 32; 366 break; 367 case PRID_IMP_R4600: 368 c->cputype = CPU_R4600; 369 c->isa_level = MIPS_CPU_ISA_III; 370 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 371 MIPS_CPU_LLSC; 372 c->tlbsize = 48; 373 break; 374 #if 0 375 case PRID_IMP_R4650: 376 /* 377 * This processor doesn't have an MMU, so it's not 378 * "real easy" to run Linux on it. It is left purely 379 * for documentation. Commented out because it shares 380 * it's c0_prid id number with the TX3900. 381 */ 382 c->cputype = CPU_R4650; 383 c->isa_level = MIPS_CPU_ISA_III; 384 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 385 c->tlbsize = 48; 386 break; 387 #endif 388 case PRID_IMP_TX39: 389 c->isa_level = MIPS_CPU_ISA_I; 390 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 391 392 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 393 c->cputype = CPU_TX3927; 394 c->tlbsize = 64; 395 } else { 396 switch (c->processor_id & 0xff) { 397 case PRID_REV_TX3912: 398 c->cputype = CPU_TX3912; 399 c->tlbsize = 32; 400 break; 401 case PRID_REV_TX3922: 402 c->cputype = CPU_TX3922; 403 c->tlbsize = 64; 404 break; 405 default: 406 c->cputype = CPU_UNKNOWN; 407 break; 408 } 409 } 410 break; 411 case PRID_IMP_R4700: 412 c->cputype = CPU_R4700; 413 c->isa_level = MIPS_CPU_ISA_III; 414 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 415 MIPS_CPU_LLSC; 416 c->tlbsize = 48; 417 break; 418 case PRID_IMP_TX49: 419 c->cputype = CPU_TX49XX; 420 c->isa_level = MIPS_CPU_ISA_III; 421 c->options = R4K_OPTS | MIPS_CPU_LLSC; 422 if (!(c->processor_id & 0x08)) 423 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 424 c->tlbsize = 48; 425 break; 426 case PRID_IMP_R5000: 427 c->cputype = CPU_R5000; 428 c->isa_level = MIPS_CPU_ISA_IV; 429 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 430 MIPS_CPU_LLSC; 431 c->tlbsize = 48; 432 break; 433 case PRID_IMP_R5432: 434 c->cputype = CPU_R5432; 435 c->isa_level = MIPS_CPU_ISA_IV; 436 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 437 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 438 c->tlbsize = 48; 439 break; 440 case PRID_IMP_R5500: 441 c->cputype = CPU_R5500; 442 c->isa_level = MIPS_CPU_ISA_IV; 443 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 444 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 445 c->tlbsize = 48; 446 break; 447 case PRID_IMP_NEVADA: 448 c->cputype = CPU_NEVADA; 449 c->isa_level = MIPS_CPU_ISA_IV; 450 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 451 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 452 c->tlbsize = 48; 453 break; 454 case PRID_IMP_R6000: 455 c->cputype = CPU_R6000; 456 c->isa_level = MIPS_CPU_ISA_II; 457 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 458 MIPS_CPU_LLSC; 459 c->tlbsize = 32; 460 break; 461 case PRID_IMP_R6000A: 462 c->cputype = CPU_R6000A; 463 c->isa_level = MIPS_CPU_ISA_II; 464 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 465 MIPS_CPU_LLSC; 466 c->tlbsize = 32; 467 break; 468 case PRID_IMP_RM7000: 469 c->cputype = CPU_RM7000; 470 c->isa_level = MIPS_CPU_ISA_IV; 471 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 472 MIPS_CPU_LLSC; 473 /* 474 * Undocumented RM7000: Bit 29 in the info register of 475 * the RM7000 v2.0 indicates if the TLB has 48 or 64 476 * entries. 477 * 478 * 29 1 => 64 entry JTLB 479 * 0 => 48 entry JTLB 480 */ 481 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 482 break; 483 case PRID_IMP_RM9000: 484 c->cputype = CPU_RM9000; 485 c->isa_level = MIPS_CPU_ISA_IV; 486 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 487 MIPS_CPU_LLSC; 488 /* 489 * Bit 29 in the info register of the RM9000 490 * indicates if the TLB has 48 or 64 entries. 491 * 492 * 29 1 => 64 entry JTLB 493 * 0 => 48 entry JTLB 494 */ 495 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 496 break; 497 case PRID_IMP_R8000: 498 c->cputype = CPU_R8000; 499 c->isa_level = MIPS_CPU_ISA_IV; 500 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 501 MIPS_CPU_FPU | MIPS_CPU_32FPR | 502 MIPS_CPU_LLSC; 503 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 504 break; 505 case PRID_IMP_R10000: 506 c->cputype = CPU_R10000; 507 c->isa_level = MIPS_CPU_ISA_IV; 508 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 509 MIPS_CPU_FPU | MIPS_CPU_32FPR | 510 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 511 MIPS_CPU_LLSC; 512 c->tlbsize = 64; 513 break; 514 case PRID_IMP_R12000: 515 c->cputype = CPU_R12000; 516 c->isa_level = MIPS_CPU_ISA_IV; 517 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 518 MIPS_CPU_FPU | MIPS_CPU_32FPR | 519 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 520 MIPS_CPU_LLSC; 521 c->tlbsize = 64; 522 break; 523 case PRID_IMP_R14000: 524 c->cputype = CPU_R14000; 525 c->isa_level = MIPS_CPU_ISA_IV; 526 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 527 MIPS_CPU_FPU | MIPS_CPU_32FPR | 528 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 529 MIPS_CPU_LLSC; 530 c->tlbsize = 64; 531 break; 532 case PRID_IMP_LOONGSON2: 533 c->cputype = CPU_LOONGSON2; 534 c->isa_level = MIPS_CPU_ISA_III; 535 c->options = R4K_OPTS | 536 MIPS_CPU_FPU | MIPS_CPU_LLSC | 537 MIPS_CPU_32FPR; 538 c->tlbsize = 64; 539 break; 540 } 541 } 542 543 static char unknown_isa[] __initdata = KERN_ERR \ 544 "Unsupported ISA type, c0.config0: %d."; 545 546 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 547 { 548 unsigned int config0; 549 int isa; 550 551 config0 = read_c0_config(); 552 553 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 554 c->options |= MIPS_CPU_TLB; 555 isa = (config0 & MIPS_CONF_AT) >> 13; 556 switch (isa) { 557 case 0: 558 switch ((config0 & MIPS_CONF_AR) >> 10) { 559 case 0: 560 c->isa_level = MIPS_CPU_ISA_M32R1; 561 break; 562 case 1: 563 c->isa_level = MIPS_CPU_ISA_M32R2; 564 break; 565 default: 566 goto unknown; 567 } 568 break; 569 case 2: 570 switch ((config0 & MIPS_CONF_AR) >> 10) { 571 case 0: 572 c->isa_level = MIPS_CPU_ISA_M64R1; 573 break; 574 case 1: 575 c->isa_level = MIPS_CPU_ISA_M64R2; 576 break; 577 default: 578 goto unknown; 579 } 580 break; 581 default: 582 goto unknown; 583 } 584 585 return config0 & MIPS_CONF_M; 586 587 unknown: 588 panic(unknown_isa, config0); 589 } 590 591 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 592 { 593 unsigned int config1; 594 595 config1 = read_c0_config1(); 596 597 if (config1 & MIPS_CONF1_MD) 598 c->ases |= MIPS_ASE_MDMX; 599 if (config1 & MIPS_CONF1_WR) 600 c->options |= MIPS_CPU_WATCH; 601 if (config1 & MIPS_CONF1_CA) 602 c->ases |= MIPS_ASE_MIPS16; 603 if (config1 & MIPS_CONF1_EP) 604 c->options |= MIPS_CPU_EJTAG; 605 if (config1 & MIPS_CONF1_FP) { 606 c->options |= MIPS_CPU_FPU; 607 c->options |= MIPS_CPU_32FPR; 608 } 609 if (cpu_has_tlb) 610 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 611 612 return config1 & MIPS_CONF_M; 613 } 614 615 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 616 { 617 unsigned int config2; 618 619 config2 = read_c0_config2(); 620 621 if (config2 & MIPS_CONF2_SL) 622 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 623 624 return config2 & MIPS_CONF_M; 625 } 626 627 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 628 { 629 unsigned int config3; 630 631 config3 = read_c0_config3(); 632 633 if (config3 & MIPS_CONF3_SM) 634 c->ases |= MIPS_ASE_SMARTMIPS; 635 if (config3 & MIPS_CONF3_DSP) 636 c->ases |= MIPS_ASE_DSP; 637 if (config3 & MIPS_CONF3_VINT) 638 c->options |= MIPS_CPU_VINT; 639 if (config3 & MIPS_CONF3_VEIC) 640 c->options |= MIPS_CPU_VEIC; 641 if (config3 & MIPS_CONF3_MT) 642 c->ases |= MIPS_ASE_MIPSMT; 643 if (config3 & MIPS_CONF3_ULRI) 644 c->options |= MIPS_CPU_ULRI; 645 646 return config3 & MIPS_CONF_M; 647 } 648 649 static void __init decode_configs(struct cpuinfo_mips *c) 650 { 651 /* MIPS32 or MIPS64 compliant CPU. */ 652 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 653 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 654 655 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 656 657 /* Read Config registers. */ 658 if (!decode_config0(c)) 659 return; /* actually worth a panic() */ 660 if (!decode_config1(c)) 661 return; 662 if (!decode_config2(c)) 663 return; 664 if (!decode_config3(c)) 665 return; 666 } 667 668 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 669 { 670 decode_configs(c); 671 switch (c->processor_id & 0xff00) { 672 case PRID_IMP_4KC: 673 c->cputype = CPU_4KC; 674 break; 675 case PRID_IMP_4KEC: 676 c->cputype = CPU_4KEC; 677 break; 678 case PRID_IMP_4KECR2: 679 c->cputype = CPU_4KEC; 680 break; 681 case PRID_IMP_4KSC: 682 case PRID_IMP_4KSD: 683 c->cputype = CPU_4KSC; 684 break; 685 case PRID_IMP_5KC: 686 c->cputype = CPU_5KC; 687 break; 688 case PRID_IMP_20KC: 689 c->cputype = CPU_20KC; 690 break; 691 case PRID_IMP_24K: 692 case PRID_IMP_24KE: 693 c->cputype = CPU_24K; 694 break; 695 case PRID_IMP_25KF: 696 c->cputype = CPU_25KF; 697 break; 698 case PRID_IMP_34K: 699 c->cputype = CPU_34K; 700 break; 701 case PRID_IMP_74K: 702 c->cputype = CPU_74K; 703 break; 704 } 705 } 706 707 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 708 { 709 decode_configs(c); 710 switch (c->processor_id & 0xff00) { 711 case PRID_IMP_AU1_REV1: 712 case PRID_IMP_AU1_REV2: 713 switch ((c->processor_id >> 24) & 0xff) { 714 case 0: 715 c->cputype = CPU_AU1000; 716 break; 717 case 1: 718 c->cputype = CPU_AU1500; 719 break; 720 case 2: 721 c->cputype = CPU_AU1100; 722 break; 723 case 3: 724 c->cputype = CPU_AU1550; 725 break; 726 case 4: 727 c->cputype = CPU_AU1200; 728 break; 729 default: 730 panic("Unknown Au Core!"); 731 break; 732 } 733 break; 734 } 735 } 736 737 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 738 { 739 decode_configs(c); 740 741 /* 742 * For historical reasons the SB1 comes with it's own variant of 743 * cache code which eventually will be folded into c-r4k.c. Until 744 * then we pretend it's got it's own cache architecture. 745 */ 746 c->options &= ~MIPS_CPU_4K_CACHE; 747 c->options |= MIPS_CPU_SB1_CACHE; 748 749 switch (c->processor_id & 0xff00) { 750 case PRID_IMP_SB1: 751 c->cputype = CPU_SB1; 752 /* FPU in pass1 is known to have issues. */ 753 if ((c->processor_id & 0xff) < 0x02) 754 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 755 break; 756 case PRID_IMP_SB1A: 757 c->cputype = CPU_SB1A; 758 break; 759 } 760 } 761 762 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 763 { 764 decode_configs(c); 765 switch (c->processor_id & 0xff00) { 766 case PRID_IMP_SR71000: 767 c->cputype = CPU_SR71000; 768 c->scache.ways = 8; 769 c->tlbsize = 64; 770 break; 771 } 772 } 773 774 static inline void cpu_probe_philips(struct cpuinfo_mips *c) 775 { 776 decode_configs(c); 777 switch (c->processor_id & 0xff00) { 778 case PRID_IMP_PR4450: 779 c->cputype = CPU_PR4450; 780 c->isa_level = MIPS_CPU_ISA_M32R1; 781 break; 782 default: 783 panic("Unknown Philips Core!"); /* REVISIT: die? */ 784 break; 785 } 786 } 787 788 789 __init void cpu_probe(void) 790 { 791 struct cpuinfo_mips *c = ¤t_cpu_data; 792 793 c->processor_id = PRID_IMP_UNKNOWN; 794 c->fpu_id = FPIR_IMP_NONE; 795 c->cputype = CPU_UNKNOWN; 796 797 c->processor_id = read_c0_prid(); 798 switch (c->processor_id & 0xff0000) { 799 case PRID_COMP_LEGACY: 800 cpu_probe_legacy(c); 801 break; 802 case PRID_COMP_MIPS: 803 cpu_probe_mips(c); 804 break; 805 case PRID_COMP_ALCHEMY: 806 cpu_probe_alchemy(c); 807 break; 808 case PRID_COMP_SIBYTE: 809 cpu_probe_sibyte(c); 810 break; 811 case PRID_COMP_SANDCRAFT: 812 cpu_probe_sandcraft(c); 813 break; 814 case PRID_COMP_PHILIPS: 815 cpu_probe_philips(c); 816 break; 817 default: 818 c->cputype = CPU_UNKNOWN; 819 } 820 if (c->options & MIPS_CPU_FPU) { 821 c->fpu_id = cpu_get_fpu_id(); 822 823 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 824 c->isa_level == MIPS_CPU_ISA_M32R2 || 825 c->isa_level == MIPS_CPU_ISA_M64R1 || 826 c->isa_level == MIPS_CPU_ISA_M64R2) { 827 if (c->fpu_id & MIPS_FPIR_3D) 828 c->ases |= MIPS_ASE_MIPS3D; 829 } 830 } 831 } 832 833 __init void cpu_report(void) 834 { 835 struct cpuinfo_mips *c = ¤t_cpu_data; 836 837 printk("CPU revision is: %08x\n", c->processor_id); 838 if (c->options & MIPS_CPU_FPU) 839 printk("FPU revision is: %08x\n", c->fpu_id); 840 } 841