1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/watch.h> 27 #include <asm/elf.h> 28 #include <asm/spram.h> 29 #include <asm/uaccess.h> 30 31 static int mips_fpu_disabled; 32 33 static int __init fpu_disable(char *s) 34 { 35 cpu_data[0].options &= ~MIPS_CPU_FPU; 36 mips_fpu_disabled = 1; 37 38 return 1; 39 } 40 41 __setup("nofpu", fpu_disable); 42 43 int mips_dsp_disabled; 44 45 static int __init dsp_disable(char *s) 46 { 47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 48 mips_dsp_disabled = 1; 49 50 return 1; 51 } 52 53 __setup("nodsp", dsp_disable); 54 55 static inline void check_errata(void) 56 { 57 struct cpuinfo_mips *c = ¤t_cpu_data; 58 59 switch (current_cpu_type()) { 60 case CPU_34K: 61 /* 62 * Erratum "RPS May Cause Incorrect Instruction Execution" 63 * This code only handles VPE0, any SMP/SMTC/RTOS code 64 * making use of VPE1 will be responsable for that VPE. 65 */ 66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 68 break; 69 default: 70 break; 71 } 72 } 73 74 void __init check_bugs32(void) 75 { 76 check_errata(); 77 } 78 79 /* 80 * Probe whether cpu has config register by trying to play with 81 * alternate cache bit and see whether it matters. 82 * It's used by cpu_probe to distinguish between R3000A and R3081. 83 */ 84 static inline int cpu_has_confreg(void) 85 { 86 #ifdef CONFIG_CPU_R3000 87 extern unsigned long r3k_cache_size(unsigned long); 88 unsigned long size1, size2; 89 unsigned long cfg = read_c0_conf(); 90 91 size1 = r3k_cache_size(ST0_ISC); 92 write_c0_conf(cfg ^ R30XX_CONF_AC); 93 size2 = r3k_cache_size(ST0_ISC); 94 write_c0_conf(cfg); 95 return size1 != size2; 96 #else 97 return 0; 98 #endif 99 } 100 101 static inline void set_elf_platform(int cpu, const char *plat) 102 { 103 if (cpu == 0) 104 __elf_platform = plat; 105 } 106 107 /* 108 * Get the FPU Implementation/Revision. 109 */ 110 static inline unsigned long cpu_get_fpu_id(void) 111 { 112 unsigned long tmp, fpu_id; 113 114 tmp = read_c0_status(); 115 __enable_fpu(FPU_AS_IS); 116 fpu_id = read_32bit_cp1_register(CP1_REVISION); 117 write_c0_status(tmp); 118 return fpu_id; 119 } 120 121 /* 122 * Check the CPU has an FPU the official way. 123 */ 124 static inline int __cpu_has_fpu(void) 125 { 126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); 127 } 128 129 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 130 { 131 #ifdef __NEED_VMBITS_PROBE 132 write_c0_entryhi(0x3fffffffffffe000ULL); 133 back_to_back_c0_hazard(); 134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 135 #endif 136 } 137 138 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 139 { 140 switch (isa) { 141 case MIPS_CPU_ISA_M64R2: 142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 143 case MIPS_CPU_ISA_M64R1: 144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 145 case MIPS_CPU_ISA_V: 146 c->isa_level |= MIPS_CPU_ISA_V; 147 case MIPS_CPU_ISA_IV: 148 c->isa_level |= MIPS_CPU_ISA_IV; 149 case MIPS_CPU_ISA_III: 150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 151 break; 152 153 case MIPS_CPU_ISA_M32R2: 154 c->isa_level |= MIPS_CPU_ISA_M32R2; 155 case MIPS_CPU_ISA_M32R1: 156 c->isa_level |= MIPS_CPU_ISA_M32R1; 157 case MIPS_CPU_ISA_II: 158 c->isa_level |= MIPS_CPU_ISA_II; 159 break; 160 } 161 } 162 163 static char unknown_isa[] = KERN_ERR \ 164 "Unsupported ISA type, c0.config0: %d."; 165 166 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 167 { 168 unsigned int config6; 169 /* 170 * Config6 is implementation dependent and it's currently only 171 * used by proAptiv 172 */ 173 if (c->cputype == CPU_PROAPTIV) { 174 config6 = read_c0_config6(); 175 if (enable) 176 /* Enable FTLB */ 177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 178 else 179 /* Disable FTLB */ 180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 181 back_to_back_c0_hazard(); 182 } 183 } 184 185 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 186 { 187 unsigned int config0; 188 int isa; 189 190 config0 = read_c0_config(); 191 192 /* 193 * Look for Standard TLB or Dual VTLB and FTLB 194 */ 195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 196 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 197 c->options |= MIPS_CPU_TLB; 198 199 isa = (config0 & MIPS_CONF_AT) >> 13; 200 switch (isa) { 201 case 0: 202 switch ((config0 & MIPS_CONF_AR) >> 10) { 203 case 0: 204 set_isa(c, MIPS_CPU_ISA_M32R1); 205 break; 206 case 1: 207 set_isa(c, MIPS_CPU_ISA_M32R2); 208 break; 209 default: 210 goto unknown; 211 } 212 break; 213 case 2: 214 switch ((config0 & MIPS_CONF_AR) >> 10) { 215 case 0: 216 set_isa(c, MIPS_CPU_ISA_M64R1); 217 break; 218 case 1: 219 set_isa(c, MIPS_CPU_ISA_M64R2); 220 break; 221 default: 222 goto unknown; 223 } 224 break; 225 default: 226 goto unknown; 227 } 228 229 return config0 & MIPS_CONF_M; 230 231 unknown: 232 panic(unknown_isa, config0); 233 } 234 235 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 236 { 237 unsigned int config1; 238 239 config1 = read_c0_config1(); 240 241 if (config1 & MIPS_CONF1_MD) 242 c->ases |= MIPS_ASE_MDMX; 243 if (config1 & MIPS_CONF1_WR) 244 c->options |= MIPS_CPU_WATCH; 245 if (config1 & MIPS_CONF1_CA) 246 c->ases |= MIPS_ASE_MIPS16; 247 if (config1 & MIPS_CONF1_EP) 248 c->options |= MIPS_CPU_EJTAG; 249 if (config1 & MIPS_CONF1_FP) { 250 c->options |= MIPS_CPU_FPU; 251 c->options |= MIPS_CPU_32FPR; 252 } 253 if (cpu_has_tlb) { 254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 255 c->tlbsizevtlb = c->tlbsize; 256 c->tlbsizeftlbsets = 0; 257 } 258 259 return config1 & MIPS_CONF_M; 260 } 261 262 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 263 { 264 unsigned int config2; 265 266 config2 = read_c0_config2(); 267 268 if (config2 & MIPS_CONF2_SL) 269 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 270 271 return config2 & MIPS_CONF_M; 272 } 273 274 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 275 { 276 unsigned int config3; 277 278 config3 = read_c0_config3(); 279 280 if (config3 & MIPS_CONF3_SM) { 281 c->ases |= MIPS_ASE_SMARTMIPS; 282 c->options |= MIPS_CPU_RIXI; 283 } 284 if (config3 & MIPS_CONF3_RXI) 285 c->options |= MIPS_CPU_RIXI; 286 if (config3 & MIPS_CONF3_DSP) 287 c->ases |= MIPS_ASE_DSP; 288 if (config3 & MIPS_CONF3_DSP2P) 289 c->ases |= MIPS_ASE_DSP2P; 290 if (config3 & MIPS_CONF3_VINT) 291 c->options |= MIPS_CPU_VINT; 292 if (config3 & MIPS_CONF3_VEIC) 293 c->options |= MIPS_CPU_VEIC; 294 if (config3 & MIPS_CONF3_MT) 295 c->ases |= MIPS_ASE_MIPSMT; 296 if (config3 & MIPS_CONF3_ULRI) 297 c->options |= MIPS_CPU_ULRI; 298 if (config3 & MIPS_CONF3_ISA) 299 c->options |= MIPS_CPU_MICROMIPS; 300 if (config3 & MIPS_CONF3_VZ) 301 c->ases |= MIPS_ASE_VZ; 302 if (config3 & MIPS_CONF3_SC) 303 c->options |= MIPS_CPU_SEGMENTS; 304 305 return config3 & MIPS_CONF_M; 306 } 307 308 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 309 { 310 unsigned int config4; 311 unsigned int newcf4; 312 unsigned int mmuextdef; 313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 314 315 config4 = read_c0_config4(); 316 317 if (cpu_has_tlb) { 318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 319 c->options |= MIPS_CPU_TLBINV; 320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 321 switch (mmuextdef) { 322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 324 c->tlbsizevtlb = c->tlbsize; 325 break; 326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 327 c->tlbsizevtlb += 328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 330 c->tlbsize = c->tlbsizevtlb; 331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 332 /* fall through */ 333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 334 newcf4 = (config4 & ~ftlb_page) | 335 (page_size_ftlb(mmuextdef) << 336 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 337 write_c0_config4(newcf4); 338 back_to_back_c0_hazard(); 339 config4 = read_c0_config4(); 340 if (config4 != newcf4) { 341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 342 PAGE_SIZE, config4); 343 /* Switch FTLB off */ 344 set_ftlb_enable(c, 0); 345 break; 346 } 347 c->tlbsizeftlbsets = 1 << 348 ((config4 & MIPS_CONF4_FTLBSETS) >> 349 MIPS_CONF4_FTLBSETS_SHIFT); 350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 353 break; 354 } 355 } 356 357 c->kscratch_mask = (config4 >> 16) & 0xff; 358 359 return config4 & MIPS_CONF_M; 360 } 361 362 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 363 { 364 unsigned int config5; 365 366 config5 = read_c0_config5(); 367 config5 &= ~MIPS_CONF5_UFR; 368 write_c0_config5(config5); 369 370 return config5 & MIPS_CONF_M; 371 } 372 373 static void decode_configs(struct cpuinfo_mips *c) 374 { 375 int ok; 376 377 /* MIPS32 or MIPS64 compliant CPU. */ 378 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 380 381 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 382 383 /* Enable FTLB if present */ 384 set_ftlb_enable(c, 1); 385 386 ok = decode_config0(c); /* Read Config registers. */ 387 BUG_ON(!ok); /* Arch spec violation! */ 388 if (ok) 389 ok = decode_config1(c); 390 if (ok) 391 ok = decode_config2(c); 392 if (ok) 393 ok = decode_config3(c); 394 if (ok) 395 ok = decode_config4(c); 396 if (ok) 397 ok = decode_config5(c); 398 399 mips_probe_watch_registers(c); 400 401 if (cpu_has_mips_r2) 402 c->core = read_c0_ebase() & 0x3ff; 403 } 404 405 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 406 | MIPS_CPU_COUNTER) 407 408 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 409 { 410 switch (c->processor_id & PRID_IMP_MASK) { 411 case PRID_IMP_R2000: 412 c->cputype = CPU_R2000; 413 __cpu_name[cpu] = "R2000"; 414 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 415 MIPS_CPU_NOFPUEX; 416 if (__cpu_has_fpu()) 417 c->options |= MIPS_CPU_FPU; 418 c->tlbsize = 64; 419 break; 420 case PRID_IMP_R3000: 421 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 422 if (cpu_has_confreg()) { 423 c->cputype = CPU_R3081E; 424 __cpu_name[cpu] = "R3081"; 425 } else { 426 c->cputype = CPU_R3000A; 427 __cpu_name[cpu] = "R3000A"; 428 } 429 } else { 430 c->cputype = CPU_R3000; 431 __cpu_name[cpu] = "R3000"; 432 } 433 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 434 MIPS_CPU_NOFPUEX; 435 if (__cpu_has_fpu()) 436 c->options |= MIPS_CPU_FPU; 437 c->tlbsize = 64; 438 break; 439 case PRID_IMP_R4000: 440 if (read_c0_config() & CONF_SC) { 441 if ((c->processor_id & PRID_REV_MASK) >= 442 PRID_REV_R4400) { 443 c->cputype = CPU_R4400PC; 444 __cpu_name[cpu] = "R4400PC"; 445 } else { 446 c->cputype = CPU_R4000PC; 447 __cpu_name[cpu] = "R4000PC"; 448 } 449 } else { 450 int cca = read_c0_config() & CONF_CM_CMASK; 451 int mc; 452 453 /* 454 * SC and MC versions can't be reliably told apart, 455 * but only the latter support coherent caching 456 * modes so assume the firmware has set the KSEG0 457 * coherency attribute reasonably (if uncached, we 458 * assume SC). 459 */ 460 switch (cca) { 461 case CONF_CM_CACHABLE_CE: 462 case CONF_CM_CACHABLE_COW: 463 case CONF_CM_CACHABLE_CUW: 464 mc = 1; 465 break; 466 default: 467 mc = 0; 468 break; 469 } 470 if ((c->processor_id & PRID_REV_MASK) >= 471 PRID_REV_R4400) { 472 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 473 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 474 } else { 475 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 476 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 477 } 478 } 479 480 set_isa(c, MIPS_CPU_ISA_III); 481 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 482 MIPS_CPU_WATCH | MIPS_CPU_VCE | 483 MIPS_CPU_LLSC; 484 c->tlbsize = 48; 485 break; 486 case PRID_IMP_VR41XX: 487 set_isa(c, MIPS_CPU_ISA_III); 488 c->options = R4K_OPTS; 489 c->tlbsize = 32; 490 switch (c->processor_id & 0xf0) { 491 case PRID_REV_VR4111: 492 c->cputype = CPU_VR4111; 493 __cpu_name[cpu] = "NEC VR4111"; 494 break; 495 case PRID_REV_VR4121: 496 c->cputype = CPU_VR4121; 497 __cpu_name[cpu] = "NEC VR4121"; 498 break; 499 case PRID_REV_VR4122: 500 if ((c->processor_id & 0xf) < 0x3) { 501 c->cputype = CPU_VR4122; 502 __cpu_name[cpu] = "NEC VR4122"; 503 } else { 504 c->cputype = CPU_VR4181A; 505 __cpu_name[cpu] = "NEC VR4181A"; 506 } 507 break; 508 case PRID_REV_VR4130: 509 if ((c->processor_id & 0xf) < 0x4) { 510 c->cputype = CPU_VR4131; 511 __cpu_name[cpu] = "NEC VR4131"; 512 } else { 513 c->cputype = CPU_VR4133; 514 c->options |= MIPS_CPU_LLSC; 515 __cpu_name[cpu] = "NEC VR4133"; 516 } 517 break; 518 default: 519 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 520 c->cputype = CPU_VR41XX; 521 __cpu_name[cpu] = "NEC Vr41xx"; 522 break; 523 } 524 break; 525 case PRID_IMP_R4300: 526 c->cputype = CPU_R4300; 527 __cpu_name[cpu] = "R4300"; 528 set_isa(c, MIPS_CPU_ISA_III); 529 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 530 MIPS_CPU_LLSC; 531 c->tlbsize = 32; 532 break; 533 case PRID_IMP_R4600: 534 c->cputype = CPU_R4600; 535 __cpu_name[cpu] = "R4600"; 536 set_isa(c, MIPS_CPU_ISA_III); 537 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 538 MIPS_CPU_LLSC; 539 c->tlbsize = 48; 540 break; 541 #if 0 542 case PRID_IMP_R4650: 543 /* 544 * This processor doesn't have an MMU, so it's not 545 * "real easy" to run Linux on it. It is left purely 546 * for documentation. Commented out because it shares 547 * it's c0_prid id number with the TX3900. 548 */ 549 c->cputype = CPU_R4650; 550 __cpu_name[cpu] = "R4650"; 551 set_isa(c, MIPS_CPU_ISA_III); 552 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 553 c->tlbsize = 48; 554 break; 555 #endif 556 case PRID_IMP_TX39: 557 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 558 559 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 560 c->cputype = CPU_TX3927; 561 __cpu_name[cpu] = "TX3927"; 562 c->tlbsize = 64; 563 } else { 564 switch (c->processor_id & PRID_REV_MASK) { 565 case PRID_REV_TX3912: 566 c->cputype = CPU_TX3912; 567 __cpu_name[cpu] = "TX3912"; 568 c->tlbsize = 32; 569 break; 570 case PRID_REV_TX3922: 571 c->cputype = CPU_TX3922; 572 __cpu_name[cpu] = "TX3922"; 573 c->tlbsize = 64; 574 break; 575 } 576 } 577 break; 578 case PRID_IMP_R4700: 579 c->cputype = CPU_R4700; 580 __cpu_name[cpu] = "R4700"; 581 set_isa(c, MIPS_CPU_ISA_III); 582 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 583 MIPS_CPU_LLSC; 584 c->tlbsize = 48; 585 break; 586 case PRID_IMP_TX49: 587 c->cputype = CPU_TX49XX; 588 __cpu_name[cpu] = "R49XX"; 589 set_isa(c, MIPS_CPU_ISA_III); 590 c->options = R4K_OPTS | MIPS_CPU_LLSC; 591 if (!(c->processor_id & 0x08)) 592 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 593 c->tlbsize = 48; 594 break; 595 case PRID_IMP_R5000: 596 c->cputype = CPU_R5000; 597 __cpu_name[cpu] = "R5000"; 598 set_isa(c, MIPS_CPU_ISA_IV); 599 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 600 MIPS_CPU_LLSC; 601 c->tlbsize = 48; 602 break; 603 case PRID_IMP_R5432: 604 c->cputype = CPU_R5432; 605 __cpu_name[cpu] = "R5432"; 606 set_isa(c, MIPS_CPU_ISA_IV); 607 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 608 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 609 c->tlbsize = 48; 610 break; 611 case PRID_IMP_R5500: 612 c->cputype = CPU_R5500; 613 __cpu_name[cpu] = "R5500"; 614 set_isa(c, MIPS_CPU_ISA_IV); 615 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 616 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 617 c->tlbsize = 48; 618 break; 619 case PRID_IMP_NEVADA: 620 c->cputype = CPU_NEVADA; 621 __cpu_name[cpu] = "Nevada"; 622 set_isa(c, MIPS_CPU_ISA_IV); 623 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 624 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 625 c->tlbsize = 48; 626 break; 627 case PRID_IMP_R6000: 628 c->cputype = CPU_R6000; 629 __cpu_name[cpu] = "R6000"; 630 set_isa(c, MIPS_CPU_ISA_II); 631 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 632 MIPS_CPU_LLSC; 633 c->tlbsize = 32; 634 break; 635 case PRID_IMP_R6000A: 636 c->cputype = CPU_R6000A; 637 __cpu_name[cpu] = "R6000A"; 638 set_isa(c, MIPS_CPU_ISA_II); 639 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 640 MIPS_CPU_LLSC; 641 c->tlbsize = 32; 642 break; 643 case PRID_IMP_RM7000: 644 c->cputype = CPU_RM7000; 645 __cpu_name[cpu] = "RM7000"; 646 set_isa(c, MIPS_CPU_ISA_IV); 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 648 MIPS_CPU_LLSC; 649 /* 650 * Undocumented RM7000: Bit 29 in the info register of 651 * the RM7000 v2.0 indicates if the TLB has 48 or 64 652 * entries. 653 * 654 * 29 1 => 64 entry JTLB 655 * 0 => 48 entry JTLB 656 */ 657 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 658 break; 659 case PRID_IMP_RM9000: 660 c->cputype = CPU_RM9000; 661 __cpu_name[cpu] = "RM9000"; 662 set_isa(c, MIPS_CPU_ISA_IV); 663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 664 MIPS_CPU_LLSC; 665 /* 666 * Bit 29 in the info register of the RM9000 667 * indicates if the TLB has 48 or 64 entries. 668 * 669 * 29 1 => 64 entry JTLB 670 * 0 => 48 entry JTLB 671 */ 672 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 673 break; 674 case PRID_IMP_R8000: 675 c->cputype = CPU_R8000; 676 __cpu_name[cpu] = "RM8000"; 677 set_isa(c, MIPS_CPU_ISA_IV); 678 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 679 MIPS_CPU_FPU | MIPS_CPU_32FPR | 680 MIPS_CPU_LLSC; 681 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 682 break; 683 case PRID_IMP_R10000: 684 c->cputype = CPU_R10000; 685 __cpu_name[cpu] = "R10000"; 686 set_isa(c, MIPS_CPU_ISA_IV); 687 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 688 MIPS_CPU_FPU | MIPS_CPU_32FPR | 689 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 690 MIPS_CPU_LLSC; 691 c->tlbsize = 64; 692 break; 693 case PRID_IMP_R12000: 694 c->cputype = CPU_R12000; 695 __cpu_name[cpu] = "R12000"; 696 set_isa(c, MIPS_CPU_ISA_IV); 697 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 698 MIPS_CPU_FPU | MIPS_CPU_32FPR | 699 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 700 MIPS_CPU_LLSC; 701 c->tlbsize = 64; 702 break; 703 case PRID_IMP_R14000: 704 c->cputype = CPU_R14000; 705 __cpu_name[cpu] = "R14000"; 706 set_isa(c, MIPS_CPU_ISA_IV); 707 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 708 MIPS_CPU_FPU | MIPS_CPU_32FPR | 709 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 710 MIPS_CPU_LLSC; 711 c->tlbsize = 64; 712 break; 713 case PRID_IMP_LOONGSON2: 714 c->cputype = CPU_LOONGSON2; 715 __cpu_name[cpu] = "ICT Loongson-2"; 716 717 switch (c->processor_id & PRID_REV_MASK) { 718 case PRID_REV_LOONGSON2E: 719 set_elf_platform(cpu, "loongson2e"); 720 break; 721 case PRID_REV_LOONGSON2F: 722 set_elf_platform(cpu, "loongson2f"); 723 break; 724 } 725 726 set_isa(c, MIPS_CPU_ISA_III); 727 c->options = R4K_OPTS | 728 MIPS_CPU_FPU | MIPS_CPU_LLSC | 729 MIPS_CPU_32FPR; 730 c->tlbsize = 64; 731 break; 732 case PRID_IMP_LOONGSON1: 733 decode_configs(c); 734 735 c->cputype = CPU_LOONGSON1; 736 737 switch (c->processor_id & PRID_REV_MASK) { 738 case PRID_REV_LOONGSON1B: 739 __cpu_name[cpu] = "Loongson 1B"; 740 break; 741 } 742 743 break; 744 } 745 } 746 747 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 748 { 749 switch (c->processor_id & PRID_IMP_MASK) { 750 case PRID_IMP_4KC: 751 c->cputype = CPU_4KC; 752 __cpu_name[cpu] = "MIPS 4Kc"; 753 break; 754 case PRID_IMP_4KEC: 755 case PRID_IMP_4KECR2: 756 c->cputype = CPU_4KEC; 757 __cpu_name[cpu] = "MIPS 4KEc"; 758 break; 759 case PRID_IMP_4KSC: 760 case PRID_IMP_4KSD: 761 c->cputype = CPU_4KSC; 762 __cpu_name[cpu] = "MIPS 4KSc"; 763 break; 764 case PRID_IMP_5KC: 765 c->cputype = CPU_5KC; 766 __cpu_name[cpu] = "MIPS 5Kc"; 767 break; 768 case PRID_IMP_5KE: 769 c->cputype = CPU_5KE; 770 __cpu_name[cpu] = "MIPS 5KE"; 771 break; 772 case PRID_IMP_20KC: 773 c->cputype = CPU_20KC; 774 __cpu_name[cpu] = "MIPS 20Kc"; 775 break; 776 case PRID_IMP_24K: 777 c->cputype = CPU_24K; 778 __cpu_name[cpu] = "MIPS 24Kc"; 779 break; 780 case PRID_IMP_24KE: 781 c->cputype = CPU_24K; 782 __cpu_name[cpu] = "MIPS 24KEc"; 783 break; 784 case PRID_IMP_25KF: 785 c->cputype = CPU_25KF; 786 __cpu_name[cpu] = "MIPS 25Kc"; 787 break; 788 case PRID_IMP_34K: 789 c->cputype = CPU_34K; 790 __cpu_name[cpu] = "MIPS 34Kc"; 791 break; 792 case PRID_IMP_74K: 793 c->cputype = CPU_74K; 794 __cpu_name[cpu] = "MIPS 74Kc"; 795 break; 796 case PRID_IMP_M14KC: 797 c->cputype = CPU_M14KC; 798 __cpu_name[cpu] = "MIPS M14Kc"; 799 break; 800 case PRID_IMP_M14KEC: 801 c->cputype = CPU_M14KEC; 802 __cpu_name[cpu] = "MIPS M14KEc"; 803 break; 804 case PRID_IMP_1004K: 805 c->cputype = CPU_1004K; 806 __cpu_name[cpu] = "MIPS 1004Kc"; 807 break; 808 case PRID_IMP_1074K: 809 c->cputype = CPU_74K; 810 __cpu_name[cpu] = "MIPS 1074Kc"; 811 break; 812 case PRID_IMP_INTERAPTIV_UP: 813 c->cputype = CPU_INTERAPTIV; 814 __cpu_name[cpu] = "MIPS interAptiv"; 815 break; 816 case PRID_IMP_INTERAPTIV_MP: 817 c->cputype = CPU_INTERAPTIV; 818 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 819 break; 820 case PRID_IMP_PROAPTIV_UP: 821 c->cputype = CPU_PROAPTIV; 822 __cpu_name[cpu] = "MIPS proAptiv"; 823 break; 824 case PRID_IMP_PROAPTIV_MP: 825 c->cputype = CPU_PROAPTIV; 826 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 827 break; 828 } 829 830 decode_configs(c); 831 832 spram_config(); 833 } 834 835 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 836 { 837 decode_configs(c); 838 switch (c->processor_id & PRID_IMP_MASK) { 839 case PRID_IMP_AU1_REV1: 840 case PRID_IMP_AU1_REV2: 841 c->cputype = CPU_ALCHEMY; 842 switch ((c->processor_id >> 24) & 0xff) { 843 case 0: 844 __cpu_name[cpu] = "Au1000"; 845 break; 846 case 1: 847 __cpu_name[cpu] = "Au1500"; 848 break; 849 case 2: 850 __cpu_name[cpu] = "Au1100"; 851 break; 852 case 3: 853 __cpu_name[cpu] = "Au1550"; 854 break; 855 case 4: 856 __cpu_name[cpu] = "Au1200"; 857 if ((c->processor_id & PRID_REV_MASK) == 2) 858 __cpu_name[cpu] = "Au1250"; 859 break; 860 case 5: 861 __cpu_name[cpu] = "Au1210"; 862 break; 863 default: 864 __cpu_name[cpu] = "Au1xxx"; 865 break; 866 } 867 break; 868 } 869 } 870 871 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 872 { 873 decode_configs(c); 874 875 switch (c->processor_id & PRID_IMP_MASK) { 876 case PRID_IMP_SB1: 877 c->cputype = CPU_SB1; 878 __cpu_name[cpu] = "SiByte SB1"; 879 /* FPU in pass1 is known to have issues. */ 880 if ((c->processor_id & PRID_REV_MASK) < 0x02) 881 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 882 break; 883 case PRID_IMP_SB1A: 884 c->cputype = CPU_SB1A; 885 __cpu_name[cpu] = "SiByte SB1A"; 886 break; 887 } 888 } 889 890 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 891 { 892 decode_configs(c); 893 switch (c->processor_id & PRID_IMP_MASK) { 894 case PRID_IMP_SR71000: 895 c->cputype = CPU_SR71000; 896 __cpu_name[cpu] = "Sandcraft SR71000"; 897 c->scache.ways = 8; 898 c->tlbsize = 64; 899 break; 900 } 901 } 902 903 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 904 { 905 decode_configs(c); 906 switch (c->processor_id & PRID_IMP_MASK) { 907 case PRID_IMP_PR4450: 908 c->cputype = CPU_PR4450; 909 __cpu_name[cpu] = "Philips PR4450"; 910 set_isa(c, MIPS_CPU_ISA_M32R1); 911 break; 912 } 913 } 914 915 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 916 { 917 decode_configs(c); 918 switch (c->processor_id & PRID_IMP_MASK) { 919 case PRID_IMP_BMIPS32_REV4: 920 case PRID_IMP_BMIPS32_REV8: 921 c->cputype = CPU_BMIPS32; 922 __cpu_name[cpu] = "Broadcom BMIPS32"; 923 set_elf_platform(cpu, "bmips32"); 924 break; 925 case PRID_IMP_BMIPS3300: 926 case PRID_IMP_BMIPS3300_ALT: 927 case PRID_IMP_BMIPS3300_BUG: 928 c->cputype = CPU_BMIPS3300; 929 __cpu_name[cpu] = "Broadcom BMIPS3300"; 930 set_elf_platform(cpu, "bmips3300"); 931 break; 932 case PRID_IMP_BMIPS43XX: { 933 int rev = c->processor_id & PRID_REV_MASK; 934 935 if (rev >= PRID_REV_BMIPS4380_LO && 936 rev <= PRID_REV_BMIPS4380_HI) { 937 c->cputype = CPU_BMIPS4380; 938 __cpu_name[cpu] = "Broadcom BMIPS4380"; 939 set_elf_platform(cpu, "bmips4380"); 940 } else { 941 c->cputype = CPU_BMIPS4350; 942 __cpu_name[cpu] = "Broadcom BMIPS4350"; 943 set_elf_platform(cpu, "bmips4350"); 944 } 945 break; 946 } 947 case PRID_IMP_BMIPS5000: 948 c->cputype = CPU_BMIPS5000; 949 __cpu_name[cpu] = "Broadcom BMIPS5000"; 950 set_elf_platform(cpu, "bmips5000"); 951 c->options |= MIPS_CPU_ULRI; 952 break; 953 } 954 } 955 956 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 957 { 958 decode_configs(c); 959 switch (c->processor_id & PRID_IMP_MASK) { 960 case PRID_IMP_CAVIUM_CN38XX: 961 case PRID_IMP_CAVIUM_CN31XX: 962 case PRID_IMP_CAVIUM_CN30XX: 963 c->cputype = CPU_CAVIUM_OCTEON; 964 __cpu_name[cpu] = "Cavium Octeon"; 965 goto platform; 966 case PRID_IMP_CAVIUM_CN58XX: 967 case PRID_IMP_CAVIUM_CN56XX: 968 case PRID_IMP_CAVIUM_CN50XX: 969 case PRID_IMP_CAVIUM_CN52XX: 970 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 971 __cpu_name[cpu] = "Cavium Octeon+"; 972 platform: 973 set_elf_platform(cpu, "octeon"); 974 break; 975 case PRID_IMP_CAVIUM_CN61XX: 976 case PRID_IMP_CAVIUM_CN63XX: 977 case PRID_IMP_CAVIUM_CN66XX: 978 case PRID_IMP_CAVIUM_CN68XX: 979 case PRID_IMP_CAVIUM_CNF71XX: 980 c->cputype = CPU_CAVIUM_OCTEON2; 981 __cpu_name[cpu] = "Cavium Octeon II"; 982 set_elf_platform(cpu, "octeon2"); 983 break; 984 case PRID_IMP_CAVIUM_CN70XX: 985 case PRID_IMP_CAVIUM_CN78XX: 986 c->cputype = CPU_CAVIUM_OCTEON3; 987 __cpu_name[cpu] = "Cavium Octeon III"; 988 set_elf_platform(cpu, "octeon3"); 989 break; 990 default: 991 printk(KERN_INFO "Unknown Octeon chip!\n"); 992 c->cputype = CPU_UNKNOWN; 993 break; 994 } 995 } 996 997 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 998 { 999 decode_configs(c); 1000 /* JZRISC does not implement the CP0 counter. */ 1001 c->options &= ~MIPS_CPU_COUNTER; 1002 switch (c->processor_id & PRID_IMP_MASK) { 1003 case PRID_IMP_JZRISC: 1004 c->cputype = CPU_JZRISC; 1005 __cpu_name[cpu] = "Ingenic JZRISC"; 1006 break; 1007 default: 1008 panic("Unknown Ingenic Processor ID!"); 1009 break; 1010 } 1011 } 1012 1013 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1014 { 1015 decode_configs(c); 1016 1017 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1018 c->cputype = CPU_ALCHEMY; 1019 __cpu_name[cpu] = "Au1300"; 1020 /* following stuff is not for Alchemy */ 1021 return; 1022 } 1023 1024 c->options = (MIPS_CPU_TLB | 1025 MIPS_CPU_4KEX | 1026 MIPS_CPU_COUNTER | 1027 MIPS_CPU_DIVEC | 1028 MIPS_CPU_WATCH | 1029 MIPS_CPU_EJTAG | 1030 MIPS_CPU_LLSC); 1031 1032 switch (c->processor_id & PRID_IMP_MASK) { 1033 case PRID_IMP_NETLOGIC_XLP2XX: 1034 case PRID_IMP_NETLOGIC_XLP9XX: 1035 c->cputype = CPU_XLP; 1036 __cpu_name[cpu] = "Broadcom XLPII"; 1037 break; 1038 1039 case PRID_IMP_NETLOGIC_XLP8XX: 1040 case PRID_IMP_NETLOGIC_XLP3XX: 1041 c->cputype = CPU_XLP; 1042 __cpu_name[cpu] = "Netlogic XLP"; 1043 break; 1044 1045 case PRID_IMP_NETLOGIC_XLR732: 1046 case PRID_IMP_NETLOGIC_XLR716: 1047 case PRID_IMP_NETLOGIC_XLR532: 1048 case PRID_IMP_NETLOGIC_XLR308: 1049 case PRID_IMP_NETLOGIC_XLR532C: 1050 case PRID_IMP_NETLOGIC_XLR516C: 1051 case PRID_IMP_NETLOGIC_XLR508C: 1052 case PRID_IMP_NETLOGIC_XLR308C: 1053 c->cputype = CPU_XLR; 1054 __cpu_name[cpu] = "Netlogic XLR"; 1055 break; 1056 1057 case PRID_IMP_NETLOGIC_XLS608: 1058 case PRID_IMP_NETLOGIC_XLS408: 1059 case PRID_IMP_NETLOGIC_XLS404: 1060 case PRID_IMP_NETLOGIC_XLS208: 1061 case PRID_IMP_NETLOGIC_XLS204: 1062 case PRID_IMP_NETLOGIC_XLS108: 1063 case PRID_IMP_NETLOGIC_XLS104: 1064 case PRID_IMP_NETLOGIC_XLS616B: 1065 case PRID_IMP_NETLOGIC_XLS608B: 1066 case PRID_IMP_NETLOGIC_XLS416B: 1067 case PRID_IMP_NETLOGIC_XLS412B: 1068 case PRID_IMP_NETLOGIC_XLS408B: 1069 case PRID_IMP_NETLOGIC_XLS404B: 1070 c->cputype = CPU_XLR; 1071 __cpu_name[cpu] = "Netlogic XLS"; 1072 break; 1073 1074 default: 1075 pr_info("Unknown Netlogic chip id [%02x]!\n", 1076 c->processor_id); 1077 c->cputype = CPU_XLR; 1078 break; 1079 } 1080 1081 if (c->cputype == CPU_XLP) { 1082 set_isa(c, MIPS_CPU_ISA_M64R2); 1083 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1084 /* This will be updated again after all threads are woken up */ 1085 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1086 } else { 1087 set_isa(c, MIPS_CPU_ISA_M64R1); 1088 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1089 } 1090 c->kscratch_mask = 0xf; 1091 } 1092 1093 #ifdef CONFIG_64BIT 1094 /* For use by uaccess.h */ 1095 u64 __ua_limit; 1096 EXPORT_SYMBOL(__ua_limit); 1097 #endif 1098 1099 const char *__cpu_name[NR_CPUS]; 1100 const char *__elf_platform; 1101 1102 void cpu_probe(void) 1103 { 1104 struct cpuinfo_mips *c = ¤t_cpu_data; 1105 unsigned int cpu = smp_processor_id(); 1106 1107 c->processor_id = PRID_IMP_UNKNOWN; 1108 c->fpu_id = FPIR_IMP_NONE; 1109 c->cputype = CPU_UNKNOWN; 1110 1111 c->processor_id = read_c0_prid(); 1112 switch (c->processor_id & PRID_COMP_MASK) { 1113 case PRID_COMP_LEGACY: 1114 cpu_probe_legacy(c, cpu); 1115 break; 1116 case PRID_COMP_MIPS: 1117 cpu_probe_mips(c, cpu); 1118 break; 1119 case PRID_COMP_ALCHEMY: 1120 cpu_probe_alchemy(c, cpu); 1121 break; 1122 case PRID_COMP_SIBYTE: 1123 cpu_probe_sibyte(c, cpu); 1124 break; 1125 case PRID_COMP_BROADCOM: 1126 cpu_probe_broadcom(c, cpu); 1127 break; 1128 case PRID_COMP_SANDCRAFT: 1129 cpu_probe_sandcraft(c, cpu); 1130 break; 1131 case PRID_COMP_NXP: 1132 cpu_probe_nxp(c, cpu); 1133 break; 1134 case PRID_COMP_CAVIUM: 1135 cpu_probe_cavium(c, cpu); 1136 break; 1137 case PRID_COMP_INGENIC: 1138 cpu_probe_ingenic(c, cpu); 1139 break; 1140 case PRID_COMP_NETLOGIC: 1141 cpu_probe_netlogic(c, cpu); 1142 break; 1143 } 1144 1145 BUG_ON(!__cpu_name[cpu]); 1146 BUG_ON(c->cputype == CPU_UNKNOWN); 1147 1148 /* 1149 * Platform code can force the cpu type to optimize code 1150 * generation. In that case be sure the cpu type is correctly 1151 * manually setup otherwise it could trigger some nasty bugs. 1152 */ 1153 BUG_ON(current_cpu_type() != c->cputype); 1154 1155 if (mips_fpu_disabled) 1156 c->options &= ~MIPS_CPU_FPU; 1157 1158 if (mips_dsp_disabled) 1159 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1160 1161 if (c->options & MIPS_CPU_FPU) { 1162 c->fpu_id = cpu_get_fpu_id(); 1163 1164 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1165 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1166 if (c->fpu_id & MIPS_FPIR_3D) 1167 c->ases |= MIPS_ASE_MIPS3D; 1168 } 1169 } 1170 1171 if (cpu_has_mips_r2) { 1172 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1173 /* R2 has Performance Counter Interrupt indicator */ 1174 c->options |= MIPS_CPU_PCI; 1175 } 1176 else 1177 c->srsets = 1; 1178 1179 cpu_probe_vmbits(c); 1180 1181 #ifdef CONFIG_64BIT 1182 if (cpu == 0) 1183 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1184 #endif 1185 } 1186 1187 void cpu_report(void) 1188 { 1189 struct cpuinfo_mips *c = ¤t_cpu_data; 1190 1191 pr_info("CPU%d revision is: %08x (%s)\n", 1192 smp_processor_id(), c->processor_id, cpu_name_string()); 1193 if (c->options & MIPS_CPU_FPU) 1194 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1195 } 1196