1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/fpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/spram.h> 28 #include <asm/uaccess.h> 29 30 /* 31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 32 * the implementation of the "wait" feature differs between CPU families. This 33 * points to the function that implements CPU specific wait. 34 * The wait instruction stops the pipeline and reduces the power consumption of 35 * the CPU very much. 36 */ 37 void (*cpu_wait)(void); 38 EXPORT_SYMBOL(cpu_wait); 39 40 static void r3081_wait(void) 41 { 42 unsigned long cfg = read_c0_conf(); 43 write_c0_conf(cfg | R30XX_CONF_HALT); 44 } 45 46 static void r39xx_wait(void) 47 { 48 local_irq_disable(); 49 if (!need_resched()) 50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 51 local_irq_enable(); 52 } 53 54 extern void r4k_wait(void); 55 56 /* 57 * This variant is preferable as it allows testing need_resched and going to 58 * sleep depending on the outcome atomically. Unfortunately the "It is 59 * implementation-dependent whether the pipeline restarts when a non-enabled 60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 61 * using this version a gamble. 62 */ 63 void r4k_wait_irqoff(void) 64 { 65 local_irq_disable(); 66 if (!need_resched()) 67 __asm__(" .set push \n" 68 " .set mips3 \n" 69 " wait \n" 70 " .set pop \n"); 71 local_irq_enable(); 72 __asm__(" .globl __pastwait \n" 73 "__pastwait: \n"); 74 } 75 76 /* 77 * The RM7000 variant has to handle erratum 38. The workaround is to not 78 * have any pending stores when the WAIT instruction is executed. 79 */ 80 static void rm7k_wait_irqoff(void) 81 { 82 local_irq_disable(); 83 if (!need_resched()) 84 __asm__( 85 " .set push \n" 86 " .set mips3 \n" 87 " .set noat \n" 88 " mfc0 $1, $12 \n" 89 " sync \n" 90 " mtc0 $1, $12 # stalls until W stage \n" 91 " wait \n" 92 " mtc0 $1, $12 # stalls until W stage \n" 93 " .set pop \n"); 94 local_irq_enable(); 95 } 96 97 /* 98 * The Au1xxx wait is available only if using 32khz counter or 99 * external timer source, but specifically not CP0 Counter. 100 * alchemy/common/time.c may override cpu_wait! 101 */ 102 static void au1k_wait(void) 103 { 104 __asm__(" .set mips3 \n" 105 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 32(%0) \n" 107 " sync \n" 108 " nop \n" 109 " wait \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " nop \n" 114 " .set mips0 \n" 115 : : "r" (au1k_wait)); 116 } 117 118 static int __initdata nowait; 119 120 static int __init wait_disable(char *s) 121 { 122 nowait = 1; 123 124 return 1; 125 } 126 127 __setup("nowait", wait_disable); 128 129 static int __cpuinitdata mips_fpu_disabled; 130 131 static int __init fpu_disable(char *s) 132 { 133 cpu_data[0].options &= ~MIPS_CPU_FPU; 134 mips_fpu_disabled = 1; 135 136 return 1; 137 } 138 139 __setup("nofpu", fpu_disable); 140 141 int __cpuinitdata mips_dsp_disabled; 142 143 static int __init dsp_disable(char *s) 144 { 145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 146 mips_dsp_disabled = 1; 147 148 return 1; 149 } 150 151 __setup("nodsp", dsp_disable); 152 153 void __init check_wait(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 if (nowait) { 158 printk("Wait instruction disabled.\n"); 159 return; 160 } 161 162 switch (c->cputype) { 163 case CPU_R3081: 164 case CPU_R3081E: 165 cpu_wait = r3081_wait; 166 break; 167 case CPU_TX3927: 168 cpu_wait = r39xx_wait; 169 break; 170 case CPU_R4200: 171 /* case CPU_R4300: */ 172 case CPU_R4600: 173 case CPU_R4640: 174 case CPU_R4650: 175 case CPU_R4700: 176 case CPU_R5000: 177 case CPU_R5500: 178 case CPU_NEVADA: 179 case CPU_4KC: 180 case CPU_4KEC: 181 case CPU_4KSC: 182 case CPU_5KC: 183 case CPU_25KF: 184 case CPU_PR4450: 185 case CPU_BMIPS3300: 186 case CPU_BMIPS4350: 187 case CPU_BMIPS4380: 188 case CPU_BMIPS5000: 189 case CPU_CAVIUM_OCTEON: 190 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON2: 192 case CPU_JZRISC: 193 case CPU_LOONGSON1: 194 case CPU_XLR: 195 case CPU_XLP: 196 cpu_wait = r4k_wait; 197 break; 198 199 case CPU_RM7000: 200 cpu_wait = rm7k_wait_irqoff; 201 break; 202 203 case CPU_M14KC: 204 case CPU_M14KEC: 205 case CPU_24K: 206 case CPU_34K: 207 case CPU_1004K: 208 cpu_wait = r4k_wait; 209 if (read_c0_config7() & MIPS_CONF7_WII) 210 cpu_wait = r4k_wait_irqoff; 211 break; 212 213 case CPU_74K: 214 cpu_wait = r4k_wait; 215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 216 cpu_wait = r4k_wait_irqoff; 217 break; 218 219 case CPU_TX49XX: 220 cpu_wait = r4k_wait_irqoff; 221 break; 222 case CPU_ALCHEMY: 223 cpu_wait = au1k_wait; 224 break; 225 case CPU_20KC: 226 /* 227 * WAIT on Rev1.0 has E1, E2, E3 and E16. 228 * WAIT on Rev2.0 and Rev3.0 has E16. 229 * Rev3.1 WAIT is nop, why bother 230 */ 231 if ((c->processor_id & 0xff) <= 0x64) 232 break; 233 234 /* 235 * Another rev is incremeting c0_count at a reduced clock 236 * rate while in WAIT mode. So we basically have the choice 237 * between using the cp0 timer as clocksource or avoiding 238 * the WAIT instruction. Until more details are known, 239 * disable the use of WAIT for 20Kc entirely. 240 cpu_wait = r4k_wait; 241 */ 242 break; 243 case CPU_RM9000: 244 if ((c->processor_id & 0x00ff) >= 0x40) 245 cpu_wait = r4k_wait; 246 break; 247 default: 248 break; 249 } 250 } 251 252 static inline void check_errata(void) 253 { 254 struct cpuinfo_mips *c = ¤t_cpu_data; 255 256 switch (c->cputype) { 257 case CPU_34K: 258 /* 259 * Erratum "RPS May Cause Incorrect Instruction Execution" 260 * This code only handles VPE0, any SMP/SMTC/RTOS code 261 * making use of VPE1 will be responsable for that VPE. 262 */ 263 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 265 break; 266 default: 267 break; 268 } 269 } 270 271 void __init check_bugs32(void) 272 { 273 check_errata(); 274 } 275 276 /* 277 * Probe whether cpu has config register by trying to play with 278 * alternate cache bit and see whether it matters. 279 * It's used by cpu_probe to distinguish between R3000A and R3081. 280 */ 281 static inline int cpu_has_confreg(void) 282 { 283 #ifdef CONFIG_CPU_R3000 284 extern unsigned long r3k_cache_size(unsigned long); 285 unsigned long size1, size2; 286 unsigned long cfg = read_c0_conf(); 287 288 size1 = r3k_cache_size(ST0_ISC); 289 write_c0_conf(cfg ^ R30XX_CONF_AC); 290 size2 = r3k_cache_size(ST0_ISC); 291 write_c0_conf(cfg); 292 return size1 != size2; 293 #else 294 return 0; 295 #endif 296 } 297 298 static inline void set_elf_platform(int cpu, const char *plat) 299 { 300 if (cpu == 0) 301 __elf_platform = plat; 302 } 303 304 /* 305 * Get the FPU Implementation/Revision. 306 */ 307 static inline unsigned long cpu_get_fpu_id(void) 308 { 309 unsigned long tmp, fpu_id; 310 311 tmp = read_c0_status(); 312 __enable_fpu(); 313 fpu_id = read_32bit_cp1_register(CP1_REVISION); 314 write_c0_status(tmp); 315 return fpu_id; 316 } 317 318 /* 319 * Check the CPU has an FPU the official way. 320 */ 321 static inline int __cpu_has_fpu(void) 322 { 323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 324 } 325 326 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 327 { 328 #ifdef __NEED_VMBITS_PROBE 329 write_c0_entryhi(0x3fffffffffffe000ULL); 330 back_to_back_c0_hazard(); 331 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 332 #endif 333 } 334 335 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) 336 { 337 switch (isa) { 338 case MIPS_CPU_ISA_M64R2: 339 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 340 case MIPS_CPU_ISA_M64R1: 341 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 342 case MIPS_CPU_ISA_V: 343 c->isa_level |= MIPS_CPU_ISA_V; 344 case MIPS_CPU_ISA_IV: 345 c->isa_level |= MIPS_CPU_ISA_IV; 346 case MIPS_CPU_ISA_III: 347 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | 348 MIPS_CPU_ISA_III; 349 break; 350 351 case MIPS_CPU_ISA_M32R2: 352 c->isa_level |= MIPS_CPU_ISA_M32R2; 353 case MIPS_CPU_ISA_M32R1: 354 c->isa_level |= MIPS_CPU_ISA_M32R1; 355 case MIPS_CPU_ISA_II: 356 c->isa_level |= MIPS_CPU_ISA_II; 357 case MIPS_CPU_ISA_I: 358 c->isa_level |= MIPS_CPU_ISA_I; 359 break; 360 } 361 } 362 363 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 364 "Unsupported ISA type, c0.config0: %d."; 365 366 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 367 { 368 unsigned int config0; 369 int isa; 370 371 config0 = read_c0_config(); 372 373 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 374 c->options |= MIPS_CPU_TLB; 375 isa = (config0 & MIPS_CONF_AT) >> 13; 376 switch (isa) { 377 case 0: 378 switch ((config0 & MIPS_CONF_AR) >> 10) { 379 case 0: 380 set_isa(c, MIPS_CPU_ISA_M32R1); 381 break; 382 case 1: 383 set_isa(c, MIPS_CPU_ISA_M32R2); 384 break; 385 default: 386 goto unknown; 387 } 388 break; 389 case 2: 390 switch ((config0 & MIPS_CONF_AR) >> 10) { 391 case 0: 392 set_isa(c, MIPS_CPU_ISA_M64R1); 393 break; 394 case 1: 395 set_isa(c, MIPS_CPU_ISA_M64R2); 396 break; 397 default: 398 goto unknown; 399 } 400 break; 401 default: 402 goto unknown; 403 } 404 405 return config0 & MIPS_CONF_M; 406 407 unknown: 408 panic(unknown_isa, config0); 409 } 410 411 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 412 { 413 unsigned int config1; 414 415 config1 = read_c0_config1(); 416 417 if (config1 & MIPS_CONF1_MD) 418 c->ases |= MIPS_ASE_MDMX; 419 if (config1 & MIPS_CONF1_WR) 420 c->options |= MIPS_CPU_WATCH; 421 if (config1 & MIPS_CONF1_CA) 422 c->ases |= MIPS_ASE_MIPS16; 423 if (config1 & MIPS_CONF1_EP) 424 c->options |= MIPS_CPU_EJTAG; 425 if (config1 & MIPS_CONF1_FP) { 426 c->options |= MIPS_CPU_FPU; 427 c->options |= MIPS_CPU_32FPR; 428 } 429 if (cpu_has_tlb) 430 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 431 432 return config1 & MIPS_CONF_M; 433 } 434 435 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 436 { 437 unsigned int config2; 438 439 config2 = read_c0_config2(); 440 441 if (config2 & MIPS_CONF2_SL) 442 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 443 444 return config2 & MIPS_CONF_M; 445 } 446 447 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 448 { 449 unsigned int config3; 450 451 config3 = read_c0_config3(); 452 453 if (config3 & MIPS_CONF3_SM) { 454 c->ases |= MIPS_ASE_SMARTMIPS; 455 c->options |= MIPS_CPU_RIXI; 456 } 457 if (config3 & MIPS_CONF3_RXI) 458 c->options |= MIPS_CPU_RIXI; 459 if (config3 & MIPS_CONF3_DSP) 460 c->ases |= MIPS_ASE_DSP; 461 if (config3 & MIPS_CONF3_DSP2P) 462 c->ases |= MIPS_ASE_DSP2P; 463 if (config3 & MIPS_CONF3_VINT) 464 c->options |= MIPS_CPU_VINT; 465 if (config3 & MIPS_CONF3_VEIC) 466 c->options |= MIPS_CPU_VEIC; 467 if (config3 & MIPS_CONF3_MT) 468 c->ases |= MIPS_ASE_MIPSMT; 469 if (config3 & MIPS_CONF3_ULRI) 470 c->options |= MIPS_CPU_ULRI; 471 if (config3 & MIPS_CONF3_ISA) 472 c->options |= MIPS_CPU_MICROMIPS; 473 if (config3 & MIPS_CONF3_VZ) 474 c->ases |= MIPS_ASE_VZ; 475 476 return config3 & MIPS_CONF_M; 477 } 478 479 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 480 { 481 unsigned int config4; 482 483 config4 = read_c0_config4(); 484 485 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 486 && cpu_has_tlb) 487 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 488 489 c->kscratch_mask = (config4 >> 16) & 0xff; 490 491 return config4 & MIPS_CONF_M; 492 } 493 494 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 495 { 496 int ok; 497 498 /* MIPS32 or MIPS64 compliant CPU. */ 499 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 500 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 501 502 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 503 504 ok = decode_config0(c); /* Read Config registers. */ 505 BUG_ON(!ok); /* Arch spec violation! */ 506 if (ok) 507 ok = decode_config1(c); 508 if (ok) 509 ok = decode_config2(c); 510 if (ok) 511 ok = decode_config3(c); 512 if (ok) 513 ok = decode_config4(c); 514 515 mips_probe_watch_registers(c); 516 517 if (cpu_has_mips_r2) 518 c->core = read_c0_ebase() & 0x3ff; 519 } 520 521 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 522 | MIPS_CPU_COUNTER) 523 524 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 525 { 526 switch (c->processor_id & 0xff00) { 527 case PRID_IMP_R2000: 528 c->cputype = CPU_R2000; 529 __cpu_name[cpu] = "R2000"; 530 set_isa(c, MIPS_CPU_ISA_I); 531 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 532 MIPS_CPU_NOFPUEX; 533 if (__cpu_has_fpu()) 534 c->options |= MIPS_CPU_FPU; 535 c->tlbsize = 64; 536 break; 537 case PRID_IMP_R3000: 538 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 539 if (cpu_has_confreg()) { 540 c->cputype = CPU_R3081E; 541 __cpu_name[cpu] = "R3081"; 542 } else { 543 c->cputype = CPU_R3000A; 544 __cpu_name[cpu] = "R3000A"; 545 } 546 } else { 547 c->cputype = CPU_R3000; 548 __cpu_name[cpu] = "R3000"; 549 } 550 set_isa(c, MIPS_CPU_ISA_I); 551 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 552 MIPS_CPU_NOFPUEX; 553 if (__cpu_has_fpu()) 554 c->options |= MIPS_CPU_FPU; 555 c->tlbsize = 64; 556 break; 557 case PRID_IMP_R4000: 558 if (read_c0_config() & CONF_SC) { 559 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 560 c->cputype = CPU_R4400PC; 561 __cpu_name[cpu] = "R4400PC"; 562 } else { 563 c->cputype = CPU_R4000PC; 564 __cpu_name[cpu] = "R4000PC"; 565 } 566 } else { 567 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 568 c->cputype = CPU_R4400SC; 569 __cpu_name[cpu] = "R4400SC"; 570 } else { 571 c->cputype = CPU_R4000SC; 572 __cpu_name[cpu] = "R4000SC"; 573 } 574 } 575 576 set_isa(c, MIPS_CPU_ISA_III); 577 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 578 MIPS_CPU_WATCH | MIPS_CPU_VCE | 579 MIPS_CPU_LLSC; 580 c->tlbsize = 48; 581 break; 582 case PRID_IMP_VR41XX: 583 switch (c->processor_id & 0xf0) { 584 case PRID_REV_VR4111: 585 c->cputype = CPU_VR4111; 586 __cpu_name[cpu] = "NEC VR4111"; 587 break; 588 case PRID_REV_VR4121: 589 c->cputype = CPU_VR4121; 590 __cpu_name[cpu] = "NEC VR4121"; 591 break; 592 case PRID_REV_VR4122: 593 if ((c->processor_id & 0xf) < 0x3) { 594 c->cputype = CPU_VR4122; 595 __cpu_name[cpu] = "NEC VR4122"; 596 } else { 597 c->cputype = CPU_VR4181A; 598 __cpu_name[cpu] = "NEC VR4181A"; 599 } 600 break; 601 case PRID_REV_VR4130: 602 if ((c->processor_id & 0xf) < 0x4) { 603 c->cputype = CPU_VR4131; 604 __cpu_name[cpu] = "NEC VR4131"; 605 } else { 606 c->cputype = CPU_VR4133; 607 __cpu_name[cpu] = "NEC VR4133"; 608 } 609 break; 610 default: 611 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 612 c->cputype = CPU_VR41XX; 613 __cpu_name[cpu] = "NEC Vr41xx"; 614 break; 615 } 616 set_isa(c, MIPS_CPU_ISA_III); 617 c->options = R4K_OPTS; 618 c->tlbsize = 32; 619 break; 620 case PRID_IMP_R4300: 621 c->cputype = CPU_R4300; 622 __cpu_name[cpu] = "R4300"; 623 set_isa(c, MIPS_CPU_ISA_III); 624 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 625 MIPS_CPU_LLSC; 626 c->tlbsize = 32; 627 break; 628 case PRID_IMP_R4600: 629 c->cputype = CPU_R4600; 630 __cpu_name[cpu] = "R4600"; 631 set_isa(c, MIPS_CPU_ISA_III); 632 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 633 MIPS_CPU_LLSC; 634 c->tlbsize = 48; 635 break; 636 #if 0 637 case PRID_IMP_R4650: 638 /* 639 * This processor doesn't have an MMU, so it's not 640 * "real easy" to run Linux on it. It is left purely 641 * for documentation. Commented out because it shares 642 * it's c0_prid id number with the TX3900. 643 */ 644 c->cputype = CPU_R4650; 645 __cpu_name[cpu] = "R4650"; 646 set_isa(c, MIPS_CPU_ISA_III); 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 648 c->tlbsize = 48; 649 break; 650 #endif 651 case PRID_IMP_TX39: 652 set_isa(c, MIPS_CPU_ISA_I); 653 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 654 655 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 656 c->cputype = CPU_TX3927; 657 __cpu_name[cpu] = "TX3927"; 658 c->tlbsize = 64; 659 } else { 660 switch (c->processor_id & 0xff) { 661 case PRID_REV_TX3912: 662 c->cputype = CPU_TX3912; 663 __cpu_name[cpu] = "TX3912"; 664 c->tlbsize = 32; 665 break; 666 case PRID_REV_TX3922: 667 c->cputype = CPU_TX3922; 668 __cpu_name[cpu] = "TX3922"; 669 c->tlbsize = 64; 670 break; 671 } 672 } 673 break; 674 case PRID_IMP_R4700: 675 c->cputype = CPU_R4700; 676 __cpu_name[cpu] = "R4700"; 677 set_isa(c, MIPS_CPU_ISA_III); 678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 679 MIPS_CPU_LLSC; 680 c->tlbsize = 48; 681 break; 682 case PRID_IMP_TX49: 683 c->cputype = CPU_TX49XX; 684 __cpu_name[cpu] = "R49XX"; 685 set_isa(c, MIPS_CPU_ISA_III); 686 c->options = R4K_OPTS | MIPS_CPU_LLSC; 687 if (!(c->processor_id & 0x08)) 688 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 689 c->tlbsize = 48; 690 break; 691 case PRID_IMP_R5000: 692 c->cputype = CPU_R5000; 693 __cpu_name[cpu] = "R5000"; 694 set_isa(c, MIPS_CPU_ISA_IV); 695 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 696 MIPS_CPU_LLSC; 697 c->tlbsize = 48; 698 break; 699 case PRID_IMP_R5432: 700 c->cputype = CPU_R5432; 701 __cpu_name[cpu] = "R5432"; 702 set_isa(c, MIPS_CPU_ISA_IV); 703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 704 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 705 c->tlbsize = 48; 706 break; 707 case PRID_IMP_R5500: 708 c->cputype = CPU_R5500; 709 __cpu_name[cpu] = "R5500"; 710 set_isa(c, MIPS_CPU_ISA_IV); 711 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 712 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 713 c->tlbsize = 48; 714 break; 715 case PRID_IMP_NEVADA: 716 c->cputype = CPU_NEVADA; 717 __cpu_name[cpu] = "Nevada"; 718 set_isa(c, MIPS_CPU_ISA_IV); 719 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 720 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 721 c->tlbsize = 48; 722 break; 723 case PRID_IMP_R6000: 724 c->cputype = CPU_R6000; 725 __cpu_name[cpu] = "R6000"; 726 set_isa(c, MIPS_CPU_ISA_II); 727 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 728 MIPS_CPU_LLSC; 729 c->tlbsize = 32; 730 break; 731 case PRID_IMP_R6000A: 732 c->cputype = CPU_R6000A; 733 __cpu_name[cpu] = "R6000A"; 734 set_isa(c, MIPS_CPU_ISA_II); 735 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 736 MIPS_CPU_LLSC; 737 c->tlbsize = 32; 738 break; 739 case PRID_IMP_RM7000: 740 c->cputype = CPU_RM7000; 741 __cpu_name[cpu] = "RM7000"; 742 set_isa(c, MIPS_CPU_ISA_IV); 743 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 744 MIPS_CPU_LLSC; 745 /* 746 * Undocumented RM7000: Bit 29 in the info register of 747 * the RM7000 v2.0 indicates if the TLB has 48 or 64 748 * entries. 749 * 750 * 29 1 => 64 entry JTLB 751 * 0 => 48 entry JTLB 752 */ 753 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 754 break; 755 case PRID_IMP_RM9000: 756 c->cputype = CPU_RM9000; 757 __cpu_name[cpu] = "RM9000"; 758 set_isa(c, MIPS_CPU_ISA_IV); 759 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 760 MIPS_CPU_LLSC; 761 /* 762 * Bit 29 in the info register of the RM9000 763 * indicates if the TLB has 48 or 64 entries. 764 * 765 * 29 1 => 64 entry JTLB 766 * 0 => 48 entry JTLB 767 */ 768 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 769 break; 770 case PRID_IMP_R8000: 771 c->cputype = CPU_R8000; 772 __cpu_name[cpu] = "RM8000"; 773 set_isa(c, MIPS_CPU_ISA_IV); 774 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 775 MIPS_CPU_FPU | MIPS_CPU_32FPR | 776 MIPS_CPU_LLSC; 777 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 778 break; 779 case PRID_IMP_R10000: 780 c->cputype = CPU_R10000; 781 __cpu_name[cpu] = "R10000"; 782 set_isa(c, MIPS_CPU_ISA_IV); 783 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 784 MIPS_CPU_FPU | MIPS_CPU_32FPR | 785 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 786 MIPS_CPU_LLSC; 787 c->tlbsize = 64; 788 break; 789 case PRID_IMP_R12000: 790 c->cputype = CPU_R12000; 791 __cpu_name[cpu] = "R12000"; 792 set_isa(c, MIPS_CPU_ISA_IV); 793 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 794 MIPS_CPU_FPU | MIPS_CPU_32FPR | 795 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 796 MIPS_CPU_LLSC; 797 c->tlbsize = 64; 798 break; 799 case PRID_IMP_R14000: 800 c->cputype = CPU_R14000; 801 __cpu_name[cpu] = "R14000"; 802 set_isa(c, MIPS_CPU_ISA_IV); 803 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 804 MIPS_CPU_FPU | MIPS_CPU_32FPR | 805 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 806 MIPS_CPU_LLSC; 807 c->tlbsize = 64; 808 break; 809 case PRID_IMP_LOONGSON2: 810 c->cputype = CPU_LOONGSON2; 811 __cpu_name[cpu] = "ICT Loongson-2"; 812 813 switch (c->processor_id & PRID_REV_MASK) { 814 case PRID_REV_LOONGSON2E: 815 set_elf_platform(cpu, "loongson2e"); 816 break; 817 case PRID_REV_LOONGSON2F: 818 set_elf_platform(cpu, "loongson2f"); 819 break; 820 } 821 822 set_isa(c, MIPS_CPU_ISA_III); 823 c->options = R4K_OPTS | 824 MIPS_CPU_FPU | MIPS_CPU_LLSC | 825 MIPS_CPU_32FPR; 826 c->tlbsize = 64; 827 break; 828 case PRID_IMP_LOONGSON1: 829 decode_configs(c); 830 831 c->cputype = CPU_LOONGSON1; 832 833 switch (c->processor_id & PRID_REV_MASK) { 834 case PRID_REV_LOONGSON1B: 835 __cpu_name[cpu] = "Loongson 1B"; 836 break; 837 } 838 839 break; 840 } 841 } 842 843 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 844 { 845 decode_configs(c); 846 switch (c->processor_id & 0xff00) { 847 case PRID_IMP_4KC: 848 c->cputype = CPU_4KC; 849 __cpu_name[cpu] = "MIPS 4Kc"; 850 break; 851 case PRID_IMP_4KEC: 852 case PRID_IMP_4KECR2: 853 c->cputype = CPU_4KEC; 854 __cpu_name[cpu] = "MIPS 4KEc"; 855 break; 856 case PRID_IMP_4KSC: 857 case PRID_IMP_4KSD: 858 c->cputype = CPU_4KSC; 859 __cpu_name[cpu] = "MIPS 4KSc"; 860 break; 861 case PRID_IMP_5KC: 862 c->cputype = CPU_5KC; 863 __cpu_name[cpu] = "MIPS 5Kc"; 864 break; 865 case PRID_IMP_5KE: 866 c->cputype = CPU_5KE; 867 __cpu_name[cpu] = "MIPS 5KE"; 868 break; 869 case PRID_IMP_20KC: 870 c->cputype = CPU_20KC; 871 __cpu_name[cpu] = "MIPS 20Kc"; 872 break; 873 case PRID_IMP_24K: 874 c->cputype = CPU_24K; 875 __cpu_name[cpu] = "MIPS 24Kc"; 876 break; 877 case PRID_IMP_24KE: 878 c->cputype = CPU_24K; 879 __cpu_name[cpu] = "MIPS 24KEc"; 880 break; 881 case PRID_IMP_25KF: 882 c->cputype = CPU_25KF; 883 __cpu_name[cpu] = "MIPS 25Kc"; 884 break; 885 case PRID_IMP_34K: 886 c->cputype = CPU_34K; 887 __cpu_name[cpu] = "MIPS 34Kc"; 888 break; 889 case PRID_IMP_74K: 890 c->cputype = CPU_74K; 891 __cpu_name[cpu] = "MIPS 74Kc"; 892 break; 893 case PRID_IMP_M14KC: 894 c->cputype = CPU_M14KC; 895 __cpu_name[cpu] = "MIPS M14Kc"; 896 break; 897 case PRID_IMP_M14KEC: 898 c->cputype = CPU_M14KEC; 899 __cpu_name[cpu] = "MIPS M14KEc"; 900 break; 901 case PRID_IMP_1004K: 902 c->cputype = CPU_1004K; 903 __cpu_name[cpu] = "MIPS 1004Kc"; 904 break; 905 case PRID_IMP_1074K: 906 c->cputype = CPU_74K; 907 __cpu_name[cpu] = "MIPS 1074Kc"; 908 break; 909 } 910 911 spram_config(); 912 } 913 914 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 915 { 916 decode_configs(c); 917 switch (c->processor_id & 0xff00) { 918 case PRID_IMP_AU1_REV1: 919 case PRID_IMP_AU1_REV2: 920 c->cputype = CPU_ALCHEMY; 921 switch ((c->processor_id >> 24) & 0xff) { 922 case 0: 923 __cpu_name[cpu] = "Au1000"; 924 break; 925 case 1: 926 __cpu_name[cpu] = "Au1500"; 927 break; 928 case 2: 929 __cpu_name[cpu] = "Au1100"; 930 break; 931 case 3: 932 __cpu_name[cpu] = "Au1550"; 933 break; 934 case 4: 935 __cpu_name[cpu] = "Au1200"; 936 if ((c->processor_id & 0xff) == 2) 937 __cpu_name[cpu] = "Au1250"; 938 break; 939 case 5: 940 __cpu_name[cpu] = "Au1210"; 941 break; 942 default: 943 __cpu_name[cpu] = "Au1xxx"; 944 break; 945 } 946 break; 947 } 948 } 949 950 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 951 { 952 decode_configs(c); 953 954 switch (c->processor_id & 0xff00) { 955 case PRID_IMP_SB1: 956 c->cputype = CPU_SB1; 957 __cpu_name[cpu] = "SiByte SB1"; 958 /* FPU in pass1 is known to have issues. */ 959 if ((c->processor_id & 0xff) < 0x02) 960 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 961 break; 962 case PRID_IMP_SB1A: 963 c->cputype = CPU_SB1A; 964 __cpu_name[cpu] = "SiByte SB1A"; 965 break; 966 } 967 } 968 969 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 970 { 971 decode_configs(c); 972 switch (c->processor_id & 0xff00) { 973 case PRID_IMP_SR71000: 974 c->cputype = CPU_SR71000; 975 __cpu_name[cpu] = "Sandcraft SR71000"; 976 c->scache.ways = 8; 977 c->tlbsize = 64; 978 break; 979 } 980 } 981 982 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 983 { 984 decode_configs(c); 985 switch (c->processor_id & 0xff00) { 986 case PRID_IMP_PR4450: 987 c->cputype = CPU_PR4450; 988 __cpu_name[cpu] = "Philips PR4450"; 989 set_isa(c, MIPS_CPU_ISA_M32R1); 990 break; 991 } 992 } 993 994 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 995 { 996 decode_configs(c); 997 switch (c->processor_id & 0xff00) { 998 case PRID_IMP_BMIPS32_REV4: 999 case PRID_IMP_BMIPS32_REV8: 1000 c->cputype = CPU_BMIPS32; 1001 __cpu_name[cpu] = "Broadcom BMIPS32"; 1002 set_elf_platform(cpu, "bmips32"); 1003 break; 1004 case PRID_IMP_BMIPS3300: 1005 case PRID_IMP_BMIPS3300_ALT: 1006 case PRID_IMP_BMIPS3300_BUG: 1007 c->cputype = CPU_BMIPS3300; 1008 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1009 set_elf_platform(cpu, "bmips3300"); 1010 break; 1011 case PRID_IMP_BMIPS43XX: { 1012 int rev = c->processor_id & 0xff; 1013 1014 if (rev >= PRID_REV_BMIPS4380_LO && 1015 rev <= PRID_REV_BMIPS4380_HI) { 1016 c->cputype = CPU_BMIPS4380; 1017 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1018 set_elf_platform(cpu, "bmips4380"); 1019 } else { 1020 c->cputype = CPU_BMIPS4350; 1021 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1022 set_elf_platform(cpu, "bmips4350"); 1023 } 1024 break; 1025 } 1026 case PRID_IMP_BMIPS5000: 1027 c->cputype = CPU_BMIPS5000; 1028 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1029 set_elf_platform(cpu, "bmips5000"); 1030 c->options |= MIPS_CPU_ULRI; 1031 break; 1032 } 1033 } 1034 1035 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1036 { 1037 decode_configs(c); 1038 switch (c->processor_id & 0xff00) { 1039 case PRID_IMP_CAVIUM_CN38XX: 1040 case PRID_IMP_CAVIUM_CN31XX: 1041 case PRID_IMP_CAVIUM_CN30XX: 1042 c->cputype = CPU_CAVIUM_OCTEON; 1043 __cpu_name[cpu] = "Cavium Octeon"; 1044 goto platform; 1045 case PRID_IMP_CAVIUM_CN58XX: 1046 case PRID_IMP_CAVIUM_CN56XX: 1047 case PRID_IMP_CAVIUM_CN50XX: 1048 case PRID_IMP_CAVIUM_CN52XX: 1049 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1050 __cpu_name[cpu] = "Cavium Octeon+"; 1051 platform: 1052 set_elf_platform(cpu, "octeon"); 1053 break; 1054 case PRID_IMP_CAVIUM_CN61XX: 1055 case PRID_IMP_CAVIUM_CN63XX: 1056 case PRID_IMP_CAVIUM_CN66XX: 1057 case PRID_IMP_CAVIUM_CN68XX: 1058 c->cputype = CPU_CAVIUM_OCTEON2; 1059 __cpu_name[cpu] = "Cavium Octeon II"; 1060 set_elf_platform(cpu, "octeon2"); 1061 break; 1062 default: 1063 printk(KERN_INFO "Unknown Octeon chip!\n"); 1064 c->cputype = CPU_UNKNOWN; 1065 break; 1066 } 1067 } 1068 1069 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1070 { 1071 decode_configs(c); 1072 /* JZRISC does not implement the CP0 counter. */ 1073 c->options &= ~MIPS_CPU_COUNTER; 1074 switch (c->processor_id & 0xff00) { 1075 case PRID_IMP_JZRISC: 1076 c->cputype = CPU_JZRISC; 1077 __cpu_name[cpu] = "Ingenic JZRISC"; 1078 break; 1079 default: 1080 panic("Unknown Ingenic Processor ID!"); 1081 break; 1082 } 1083 } 1084 1085 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1086 { 1087 decode_configs(c); 1088 1089 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { 1090 c->cputype = CPU_ALCHEMY; 1091 __cpu_name[cpu] = "Au1300"; 1092 /* following stuff is not for Alchemy */ 1093 return; 1094 } 1095 1096 c->options = (MIPS_CPU_TLB | 1097 MIPS_CPU_4KEX | 1098 MIPS_CPU_COUNTER | 1099 MIPS_CPU_DIVEC | 1100 MIPS_CPU_WATCH | 1101 MIPS_CPU_EJTAG | 1102 MIPS_CPU_LLSC); 1103 1104 switch (c->processor_id & 0xff00) { 1105 case PRID_IMP_NETLOGIC_XLP8XX: 1106 case PRID_IMP_NETLOGIC_XLP3XX: 1107 c->cputype = CPU_XLP; 1108 __cpu_name[cpu] = "Netlogic XLP"; 1109 break; 1110 1111 case PRID_IMP_NETLOGIC_XLR732: 1112 case PRID_IMP_NETLOGIC_XLR716: 1113 case PRID_IMP_NETLOGIC_XLR532: 1114 case PRID_IMP_NETLOGIC_XLR308: 1115 case PRID_IMP_NETLOGIC_XLR532C: 1116 case PRID_IMP_NETLOGIC_XLR516C: 1117 case PRID_IMP_NETLOGIC_XLR508C: 1118 case PRID_IMP_NETLOGIC_XLR308C: 1119 c->cputype = CPU_XLR; 1120 __cpu_name[cpu] = "Netlogic XLR"; 1121 break; 1122 1123 case PRID_IMP_NETLOGIC_XLS608: 1124 case PRID_IMP_NETLOGIC_XLS408: 1125 case PRID_IMP_NETLOGIC_XLS404: 1126 case PRID_IMP_NETLOGIC_XLS208: 1127 case PRID_IMP_NETLOGIC_XLS204: 1128 case PRID_IMP_NETLOGIC_XLS108: 1129 case PRID_IMP_NETLOGIC_XLS104: 1130 case PRID_IMP_NETLOGIC_XLS616B: 1131 case PRID_IMP_NETLOGIC_XLS608B: 1132 case PRID_IMP_NETLOGIC_XLS416B: 1133 case PRID_IMP_NETLOGIC_XLS412B: 1134 case PRID_IMP_NETLOGIC_XLS408B: 1135 case PRID_IMP_NETLOGIC_XLS404B: 1136 c->cputype = CPU_XLR; 1137 __cpu_name[cpu] = "Netlogic XLS"; 1138 break; 1139 1140 default: 1141 pr_info("Unknown Netlogic chip id [%02x]!\n", 1142 c->processor_id); 1143 c->cputype = CPU_XLR; 1144 break; 1145 } 1146 1147 if (c->cputype == CPU_XLP) { 1148 set_isa(c, MIPS_CPU_ISA_M64R2); 1149 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1150 /* This will be updated again after all threads are woken up */ 1151 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1152 } else { 1153 set_isa(c, MIPS_CPU_ISA_M64R1); 1154 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1155 } 1156 } 1157 1158 #ifdef CONFIG_64BIT 1159 /* For use by uaccess.h */ 1160 u64 __ua_limit; 1161 EXPORT_SYMBOL(__ua_limit); 1162 #endif 1163 1164 const char *__cpu_name[NR_CPUS]; 1165 const char *__elf_platform; 1166 1167 __cpuinit void cpu_probe(void) 1168 { 1169 struct cpuinfo_mips *c = ¤t_cpu_data; 1170 unsigned int cpu = smp_processor_id(); 1171 1172 c->processor_id = PRID_IMP_UNKNOWN; 1173 c->fpu_id = FPIR_IMP_NONE; 1174 c->cputype = CPU_UNKNOWN; 1175 1176 c->processor_id = read_c0_prid(); 1177 switch (c->processor_id & 0xff0000) { 1178 case PRID_COMP_LEGACY: 1179 cpu_probe_legacy(c, cpu); 1180 break; 1181 case PRID_COMP_MIPS: 1182 cpu_probe_mips(c, cpu); 1183 break; 1184 case PRID_COMP_ALCHEMY: 1185 cpu_probe_alchemy(c, cpu); 1186 break; 1187 case PRID_COMP_SIBYTE: 1188 cpu_probe_sibyte(c, cpu); 1189 break; 1190 case PRID_COMP_BROADCOM: 1191 cpu_probe_broadcom(c, cpu); 1192 break; 1193 case PRID_COMP_SANDCRAFT: 1194 cpu_probe_sandcraft(c, cpu); 1195 break; 1196 case PRID_COMP_NXP: 1197 cpu_probe_nxp(c, cpu); 1198 break; 1199 case PRID_COMP_CAVIUM: 1200 cpu_probe_cavium(c, cpu); 1201 break; 1202 case PRID_COMP_INGENIC: 1203 cpu_probe_ingenic(c, cpu); 1204 break; 1205 case PRID_COMP_NETLOGIC: 1206 cpu_probe_netlogic(c, cpu); 1207 break; 1208 } 1209 1210 BUG_ON(!__cpu_name[cpu]); 1211 BUG_ON(c->cputype == CPU_UNKNOWN); 1212 1213 /* 1214 * Platform code can force the cpu type to optimize code 1215 * generation. In that case be sure the cpu type is correctly 1216 * manually setup otherwise it could trigger some nasty bugs. 1217 */ 1218 BUG_ON(current_cpu_type() != c->cputype); 1219 1220 if (mips_fpu_disabled) 1221 c->options &= ~MIPS_CPU_FPU; 1222 1223 if (mips_dsp_disabled) 1224 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1225 1226 if (c->options & MIPS_CPU_FPU) { 1227 c->fpu_id = cpu_get_fpu_id(); 1228 1229 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1230 c->isa_level == MIPS_CPU_ISA_M32R2 || 1231 c->isa_level == MIPS_CPU_ISA_M64R1 || 1232 c->isa_level == MIPS_CPU_ISA_M64R2) { 1233 if (c->fpu_id & MIPS_FPIR_3D) 1234 c->ases |= MIPS_ASE_MIPS3D; 1235 } 1236 } 1237 1238 if (cpu_has_mips_r2) { 1239 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1240 /* R2 has Performance Counter Interrupt indicator */ 1241 c->options |= MIPS_CPU_PCI; 1242 } 1243 else 1244 c->srsets = 1; 1245 1246 cpu_probe_vmbits(c); 1247 1248 #ifdef CONFIG_64BIT 1249 if (cpu == 0) 1250 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1251 #endif 1252 } 1253 1254 __cpuinit void cpu_report(void) 1255 { 1256 struct cpuinfo_mips *c = ¤t_cpu_data; 1257 1258 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1259 c->processor_id, cpu_name_string()); 1260 if (c->options & MIPS_CPU_FPU) 1261 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1262 } 1263