1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <linux/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 /* 40 * Get the FPU Implementation/Revision. 41 */ 42 static inline unsigned long cpu_get_fpu_id(void) 43 { 44 unsigned long tmp, fpu_id; 45 46 tmp = read_c0_status(); 47 __enable_fpu(FPU_AS_IS); 48 fpu_id = read_32bit_cp1_register(CP1_REVISION); 49 write_c0_status(tmp); 50 return fpu_id; 51 } 52 53 /* 54 * Check if the CPU has an external FPU. 55 */ 56 static inline int __cpu_has_fpu(void) 57 { 58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 59 } 60 61 static inline unsigned long cpu_get_msa_id(void) 62 { 63 unsigned long status, msa_id; 64 65 status = read_c0_status(); 66 __enable_fpu(FPU_64BIT); 67 enable_msa(); 68 msa_id = read_msa_ir(); 69 disable_msa(); 70 write_c0_status(status); 71 return msa_id; 72 } 73 74 /* 75 * Determine the FCSR mask for FPU hardware. 76 */ 77 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 78 { 79 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 80 81 fcsr = c->fpu_csr31; 82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 83 84 sr = read_c0_status(); 85 __enable_fpu(FPU_AS_IS); 86 87 fcsr0 = fcsr & mask; 88 write_32bit_cp1_register(CP1_STATUS, fcsr0); 89 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 90 91 fcsr1 = fcsr | ~mask; 92 write_32bit_cp1_register(CP1_STATUS, fcsr1); 93 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 94 95 write_32bit_cp1_register(CP1_STATUS, fcsr); 96 97 write_c0_status(sr); 98 99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 100 } 101 102 /* 103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 104 * supported by FPU hardware. 105 */ 106 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 107 { 108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 111 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 112 113 sr = read_c0_status(); 114 __enable_fpu(FPU_AS_IS); 115 116 fir = read_32bit_cp1_register(CP1_REVISION); 117 if (fir & MIPS_FPIR_HAS2008) { 118 fcsr = read_32bit_cp1_register(CP1_STATUS); 119 120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 121 write_32bit_cp1_register(CP1_STATUS, fcsr0); 122 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 123 124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 125 write_32bit_cp1_register(CP1_STATUS, fcsr1); 126 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 127 128 write_32bit_cp1_register(CP1_STATUS, fcsr); 129 130 if (!(fcsr0 & FPU_CSR_NAN2008)) 131 c->options |= MIPS_CPU_NAN_LEGACY; 132 if (fcsr1 & FPU_CSR_NAN2008) 133 c->options |= MIPS_CPU_NAN_2008; 134 135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 136 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 137 else 138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 139 140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 141 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 142 else 143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 144 } else { 145 c->options |= MIPS_CPU_NAN_LEGACY; 146 } 147 148 write_c0_status(sr); 149 } else { 150 c->options |= MIPS_CPU_NAN_LEGACY; 151 } 152 } 153 154 /* 155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 156 * ABS.fmt/NEG.fmt execution mode. 157 */ 158 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 159 160 /* 161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 162 * to support by the FPU emulator according to the IEEE 754 conformance 163 * mode selected. Note that "relaxed" straps the emulator so that it 164 * allows 2008-NaN binaries even for legacy processors. 165 */ 166 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 167 { 168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 171 172 switch (ieee754) { 173 case STRICT: 174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 178 } else { 179 c->options |= MIPS_CPU_NAN_LEGACY; 180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 181 } 182 break; 183 case LEGACY: 184 c->options |= MIPS_CPU_NAN_LEGACY; 185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 186 break; 187 case STD2008: 188 c->options |= MIPS_CPU_NAN_2008; 189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 191 break; 192 case RELAXED: 193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 194 break; 195 } 196 } 197 198 /* 199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 200 * according to the "ieee754=" parameter. 201 */ 202 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 203 { 204 switch (ieee754) { 205 case STRICT: 206 mips_use_nan_legacy = !!cpu_has_nan_legacy; 207 mips_use_nan_2008 = !!cpu_has_nan_2008; 208 break; 209 case LEGACY: 210 mips_use_nan_legacy = !!cpu_has_nan_legacy; 211 mips_use_nan_2008 = !cpu_has_nan_legacy; 212 break; 213 case STD2008: 214 mips_use_nan_legacy = !cpu_has_nan_2008; 215 mips_use_nan_2008 = !!cpu_has_nan_2008; 216 break; 217 case RELAXED: 218 mips_use_nan_legacy = true; 219 mips_use_nan_2008 = true; 220 break; 221 } 222 } 223 224 /* 225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 226 * settings: 227 * 228 * strict: accept binaries that request a NaN encoding supported by the FPU 229 * legacy: only accept legacy-NaN binaries 230 * 2008: only accept 2008-NaN binaries 231 * relaxed: accept any binaries regardless of whether supported by the FPU 232 */ 233 static int __init ieee754_setup(char *s) 234 { 235 if (!s) 236 return -1; 237 else if (!strcmp(s, "strict")) 238 ieee754 = STRICT; 239 else if (!strcmp(s, "legacy")) 240 ieee754 = LEGACY; 241 else if (!strcmp(s, "2008")) 242 ieee754 = STD2008; 243 else if (!strcmp(s, "relaxed")) 244 ieee754 = RELAXED; 245 else 246 return -1; 247 248 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 249 cpu_set_nofpu_2008(&boot_cpu_data); 250 cpu_set_nan_2008(&boot_cpu_data); 251 252 return 0; 253 } 254 255 early_param("ieee754", ieee754_setup); 256 257 /* 258 * Set the FIR feature flags for the FPU emulator. 259 */ 260 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 261 { 262 u32 value; 263 264 value = 0; 265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 268 value |= MIPS_FPIR_D | MIPS_FPIR_S; 269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 272 if (c->options & MIPS_CPU_NAN_2008) 273 value |= MIPS_FPIR_HAS2008; 274 c->fpu_id = value; 275 } 276 277 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 278 static unsigned int mips_nofpu_msk31; 279 280 /* 281 * Set options for FPU hardware. 282 */ 283 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 284 { 285 c->fpu_id = cpu_get_fpu_id(); 286 mips_nofpu_msk31 = c->fpu_msk31; 287 288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 291 if (c->fpu_id & MIPS_FPIR_3D) 292 c->ases |= MIPS_ASE_MIPS3D; 293 if (c->fpu_id & MIPS_FPIR_UFRP) 294 c->options |= MIPS_CPU_UFR; 295 if (c->fpu_id & MIPS_FPIR_FREP) 296 c->options |= MIPS_CPU_FRE; 297 } 298 299 cpu_set_fpu_fcsr_mask(c); 300 cpu_set_fpu_2008(c); 301 cpu_set_nan_2008(c); 302 } 303 304 /* 305 * Set options for the FPU emulator. 306 */ 307 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 308 { 309 c->options &= ~MIPS_CPU_FPU; 310 c->fpu_msk31 = mips_nofpu_msk31; 311 312 cpu_set_nofpu_2008(c); 313 cpu_set_nan_2008(c); 314 cpu_set_nofpu_id(c); 315 } 316 317 static int mips_fpu_disabled; 318 319 static int __init fpu_disable(char *s) 320 { 321 cpu_set_nofpu_opts(&boot_cpu_data); 322 mips_fpu_disabled = 1; 323 324 return 1; 325 } 326 327 __setup("nofpu", fpu_disable); 328 329 static int mips_dsp_disabled; 330 331 static int __init dsp_disable(char *s) 332 { 333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 334 mips_dsp_disabled = 1; 335 336 return 1; 337 } 338 339 __setup("nodsp", dsp_disable); 340 341 static int mips_htw_disabled; 342 343 static int __init htw_disable(char *s) 344 { 345 mips_htw_disabled = 1; 346 cpu_data[0].options &= ~MIPS_CPU_HTW; 347 write_c0_pwctl(read_c0_pwctl() & 348 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 349 350 return 1; 351 } 352 353 __setup("nohtw", htw_disable); 354 355 static int mips_ftlb_disabled; 356 static int mips_has_ftlb_configured; 357 358 enum ftlb_flags { 359 FTLB_EN = 1 << 0, 360 FTLB_SET_PROB = 1 << 1, 361 }; 362 363 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 364 365 static int __init ftlb_disable(char *s) 366 { 367 unsigned int config4, mmuextdef; 368 369 /* 370 * If the core hasn't done any FTLB configuration, there is nothing 371 * for us to do here. 372 */ 373 if (!mips_has_ftlb_configured) 374 return 1; 375 376 /* Disable it in the boot cpu */ 377 if (set_ftlb_enable(&cpu_data[0], 0)) { 378 pr_warn("Can't turn FTLB off\n"); 379 return 1; 380 } 381 382 config4 = read_c0_config4(); 383 384 /* Check that FTLB has been disabled */ 385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 388 /* This should never happen */ 389 pr_warn("FTLB could not be disabled!\n"); 390 return 1; 391 } 392 393 mips_ftlb_disabled = 1; 394 mips_has_ftlb_configured = 0; 395 396 /* 397 * noftlb is mainly used for debug purposes so print 398 * an informative message instead of using pr_debug() 399 */ 400 pr_info("FTLB has been disabled\n"); 401 402 /* 403 * Some of these bits are duplicated in the decode_config4. 404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 405 * once FTLB has been disabled so undo what decode_config4 did. 406 */ 407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 408 cpu_data[0].tlbsizeftlbsets; 409 cpu_data[0].tlbsizeftlbsets = 0; 410 cpu_data[0].tlbsizeftlbways = 0; 411 412 return 1; 413 } 414 415 __setup("noftlb", ftlb_disable); 416 417 /* 418 * Check if the CPU has per tc perf counters 419 */ 420 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) 421 { 422 if (read_c0_config7() & MTI_CONF7_PTC) 423 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; 424 } 425 426 static inline void check_errata(void) 427 { 428 struct cpuinfo_mips *c = ¤t_cpu_data; 429 430 switch (current_cpu_type()) { 431 case CPU_34K: 432 /* 433 * Erratum "RPS May Cause Incorrect Instruction Execution" 434 * This code only handles VPE0, any SMP/RTOS code 435 * making use of VPE1 will be responsable for that VPE. 436 */ 437 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 438 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 439 break; 440 default: 441 break; 442 } 443 } 444 445 void __init check_bugs32(void) 446 { 447 check_errata(); 448 } 449 450 /* 451 * Probe whether cpu has config register by trying to play with 452 * alternate cache bit and see whether it matters. 453 * It's used by cpu_probe to distinguish between R3000A and R3081. 454 */ 455 static inline int cpu_has_confreg(void) 456 { 457 #ifdef CONFIG_CPU_R3000 458 extern unsigned long r3k_cache_size(unsigned long); 459 unsigned long size1, size2; 460 unsigned long cfg = read_c0_conf(); 461 462 size1 = r3k_cache_size(ST0_ISC); 463 write_c0_conf(cfg ^ R30XX_CONF_AC); 464 size2 = r3k_cache_size(ST0_ISC); 465 write_c0_conf(cfg); 466 return size1 != size2; 467 #else 468 return 0; 469 #endif 470 } 471 472 static inline void set_elf_platform(int cpu, const char *plat) 473 { 474 if (cpu == 0) 475 __elf_platform = plat; 476 } 477 478 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 479 { 480 #ifdef __NEED_VMBITS_PROBE 481 write_c0_entryhi(0x3fffffffffffe000ULL); 482 back_to_back_c0_hazard(); 483 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 484 #endif 485 } 486 487 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 488 { 489 switch (isa) { 490 case MIPS_CPU_ISA_M64R2: 491 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 492 case MIPS_CPU_ISA_M64R1: 493 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 494 case MIPS_CPU_ISA_V: 495 c->isa_level |= MIPS_CPU_ISA_V; 496 case MIPS_CPU_ISA_IV: 497 c->isa_level |= MIPS_CPU_ISA_IV; 498 case MIPS_CPU_ISA_III: 499 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 500 break; 501 502 /* R6 incompatible with everything else */ 503 case MIPS_CPU_ISA_M64R6: 504 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 505 case MIPS_CPU_ISA_M32R6: 506 c->isa_level |= MIPS_CPU_ISA_M32R6; 507 /* Break here so we don't add incompatible ISAs */ 508 break; 509 case MIPS_CPU_ISA_M32R2: 510 c->isa_level |= MIPS_CPU_ISA_M32R2; 511 case MIPS_CPU_ISA_M32R1: 512 c->isa_level |= MIPS_CPU_ISA_M32R1; 513 case MIPS_CPU_ISA_II: 514 c->isa_level |= MIPS_CPU_ISA_II; 515 break; 516 } 517 } 518 519 static char unknown_isa[] = KERN_ERR \ 520 "Unsupported ISA type, c0.config0: %d."; 521 522 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 523 { 524 525 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 526 527 /* 528 * 0 = All TLBWR instructions go to FTLB 529 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 530 * FTLB and 1 goes to the VTLB. 531 * 2 = 7:1: As above with 7:1 ratio. 532 * 3 = 3:1: As above with 3:1 ratio. 533 * 534 * Use the linear midpoint as the probability threshold. 535 */ 536 if (probability >= 12) 537 return 1; 538 else if (probability >= 6) 539 return 2; 540 else 541 /* 542 * So FTLB is less than 4 times bigger than VTLB. 543 * A 3:1 ratio can still be useful though. 544 */ 545 return 3; 546 } 547 548 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 549 { 550 unsigned int config; 551 552 /* It's implementation dependent how the FTLB can be enabled */ 553 switch (c->cputype) { 554 case CPU_PROAPTIV: 555 case CPU_P5600: 556 case CPU_P6600: 557 /* proAptiv & related cores use Config6 to enable the FTLB */ 558 config = read_c0_config6(); 559 560 if (flags & FTLB_EN) 561 config |= MIPS_CONF6_FTLBEN; 562 else 563 config &= ~MIPS_CONF6_FTLBEN; 564 565 if (flags & FTLB_SET_PROB) { 566 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 567 config |= calculate_ftlb_probability(c) 568 << MIPS_CONF6_FTLBP_SHIFT; 569 } 570 571 write_c0_config6(config); 572 back_to_back_c0_hazard(); 573 break; 574 case CPU_I6400: 575 case CPU_I6500: 576 /* There's no way to disable the FTLB */ 577 if (!(flags & FTLB_EN)) 578 return 1; 579 return 0; 580 case CPU_LOONGSON3: 581 /* Flush ITLB, DTLB, VTLB and FTLB */ 582 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 583 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 584 /* Loongson-3 cores use Config6 to enable the FTLB */ 585 config = read_c0_config6(); 586 if (flags & FTLB_EN) 587 /* Enable FTLB */ 588 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); 589 else 590 /* Disable FTLB */ 591 write_c0_config6(config | MIPS_CONF6_FTLBDIS); 592 break; 593 default: 594 return 1; 595 } 596 597 return 0; 598 } 599 600 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 601 { 602 unsigned int config0; 603 int isa, mt; 604 605 config0 = read_c0_config(); 606 607 /* 608 * Look for Standard TLB or Dual VTLB and FTLB 609 */ 610 mt = config0 & MIPS_CONF_MT; 611 if (mt == MIPS_CONF_MT_TLB) 612 c->options |= MIPS_CPU_TLB; 613 else if (mt == MIPS_CONF_MT_FTLB) 614 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 615 616 isa = (config0 & MIPS_CONF_AT) >> 13; 617 switch (isa) { 618 case 0: 619 switch ((config0 & MIPS_CONF_AR) >> 10) { 620 case 0: 621 set_isa(c, MIPS_CPU_ISA_M32R1); 622 break; 623 case 1: 624 set_isa(c, MIPS_CPU_ISA_M32R2); 625 break; 626 case 2: 627 set_isa(c, MIPS_CPU_ISA_M32R6); 628 break; 629 default: 630 goto unknown; 631 } 632 break; 633 case 2: 634 switch ((config0 & MIPS_CONF_AR) >> 10) { 635 case 0: 636 set_isa(c, MIPS_CPU_ISA_M64R1); 637 break; 638 case 1: 639 set_isa(c, MIPS_CPU_ISA_M64R2); 640 break; 641 case 2: 642 set_isa(c, MIPS_CPU_ISA_M64R6); 643 break; 644 default: 645 goto unknown; 646 } 647 break; 648 default: 649 goto unknown; 650 } 651 652 return config0 & MIPS_CONF_M; 653 654 unknown: 655 panic(unknown_isa, config0); 656 } 657 658 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 659 { 660 unsigned int config1; 661 662 config1 = read_c0_config1(); 663 664 if (config1 & MIPS_CONF1_MD) 665 c->ases |= MIPS_ASE_MDMX; 666 if (config1 & MIPS_CONF1_PC) 667 c->options |= MIPS_CPU_PERF; 668 if (config1 & MIPS_CONF1_WR) 669 c->options |= MIPS_CPU_WATCH; 670 if (config1 & MIPS_CONF1_CA) 671 c->ases |= MIPS_ASE_MIPS16; 672 if (config1 & MIPS_CONF1_EP) 673 c->options |= MIPS_CPU_EJTAG; 674 if (config1 & MIPS_CONF1_FP) { 675 c->options |= MIPS_CPU_FPU; 676 c->options |= MIPS_CPU_32FPR; 677 } 678 if (cpu_has_tlb) { 679 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 680 c->tlbsizevtlb = c->tlbsize; 681 c->tlbsizeftlbsets = 0; 682 } 683 684 return config1 & MIPS_CONF_M; 685 } 686 687 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 688 { 689 unsigned int config2; 690 691 config2 = read_c0_config2(); 692 693 if (config2 & MIPS_CONF2_SL) 694 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 695 696 return config2 & MIPS_CONF_M; 697 } 698 699 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 700 { 701 unsigned int config3; 702 703 config3 = read_c0_config3(); 704 705 if (config3 & MIPS_CONF3_SM) { 706 c->ases |= MIPS_ASE_SMARTMIPS; 707 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 708 } 709 if (config3 & MIPS_CONF3_RXI) 710 c->options |= MIPS_CPU_RIXI; 711 if (config3 & MIPS_CONF3_CTXTC) 712 c->options |= MIPS_CPU_CTXTC; 713 if (config3 & MIPS_CONF3_DSP) 714 c->ases |= MIPS_ASE_DSP; 715 if (config3 & MIPS_CONF3_DSP2P) { 716 c->ases |= MIPS_ASE_DSP2P; 717 if (cpu_has_mips_r6) 718 c->ases |= MIPS_ASE_DSP3; 719 } 720 if (config3 & MIPS_CONF3_VINT) 721 c->options |= MIPS_CPU_VINT; 722 if (config3 & MIPS_CONF3_VEIC) 723 c->options |= MIPS_CPU_VEIC; 724 if (config3 & MIPS_CONF3_LPA) 725 c->options |= MIPS_CPU_LPA; 726 if (config3 & MIPS_CONF3_MT) 727 c->ases |= MIPS_ASE_MIPSMT; 728 if (config3 & MIPS_CONF3_ULRI) 729 c->options |= MIPS_CPU_ULRI; 730 if (config3 & MIPS_CONF3_ISA) 731 c->options |= MIPS_CPU_MICROMIPS; 732 if (config3 & MIPS_CONF3_VZ) 733 c->ases |= MIPS_ASE_VZ; 734 if (config3 & MIPS_CONF3_SC) 735 c->options |= MIPS_CPU_SEGMENTS; 736 if (config3 & MIPS_CONF3_BI) 737 c->options |= MIPS_CPU_BADINSTR; 738 if (config3 & MIPS_CONF3_BP) 739 c->options |= MIPS_CPU_BADINSTRP; 740 if (config3 & MIPS_CONF3_MSA) 741 c->ases |= MIPS_ASE_MSA; 742 if (config3 & MIPS_CONF3_PW) { 743 c->htw_seq = 0; 744 c->options |= MIPS_CPU_HTW; 745 } 746 if (config3 & MIPS_CONF3_CDMM) 747 c->options |= MIPS_CPU_CDMM; 748 if (config3 & MIPS_CONF3_SP) 749 c->options |= MIPS_CPU_SP; 750 751 return config3 & MIPS_CONF_M; 752 } 753 754 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 755 { 756 unsigned int config4; 757 unsigned int newcf4; 758 unsigned int mmuextdef; 759 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 760 unsigned long asid_mask; 761 762 config4 = read_c0_config4(); 763 764 if (cpu_has_tlb) { 765 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 766 c->options |= MIPS_CPU_TLBINV; 767 768 /* 769 * R6 has dropped the MMUExtDef field from config4. 770 * On R6 the fields always describe the FTLB, and only if it is 771 * present according to Config.MT. 772 */ 773 if (!cpu_has_mips_r6) 774 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 775 else if (cpu_has_ftlb) 776 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 777 else 778 mmuextdef = 0; 779 780 switch (mmuextdef) { 781 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 782 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 783 c->tlbsizevtlb = c->tlbsize; 784 break; 785 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 786 c->tlbsizevtlb += 787 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 788 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 789 c->tlbsize = c->tlbsizevtlb; 790 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 791 /* fall through */ 792 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 793 if (mips_ftlb_disabled) 794 break; 795 newcf4 = (config4 & ~ftlb_page) | 796 (page_size_ftlb(mmuextdef) << 797 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 798 write_c0_config4(newcf4); 799 back_to_back_c0_hazard(); 800 config4 = read_c0_config4(); 801 if (config4 != newcf4) { 802 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 803 PAGE_SIZE, config4); 804 /* Switch FTLB off */ 805 set_ftlb_enable(c, 0); 806 mips_ftlb_disabled = 1; 807 break; 808 } 809 c->tlbsizeftlbsets = 1 << 810 ((config4 & MIPS_CONF4_FTLBSETS) >> 811 MIPS_CONF4_FTLBSETS_SHIFT); 812 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 813 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 814 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 815 mips_has_ftlb_configured = 1; 816 break; 817 } 818 } 819 820 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 821 >> MIPS_CONF4_KSCREXIST_SHIFT; 822 823 asid_mask = MIPS_ENTRYHI_ASID; 824 if (config4 & MIPS_CONF4_AE) 825 asid_mask |= MIPS_ENTRYHI_ASIDX; 826 set_cpu_asid_mask(c, asid_mask); 827 828 /* 829 * Warn if the computed ASID mask doesn't match the mask the kernel 830 * is built for. This may indicate either a serious problem or an 831 * easy optimisation opportunity, but either way should be addressed. 832 */ 833 WARN_ON(asid_mask != cpu_asid_mask(c)); 834 835 return config4 & MIPS_CONF_M; 836 } 837 838 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 839 { 840 unsigned int config5; 841 842 config5 = read_c0_config5(); 843 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 844 write_c0_config5(config5); 845 846 if (config5 & MIPS_CONF5_EVA) 847 c->options |= MIPS_CPU_EVA; 848 if (config5 & MIPS_CONF5_MRP) 849 c->options |= MIPS_CPU_MAAR; 850 if (config5 & MIPS_CONF5_LLB) 851 c->options |= MIPS_CPU_RW_LLB; 852 if (config5 & MIPS_CONF5_MVH) 853 c->options |= MIPS_CPU_MVH; 854 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 855 c->options |= MIPS_CPU_VP; 856 if (config5 & MIPS_CONF5_CA2) 857 c->ases |= MIPS_ASE_MIPS16E2; 858 859 if (config5 & MIPS_CONF5_CRCP) 860 elf_hwcap |= HWCAP_MIPS_CRC32; 861 862 return config5 & MIPS_CONF_M; 863 } 864 865 static void decode_configs(struct cpuinfo_mips *c) 866 { 867 int ok; 868 869 /* MIPS32 or MIPS64 compliant CPU. */ 870 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 871 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 872 873 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 874 875 /* Enable FTLB if present and not disabled */ 876 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 877 878 ok = decode_config0(c); /* Read Config registers. */ 879 BUG_ON(!ok); /* Arch spec violation! */ 880 if (ok) 881 ok = decode_config1(c); 882 if (ok) 883 ok = decode_config2(c); 884 if (ok) 885 ok = decode_config3(c); 886 if (ok) 887 ok = decode_config4(c); 888 if (ok) 889 ok = decode_config5(c); 890 891 /* Probe the EBase.WG bit */ 892 if (cpu_has_mips_r2_r6) { 893 u64 ebase; 894 unsigned int status; 895 896 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 897 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 898 : (s32)read_c0_ebase(); 899 if (ebase & MIPS_EBASE_WG) { 900 /* WG bit already set, we can avoid the clumsy probe */ 901 c->options |= MIPS_CPU_EBASE_WG; 902 } else { 903 /* Its UNDEFINED to change EBase while BEV=0 */ 904 status = read_c0_status(); 905 write_c0_status(status | ST0_BEV); 906 irq_enable_hazard(); 907 /* 908 * On pre-r6 cores, this may well clobber the upper bits 909 * of EBase. This is hard to avoid without potentially 910 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 911 */ 912 if (cpu_has_mips64r6) 913 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 914 else 915 write_c0_ebase(ebase | MIPS_EBASE_WG); 916 back_to_back_c0_hazard(); 917 /* Restore BEV */ 918 write_c0_status(status); 919 if (read_c0_ebase() & MIPS_EBASE_WG) { 920 c->options |= MIPS_CPU_EBASE_WG; 921 write_c0_ebase(ebase); 922 } 923 } 924 } 925 926 /* configure the FTLB write probability */ 927 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 928 929 mips_probe_watch_registers(c); 930 931 #ifndef CONFIG_MIPS_CPS 932 if (cpu_has_mips_r2_r6) { 933 unsigned int core; 934 935 core = get_ebase_cpunum(); 936 if (cpu_has_mipsmt) 937 core >>= fls(core_nvpes()) - 1; 938 cpu_set_core(c, core); 939 } 940 #endif 941 } 942 943 /* 944 * Probe for certain guest capabilities by writing config bits and reading back. 945 * Finally write back the original value. 946 */ 947 #define probe_gc0_config(name, maxconf, bits) \ 948 do { \ 949 unsigned int tmp; \ 950 tmp = read_gc0_##name(); \ 951 write_gc0_##name(tmp | (bits)); \ 952 back_to_back_c0_hazard(); \ 953 maxconf = read_gc0_##name(); \ 954 write_gc0_##name(tmp); \ 955 } while (0) 956 957 /* 958 * Probe for dynamic guest capabilities by changing certain config bits and 959 * reading back to see if they change. Finally write back the original value. 960 */ 961 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 962 do { \ 963 maxconf = read_gc0_##name(); \ 964 write_gc0_##name(maxconf ^ (bits)); \ 965 back_to_back_c0_hazard(); \ 966 dynconf = maxconf ^ read_gc0_##name(); \ 967 write_gc0_##name(maxconf); \ 968 maxconf |= dynconf; \ 969 } while (0) 970 971 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 972 { 973 unsigned int config0; 974 975 probe_gc0_config(config, config0, MIPS_CONF_M); 976 977 if (config0 & MIPS_CONF_M) 978 c->guest.conf |= BIT(1); 979 return config0 & MIPS_CONF_M; 980 } 981 982 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 983 { 984 unsigned int config1, config1_dyn; 985 986 probe_gc0_config_dyn(config1, config1, config1_dyn, 987 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 988 MIPS_CONF1_FP); 989 990 if (config1 & MIPS_CONF1_FP) 991 c->guest.options |= MIPS_CPU_FPU; 992 if (config1_dyn & MIPS_CONF1_FP) 993 c->guest.options_dyn |= MIPS_CPU_FPU; 994 995 if (config1 & MIPS_CONF1_WR) 996 c->guest.options |= MIPS_CPU_WATCH; 997 if (config1_dyn & MIPS_CONF1_WR) 998 c->guest.options_dyn |= MIPS_CPU_WATCH; 999 1000 if (config1 & MIPS_CONF1_PC) 1001 c->guest.options |= MIPS_CPU_PERF; 1002 if (config1_dyn & MIPS_CONF1_PC) 1003 c->guest.options_dyn |= MIPS_CPU_PERF; 1004 1005 if (config1 & MIPS_CONF_M) 1006 c->guest.conf |= BIT(2); 1007 return config1 & MIPS_CONF_M; 1008 } 1009 1010 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 1011 { 1012 unsigned int config2; 1013 1014 probe_gc0_config(config2, config2, MIPS_CONF_M); 1015 1016 if (config2 & MIPS_CONF_M) 1017 c->guest.conf |= BIT(3); 1018 return config2 & MIPS_CONF_M; 1019 } 1020 1021 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 1022 { 1023 unsigned int config3, config3_dyn; 1024 1025 probe_gc0_config_dyn(config3, config3, config3_dyn, 1026 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 1027 MIPS_CONF3_CTXTC); 1028 1029 if (config3 & MIPS_CONF3_CTXTC) 1030 c->guest.options |= MIPS_CPU_CTXTC; 1031 if (config3_dyn & MIPS_CONF3_CTXTC) 1032 c->guest.options_dyn |= MIPS_CPU_CTXTC; 1033 1034 if (config3 & MIPS_CONF3_PW) 1035 c->guest.options |= MIPS_CPU_HTW; 1036 1037 if (config3 & MIPS_CONF3_ULRI) 1038 c->guest.options |= MIPS_CPU_ULRI; 1039 1040 if (config3 & MIPS_CONF3_SC) 1041 c->guest.options |= MIPS_CPU_SEGMENTS; 1042 1043 if (config3 & MIPS_CONF3_BI) 1044 c->guest.options |= MIPS_CPU_BADINSTR; 1045 if (config3 & MIPS_CONF3_BP) 1046 c->guest.options |= MIPS_CPU_BADINSTRP; 1047 1048 if (config3 & MIPS_CONF3_MSA) 1049 c->guest.ases |= MIPS_ASE_MSA; 1050 if (config3_dyn & MIPS_CONF3_MSA) 1051 c->guest.ases_dyn |= MIPS_ASE_MSA; 1052 1053 if (config3 & MIPS_CONF_M) 1054 c->guest.conf |= BIT(4); 1055 return config3 & MIPS_CONF_M; 1056 } 1057 1058 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 1059 { 1060 unsigned int config4; 1061 1062 probe_gc0_config(config4, config4, 1063 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 1064 1065 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 1066 >> MIPS_CONF4_KSCREXIST_SHIFT; 1067 1068 if (config4 & MIPS_CONF_M) 1069 c->guest.conf |= BIT(5); 1070 return config4 & MIPS_CONF_M; 1071 } 1072 1073 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 1074 { 1075 unsigned int config5, config5_dyn; 1076 1077 probe_gc0_config_dyn(config5, config5, config5_dyn, 1078 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 1079 1080 if (config5 & MIPS_CONF5_MRP) 1081 c->guest.options |= MIPS_CPU_MAAR; 1082 if (config5_dyn & MIPS_CONF5_MRP) 1083 c->guest.options_dyn |= MIPS_CPU_MAAR; 1084 1085 if (config5 & MIPS_CONF5_LLB) 1086 c->guest.options |= MIPS_CPU_RW_LLB; 1087 1088 if (config5 & MIPS_CONF5_MVH) 1089 c->guest.options |= MIPS_CPU_MVH; 1090 1091 if (config5 & MIPS_CONF_M) 1092 c->guest.conf |= BIT(6); 1093 return config5 & MIPS_CONF_M; 1094 } 1095 1096 static inline void decode_guest_configs(struct cpuinfo_mips *c) 1097 { 1098 unsigned int ok; 1099 1100 ok = decode_guest_config0(c); 1101 if (ok) 1102 ok = decode_guest_config1(c); 1103 if (ok) 1104 ok = decode_guest_config2(c); 1105 if (ok) 1106 ok = decode_guest_config3(c); 1107 if (ok) 1108 ok = decode_guest_config4(c); 1109 if (ok) 1110 decode_guest_config5(c); 1111 } 1112 1113 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 1114 { 1115 unsigned int guestctl0, temp; 1116 1117 guestctl0 = read_c0_guestctl0(); 1118 1119 if (guestctl0 & MIPS_GCTL0_G0E) 1120 c->options |= MIPS_CPU_GUESTCTL0EXT; 1121 if (guestctl0 & MIPS_GCTL0_G1) 1122 c->options |= MIPS_CPU_GUESTCTL1; 1123 if (guestctl0 & MIPS_GCTL0_G2) 1124 c->options |= MIPS_CPU_GUESTCTL2; 1125 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 1126 c->options |= MIPS_CPU_GUESTID; 1127 1128 /* 1129 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 1130 * first, otherwise all data accesses will be fully virtualised 1131 * as if they were performed by guest mode. 1132 */ 1133 write_c0_guestctl1(0); 1134 tlbw_use_hazard(); 1135 1136 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 1137 back_to_back_c0_hazard(); 1138 temp = read_c0_guestctl0(); 1139 1140 if (temp & MIPS_GCTL0_DRG) { 1141 write_c0_guestctl0(guestctl0); 1142 c->options |= MIPS_CPU_DRG; 1143 } 1144 } 1145 } 1146 1147 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1148 { 1149 if (cpu_has_guestid) { 1150 /* determine the number of bits of GuestID available */ 1151 write_c0_guestctl1(MIPS_GCTL1_ID); 1152 back_to_back_c0_hazard(); 1153 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1154 >> MIPS_GCTL1_ID_SHIFT; 1155 write_c0_guestctl1(0); 1156 } 1157 } 1158 1159 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1160 { 1161 /* determine the number of bits of GTOffset available */ 1162 write_c0_gtoffset(0xffffffff); 1163 back_to_back_c0_hazard(); 1164 c->gtoffset_mask = read_c0_gtoffset(); 1165 write_c0_gtoffset(0); 1166 } 1167 1168 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1169 { 1170 cpu_probe_guestctl0(c); 1171 if (cpu_has_guestctl1) 1172 cpu_probe_guestctl1(c); 1173 1174 cpu_probe_gtoffset(c); 1175 1176 decode_guest_configs(c); 1177 } 1178 1179 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1180 | MIPS_CPU_COUNTER) 1181 1182 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1183 { 1184 switch (c->processor_id & PRID_IMP_MASK) { 1185 case PRID_IMP_R2000: 1186 c->cputype = CPU_R2000; 1187 __cpu_name[cpu] = "R2000"; 1188 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1189 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1190 MIPS_CPU_NOFPUEX; 1191 if (__cpu_has_fpu()) 1192 c->options |= MIPS_CPU_FPU; 1193 c->tlbsize = 64; 1194 break; 1195 case PRID_IMP_R3000: 1196 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1197 if (cpu_has_confreg()) { 1198 c->cputype = CPU_R3081E; 1199 __cpu_name[cpu] = "R3081"; 1200 } else { 1201 c->cputype = CPU_R3000A; 1202 __cpu_name[cpu] = "R3000A"; 1203 } 1204 } else { 1205 c->cputype = CPU_R3000; 1206 __cpu_name[cpu] = "R3000"; 1207 } 1208 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1209 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1210 MIPS_CPU_NOFPUEX; 1211 if (__cpu_has_fpu()) 1212 c->options |= MIPS_CPU_FPU; 1213 c->tlbsize = 64; 1214 break; 1215 case PRID_IMP_R4000: 1216 if (read_c0_config() & CONF_SC) { 1217 if ((c->processor_id & PRID_REV_MASK) >= 1218 PRID_REV_R4400) { 1219 c->cputype = CPU_R4400PC; 1220 __cpu_name[cpu] = "R4400PC"; 1221 } else { 1222 c->cputype = CPU_R4000PC; 1223 __cpu_name[cpu] = "R4000PC"; 1224 } 1225 } else { 1226 int cca = read_c0_config() & CONF_CM_CMASK; 1227 int mc; 1228 1229 /* 1230 * SC and MC versions can't be reliably told apart, 1231 * but only the latter support coherent caching 1232 * modes so assume the firmware has set the KSEG0 1233 * coherency attribute reasonably (if uncached, we 1234 * assume SC). 1235 */ 1236 switch (cca) { 1237 case CONF_CM_CACHABLE_CE: 1238 case CONF_CM_CACHABLE_COW: 1239 case CONF_CM_CACHABLE_CUW: 1240 mc = 1; 1241 break; 1242 default: 1243 mc = 0; 1244 break; 1245 } 1246 if ((c->processor_id & PRID_REV_MASK) >= 1247 PRID_REV_R4400) { 1248 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1249 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1250 } else { 1251 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1252 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1253 } 1254 } 1255 1256 set_isa(c, MIPS_CPU_ISA_III); 1257 c->fpu_msk31 |= FPU_CSR_CONDX; 1258 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1259 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1260 MIPS_CPU_LLSC; 1261 c->tlbsize = 48; 1262 break; 1263 case PRID_IMP_VR41XX: 1264 set_isa(c, MIPS_CPU_ISA_III); 1265 c->fpu_msk31 |= FPU_CSR_CONDX; 1266 c->options = R4K_OPTS; 1267 c->tlbsize = 32; 1268 switch (c->processor_id & 0xf0) { 1269 case PRID_REV_VR4111: 1270 c->cputype = CPU_VR4111; 1271 __cpu_name[cpu] = "NEC VR4111"; 1272 break; 1273 case PRID_REV_VR4121: 1274 c->cputype = CPU_VR4121; 1275 __cpu_name[cpu] = "NEC VR4121"; 1276 break; 1277 case PRID_REV_VR4122: 1278 if ((c->processor_id & 0xf) < 0x3) { 1279 c->cputype = CPU_VR4122; 1280 __cpu_name[cpu] = "NEC VR4122"; 1281 } else { 1282 c->cputype = CPU_VR4181A; 1283 __cpu_name[cpu] = "NEC VR4181A"; 1284 } 1285 break; 1286 case PRID_REV_VR4130: 1287 if ((c->processor_id & 0xf) < 0x4) { 1288 c->cputype = CPU_VR4131; 1289 __cpu_name[cpu] = "NEC VR4131"; 1290 } else { 1291 c->cputype = CPU_VR4133; 1292 c->options |= MIPS_CPU_LLSC; 1293 __cpu_name[cpu] = "NEC VR4133"; 1294 } 1295 break; 1296 default: 1297 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1298 c->cputype = CPU_VR41XX; 1299 __cpu_name[cpu] = "NEC Vr41xx"; 1300 break; 1301 } 1302 break; 1303 case PRID_IMP_R4300: 1304 c->cputype = CPU_R4300; 1305 __cpu_name[cpu] = "R4300"; 1306 set_isa(c, MIPS_CPU_ISA_III); 1307 c->fpu_msk31 |= FPU_CSR_CONDX; 1308 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1309 MIPS_CPU_LLSC; 1310 c->tlbsize = 32; 1311 break; 1312 case PRID_IMP_R4600: 1313 c->cputype = CPU_R4600; 1314 __cpu_name[cpu] = "R4600"; 1315 set_isa(c, MIPS_CPU_ISA_III); 1316 c->fpu_msk31 |= FPU_CSR_CONDX; 1317 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1318 MIPS_CPU_LLSC; 1319 c->tlbsize = 48; 1320 break; 1321 #if 0 1322 case PRID_IMP_R4650: 1323 /* 1324 * This processor doesn't have an MMU, so it's not 1325 * "real easy" to run Linux on it. It is left purely 1326 * for documentation. Commented out because it shares 1327 * it's c0_prid id number with the TX3900. 1328 */ 1329 c->cputype = CPU_R4650; 1330 __cpu_name[cpu] = "R4650"; 1331 set_isa(c, MIPS_CPU_ISA_III); 1332 c->fpu_msk31 |= FPU_CSR_CONDX; 1333 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1334 c->tlbsize = 48; 1335 break; 1336 #endif 1337 case PRID_IMP_TX39: 1338 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1339 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1340 1341 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1342 c->cputype = CPU_TX3927; 1343 __cpu_name[cpu] = "TX3927"; 1344 c->tlbsize = 64; 1345 } else { 1346 switch (c->processor_id & PRID_REV_MASK) { 1347 case PRID_REV_TX3912: 1348 c->cputype = CPU_TX3912; 1349 __cpu_name[cpu] = "TX3912"; 1350 c->tlbsize = 32; 1351 break; 1352 case PRID_REV_TX3922: 1353 c->cputype = CPU_TX3922; 1354 __cpu_name[cpu] = "TX3922"; 1355 c->tlbsize = 64; 1356 break; 1357 } 1358 } 1359 break; 1360 case PRID_IMP_R4700: 1361 c->cputype = CPU_R4700; 1362 __cpu_name[cpu] = "R4700"; 1363 set_isa(c, MIPS_CPU_ISA_III); 1364 c->fpu_msk31 |= FPU_CSR_CONDX; 1365 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1366 MIPS_CPU_LLSC; 1367 c->tlbsize = 48; 1368 break; 1369 case PRID_IMP_TX49: 1370 c->cputype = CPU_TX49XX; 1371 __cpu_name[cpu] = "R49XX"; 1372 set_isa(c, MIPS_CPU_ISA_III); 1373 c->fpu_msk31 |= FPU_CSR_CONDX; 1374 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1375 if (!(c->processor_id & 0x08)) 1376 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1377 c->tlbsize = 48; 1378 break; 1379 case PRID_IMP_R5000: 1380 c->cputype = CPU_R5000; 1381 __cpu_name[cpu] = "R5000"; 1382 set_isa(c, MIPS_CPU_ISA_IV); 1383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1384 MIPS_CPU_LLSC; 1385 c->tlbsize = 48; 1386 break; 1387 case PRID_IMP_R5432: 1388 c->cputype = CPU_R5432; 1389 __cpu_name[cpu] = "R5432"; 1390 set_isa(c, MIPS_CPU_ISA_IV); 1391 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1392 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1393 c->tlbsize = 48; 1394 break; 1395 case PRID_IMP_R5500: 1396 c->cputype = CPU_R5500; 1397 __cpu_name[cpu] = "R5500"; 1398 set_isa(c, MIPS_CPU_ISA_IV); 1399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1400 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1401 c->tlbsize = 48; 1402 break; 1403 case PRID_IMP_NEVADA: 1404 c->cputype = CPU_NEVADA; 1405 __cpu_name[cpu] = "Nevada"; 1406 set_isa(c, MIPS_CPU_ISA_IV); 1407 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1408 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1409 c->tlbsize = 48; 1410 break; 1411 case PRID_IMP_RM7000: 1412 c->cputype = CPU_RM7000; 1413 __cpu_name[cpu] = "RM7000"; 1414 set_isa(c, MIPS_CPU_ISA_IV); 1415 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1416 MIPS_CPU_LLSC; 1417 /* 1418 * Undocumented RM7000: Bit 29 in the info register of 1419 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1420 * entries. 1421 * 1422 * 29 1 => 64 entry JTLB 1423 * 0 => 48 entry JTLB 1424 */ 1425 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1426 break; 1427 case PRID_IMP_R8000: 1428 c->cputype = CPU_R8000; 1429 __cpu_name[cpu] = "RM8000"; 1430 set_isa(c, MIPS_CPU_ISA_IV); 1431 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 1432 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1433 MIPS_CPU_LLSC; 1434 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 1435 break; 1436 case PRID_IMP_R10000: 1437 c->cputype = CPU_R10000; 1438 __cpu_name[cpu] = "R10000"; 1439 set_isa(c, MIPS_CPU_ISA_IV); 1440 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1441 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1442 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1443 MIPS_CPU_LLSC; 1444 c->tlbsize = 64; 1445 break; 1446 case PRID_IMP_R12000: 1447 c->cputype = CPU_R12000; 1448 __cpu_name[cpu] = "R12000"; 1449 set_isa(c, MIPS_CPU_ISA_IV); 1450 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1451 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1452 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1453 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1454 c->tlbsize = 64; 1455 break; 1456 case PRID_IMP_R14000: 1457 if (((c->processor_id >> 4) & 0x0f) > 2) { 1458 c->cputype = CPU_R16000; 1459 __cpu_name[cpu] = "R16000"; 1460 } else { 1461 c->cputype = CPU_R14000; 1462 __cpu_name[cpu] = "R14000"; 1463 } 1464 set_isa(c, MIPS_CPU_ISA_IV); 1465 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1466 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1467 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1468 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1469 c->tlbsize = 64; 1470 break; 1471 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1472 switch (c->processor_id & PRID_REV_MASK) { 1473 case PRID_REV_LOONGSON2E: 1474 c->cputype = CPU_LOONGSON2; 1475 __cpu_name[cpu] = "ICT Loongson-2"; 1476 set_elf_platform(cpu, "loongson2e"); 1477 set_isa(c, MIPS_CPU_ISA_III); 1478 c->fpu_msk31 |= FPU_CSR_CONDX; 1479 break; 1480 case PRID_REV_LOONGSON2F: 1481 c->cputype = CPU_LOONGSON2; 1482 __cpu_name[cpu] = "ICT Loongson-2"; 1483 set_elf_platform(cpu, "loongson2f"); 1484 set_isa(c, MIPS_CPU_ISA_III); 1485 c->fpu_msk31 |= FPU_CSR_CONDX; 1486 break; 1487 case PRID_REV_LOONGSON3A_R1: 1488 c->cputype = CPU_LOONGSON3; 1489 __cpu_name[cpu] = "ICT Loongson-3"; 1490 set_elf_platform(cpu, "loongson3a"); 1491 set_isa(c, MIPS_CPU_ISA_M64R1); 1492 break; 1493 case PRID_REV_LOONGSON3B_R1: 1494 case PRID_REV_LOONGSON3B_R2: 1495 c->cputype = CPU_LOONGSON3; 1496 __cpu_name[cpu] = "ICT Loongson-3"; 1497 set_elf_platform(cpu, "loongson3b"); 1498 set_isa(c, MIPS_CPU_ISA_M64R1); 1499 break; 1500 } 1501 1502 c->options = R4K_OPTS | 1503 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1504 MIPS_CPU_32FPR; 1505 c->tlbsize = 64; 1506 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1507 break; 1508 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1509 decode_configs(c); 1510 1511 c->cputype = CPU_LOONGSON1; 1512 1513 switch (c->processor_id & PRID_REV_MASK) { 1514 case PRID_REV_LOONGSON1B: 1515 __cpu_name[cpu] = "Loongson 1B"; 1516 break; 1517 } 1518 1519 break; 1520 } 1521 } 1522 1523 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1524 { 1525 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1526 switch (c->processor_id & PRID_IMP_MASK) { 1527 case PRID_IMP_QEMU_GENERIC: 1528 c->writecombine = _CACHE_UNCACHED; 1529 c->cputype = CPU_QEMU_GENERIC; 1530 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1531 break; 1532 case PRID_IMP_4KC: 1533 c->cputype = CPU_4KC; 1534 c->writecombine = _CACHE_UNCACHED; 1535 __cpu_name[cpu] = "MIPS 4Kc"; 1536 break; 1537 case PRID_IMP_4KEC: 1538 case PRID_IMP_4KECR2: 1539 c->cputype = CPU_4KEC; 1540 c->writecombine = _CACHE_UNCACHED; 1541 __cpu_name[cpu] = "MIPS 4KEc"; 1542 break; 1543 case PRID_IMP_4KSC: 1544 case PRID_IMP_4KSD: 1545 c->cputype = CPU_4KSC; 1546 c->writecombine = _CACHE_UNCACHED; 1547 __cpu_name[cpu] = "MIPS 4KSc"; 1548 break; 1549 case PRID_IMP_5KC: 1550 c->cputype = CPU_5KC; 1551 c->writecombine = _CACHE_UNCACHED; 1552 __cpu_name[cpu] = "MIPS 5Kc"; 1553 break; 1554 case PRID_IMP_5KE: 1555 c->cputype = CPU_5KE; 1556 c->writecombine = _CACHE_UNCACHED; 1557 __cpu_name[cpu] = "MIPS 5KE"; 1558 break; 1559 case PRID_IMP_20KC: 1560 c->cputype = CPU_20KC; 1561 c->writecombine = _CACHE_UNCACHED; 1562 __cpu_name[cpu] = "MIPS 20Kc"; 1563 break; 1564 case PRID_IMP_24K: 1565 c->cputype = CPU_24K; 1566 c->writecombine = _CACHE_UNCACHED; 1567 __cpu_name[cpu] = "MIPS 24Kc"; 1568 break; 1569 case PRID_IMP_24KE: 1570 c->cputype = CPU_24K; 1571 c->writecombine = _CACHE_UNCACHED; 1572 __cpu_name[cpu] = "MIPS 24KEc"; 1573 break; 1574 case PRID_IMP_25KF: 1575 c->cputype = CPU_25KF; 1576 c->writecombine = _CACHE_UNCACHED; 1577 __cpu_name[cpu] = "MIPS 25Kc"; 1578 break; 1579 case PRID_IMP_34K: 1580 c->cputype = CPU_34K; 1581 c->writecombine = _CACHE_UNCACHED; 1582 __cpu_name[cpu] = "MIPS 34Kc"; 1583 cpu_set_mt_per_tc_perf(c); 1584 break; 1585 case PRID_IMP_74K: 1586 c->cputype = CPU_74K; 1587 c->writecombine = _CACHE_UNCACHED; 1588 __cpu_name[cpu] = "MIPS 74Kc"; 1589 break; 1590 case PRID_IMP_M14KC: 1591 c->cputype = CPU_M14KC; 1592 c->writecombine = _CACHE_UNCACHED; 1593 __cpu_name[cpu] = "MIPS M14Kc"; 1594 break; 1595 case PRID_IMP_M14KEC: 1596 c->cputype = CPU_M14KEC; 1597 c->writecombine = _CACHE_UNCACHED; 1598 __cpu_name[cpu] = "MIPS M14KEc"; 1599 break; 1600 case PRID_IMP_1004K: 1601 c->cputype = CPU_1004K; 1602 c->writecombine = _CACHE_UNCACHED; 1603 __cpu_name[cpu] = "MIPS 1004Kc"; 1604 cpu_set_mt_per_tc_perf(c); 1605 break; 1606 case PRID_IMP_1074K: 1607 c->cputype = CPU_1074K; 1608 c->writecombine = _CACHE_UNCACHED; 1609 __cpu_name[cpu] = "MIPS 1074Kc"; 1610 break; 1611 case PRID_IMP_INTERAPTIV_UP: 1612 c->cputype = CPU_INTERAPTIV; 1613 __cpu_name[cpu] = "MIPS interAptiv"; 1614 cpu_set_mt_per_tc_perf(c); 1615 break; 1616 case PRID_IMP_INTERAPTIV_MP: 1617 c->cputype = CPU_INTERAPTIV; 1618 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1619 cpu_set_mt_per_tc_perf(c); 1620 break; 1621 case PRID_IMP_PROAPTIV_UP: 1622 c->cputype = CPU_PROAPTIV; 1623 __cpu_name[cpu] = "MIPS proAptiv"; 1624 break; 1625 case PRID_IMP_PROAPTIV_MP: 1626 c->cputype = CPU_PROAPTIV; 1627 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1628 break; 1629 case PRID_IMP_P5600: 1630 c->cputype = CPU_P5600; 1631 __cpu_name[cpu] = "MIPS P5600"; 1632 break; 1633 case PRID_IMP_P6600: 1634 c->cputype = CPU_P6600; 1635 __cpu_name[cpu] = "MIPS P6600"; 1636 break; 1637 case PRID_IMP_I6400: 1638 c->cputype = CPU_I6400; 1639 __cpu_name[cpu] = "MIPS I6400"; 1640 break; 1641 case PRID_IMP_I6500: 1642 c->cputype = CPU_I6500; 1643 __cpu_name[cpu] = "MIPS I6500"; 1644 break; 1645 case PRID_IMP_M5150: 1646 c->cputype = CPU_M5150; 1647 __cpu_name[cpu] = "MIPS M5150"; 1648 break; 1649 case PRID_IMP_M6250: 1650 c->cputype = CPU_M6250; 1651 __cpu_name[cpu] = "MIPS M6250"; 1652 break; 1653 } 1654 1655 decode_configs(c); 1656 1657 spram_config(); 1658 1659 switch (__get_cpu_type(c->cputype)) { 1660 case CPU_I6500: 1661 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1662 /* fall-through */ 1663 case CPU_I6400: 1664 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1665 /* fall-through */ 1666 default: 1667 break; 1668 } 1669 } 1670 1671 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1672 { 1673 decode_configs(c); 1674 switch (c->processor_id & PRID_IMP_MASK) { 1675 case PRID_IMP_AU1_REV1: 1676 case PRID_IMP_AU1_REV2: 1677 c->cputype = CPU_ALCHEMY; 1678 switch ((c->processor_id >> 24) & 0xff) { 1679 case 0: 1680 __cpu_name[cpu] = "Au1000"; 1681 break; 1682 case 1: 1683 __cpu_name[cpu] = "Au1500"; 1684 break; 1685 case 2: 1686 __cpu_name[cpu] = "Au1100"; 1687 break; 1688 case 3: 1689 __cpu_name[cpu] = "Au1550"; 1690 break; 1691 case 4: 1692 __cpu_name[cpu] = "Au1200"; 1693 if ((c->processor_id & PRID_REV_MASK) == 2) 1694 __cpu_name[cpu] = "Au1250"; 1695 break; 1696 case 5: 1697 __cpu_name[cpu] = "Au1210"; 1698 break; 1699 default: 1700 __cpu_name[cpu] = "Au1xxx"; 1701 break; 1702 } 1703 break; 1704 } 1705 } 1706 1707 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1708 { 1709 decode_configs(c); 1710 1711 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1712 switch (c->processor_id & PRID_IMP_MASK) { 1713 case PRID_IMP_SB1: 1714 c->cputype = CPU_SB1; 1715 __cpu_name[cpu] = "SiByte SB1"; 1716 /* FPU in pass1 is known to have issues. */ 1717 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1718 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1719 break; 1720 case PRID_IMP_SB1A: 1721 c->cputype = CPU_SB1A; 1722 __cpu_name[cpu] = "SiByte SB1A"; 1723 break; 1724 } 1725 } 1726 1727 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1728 { 1729 decode_configs(c); 1730 switch (c->processor_id & PRID_IMP_MASK) { 1731 case PRID_IMP_SR71000: 1732 c->cputype = CPU_SR71000; 1733 __cpu_name[cpu] = "Sandcraft SR71000"; 1734 c->scache.ways = 8; 1735 c->tlbsize = 64; 1736 break; 1737 } 1738 } 1739 1740 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1741 { 1742 decode_configs(c); 1743 switch (c->processor_id & PRID_IMP_MASK) { 1744 case PRID_IMP_PR4450: 1745 c->cputype = CPU_PR4450; 1746 __cpu_name[cpu] = "Philips PR4450"; 1747 set_isa(c, MIPS_CPU_ISA_M32R1); 1748 break; 1749 } 1750 } 1751 1752 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1753 { 1754 decode_configs(c); 1755 switch (c->processor_id & PRID_IMP_MASK) { 1756 case PRID_IMP_BMIPS32_REV4: 1757 case PRID_IMP_BMIPS32_REV8: 1758 c->cputype = CPU_BMIPS32; 1759 __cpu_name[cpu] = "Broadcom BMIPS32"; 1760 set_elf_platform(cpu, "bmips32"); 1761 break; 1762 case PRID_IMP_BMIPS3300: 1763 case PRID_IMP_BMIPS3300_ALT: 1764 case PRID_IMP_BMIPS3300_BUG: 1765 c->cputype = CPU_BMIPS3300; 1766 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1767 set_elf_platform(cpu, "bmips3300"); 1768 break; 1769 case PRID_IMP_BMIPS43XX: { 1770 int rev = c->processor_id & PRID_REV_MASK; 1771 1772 if (rev >= PRID_REV_BMIPS4380_LO && 1773 rev <= PRID_REV_BMIPS4380_HI) { 1774 c->cputype = CPU_BMIPS4380; 1775 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1776 set_elf_platform(cpu, "bmips4380"); 1777 c->options |= MIPS_CPU_RIXI; 1778 } else { 1779 c->cputype = CPU_BMIPS4350; 1780 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1781 set_elf_platform(cpu, "bmips4350"); 1782 } 1783 break; 1784 } 1785 case PRID_IMP_BMIPS5000: 1786 case PRID_IMP_BMIPS5200: 1787 c->cputype = CPU_BMIPS5000; 1788 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1789 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1790 else 1791 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1792 set_elf_platform(cpu, "bmips5000"); 1793 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1794 break; 1795 } 1796 } 1797 1798 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1799 { 1800 decode_configs(c); 1801 switch (c->processor_id & PRID_IMP_MASK) { 1802 case PRID_IMP_CAVIUM_CN38XX: 1803 case PRID_IMP_CAVIUM_CN31XX: 1804 case PRID_IMP_CAVIUM_CN30XX: 1805 c->cputype = CPU_CAVIUM_OCTEON; 1806 __cpu_name[cpu] = "Cavium Octeon"; 1807 goto platform; 1808 case PRID_IMP_CAVIUM_CN58XX: 1809 case PRID_IMP_CAVIUM_CN56XX: 1810 case PRID_IMP_CAVIUM_CN50XX: 1811 case PRID_IMP_CAVIUM_CN52XX: 1812 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1813 __cpu_name[cpu] = "Cavium Octeon+"; 1814 platform: 1815 set_elf_platform(cpu, "octeon"); 1816 break; 1817 case PRID_IMP_CAVIUM_CN61XX: 1818 case PRID_IMP_CAVIUM_CN63XX: 1819 case PRID_IMP_CAVIUM_CN66XX: 1820 case PRID_IMP_CAVIUM_CN68XX: 1821 case PRID_IMP_CAVIUM_CNF71XX: 1822 c->cputype = CPU_CAVIUM_OCTEON2; 1823 __cpu_name[cpu] = "Cavium Octeon II"; 1824 set_elf_platform(cpu, "octeon2"); 1825 break; 1826 case PRID_IMP_CAVIUM_CN70XX: 1827 case PRID_IMP_CAVIUM_CN73XX: 1828 case PRID_IMP_CAVIUM_CNF75XX: 1829 case PRID_IMP_CAVIUM_CN78XX: 1830 c->cputype = CPU_CAVIUM_OCTEON3; 1831 __cpu_name[cpu] = "Cavium Octeon III"; 1832 set_elf_platform(cpu, "octeon3"); 1833 break; 1834 default: 1835 printk(KERN_INFO "Unknown Octeon chip!\n"); 1836 c->cputype = CPU_UNKNOWN; 1837 break; 1838 } 1839 } 1840 1841 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1842 { 1843 switch (c->processor_id & PRID_IMP_MASK) { 1844 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1845 switch (c->processor_id & PRID_REV_MASK) { 1846 case PRID_REV_LOONGSON3A_R2: 1847 c->cputype = CPU_LOONGSON3; 1848 __cpu_name[cpu] = "ICT Loongson-3"; 1849 set_elf_platform(cpu, "loongson3a"); 1850 set_isa(c, MIPS_CPU_ISA_M64R2); 1851 break; 1852 case PRID_REV_LOONGSON3A_R3_0: 1853 case PRID_REV_LOONGSON3A_R3_1: 1854 c->cputype = CPU_LOONGSON3; 1855 __cpu_name[cpu] = "ICT Loongson-3"; 1856 set_elf_platform(cpu, "loongson3a"); 1857 set_isa(c, MIPS_CPU_ISA_M64R2); 1858 break; 1859 } 1860 1861 decode_configs(c); 1862 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1863 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1864 break; 1865 default: 1866 panic("Unknown Loongson Processor ID!"); 1867 break; 1868 } 1869 } 1870 1871 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1872 { 1873 decode_configs(c); 1874 /* JZRISC does not implement the CP0 counter. */ 1875 c->options &= ~MIPS_CPU_COUNTER; 1876 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1877 switch (c->processor_id & PRID_IMP_MASK) { 1878 case PRID_IMP_JZRISC: 1879 c->cputype = CPU_JZRISC; 1880 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1881 __cpu_name[cpu] = "Ingenic JZRISC"; 1882 break; 1883 default: 1884 panic("Unknown Ingenic Processor ID!"); 1885 break; 1886 } 1887 } 1888 1889 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1890 { 1891 decode_configs(c); 1892 1893 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1894 c->cputype = CPU_ALCHEMY; 1895 __cpu_name[cpu] = "Au1300"; 1896 /* following stuff is not for Alchemy */ 1897 return; 1898 } 1899 1900 c->options = (MIPS_CPU_TLB | 1901 MIPS_CPU_4KEX | 1902 MIPS_CPU_COUNTER | 1903 MIPS_CPU_DIVEC | 1904 MIPS_CPU_WATCH | 1905 MIPS_CPU_EJTAG | 1906 MIPS_CPU_LLSC); 1907 1908 switch (c->processor_id & PRID_IMP_MASK) { 1909 case PRID_IMP_NETLOGIC_XLP2XX: 1910 case PRID_IMP_NETLOGIC_XLP9XX: 1911 case PRID_IMP_NETLOGIC_XLP5XX: 1912 c->cputype = CPU_XLP; 1913 __cpu_name[cpu] = "Broadcom XLPII"; 1914 break; 1915 1916 case PRID_IMP_NETLOGIC_XLP8XX: 1917 case PRID_IMP_NETLOGIC_XLP3XX: 1918 c->cputype = CPU_XLP; 1919 __cpu_name[cpu] = "Netlogic XLP"; 1920 break; 1921 1922 case PRID_IMP_NETLOGIC_XLR732: 1923 case PRID_IMP_NETLOGIC_XLR716: 1924 case PRID_IMP_NETLOGIC_XLR532: 1925 case PRID_IMP_NETLOGIC_XLR308: 1926 case PRID_IMP_NETLOGIC_XLR532C: 1927 case PRID_IMP_NETLOGIC_XLR516C: 1928 case PRID_IMP_NETLOGIC_XLR508C: 1929 case PRID_IMP_NETLOGIC_XLR308C: 1930 c->cputype = CPU_XLR; 1931 __cpu_name[cpu] = "Netlogic XLR"; 1932 break; 1933 1934 case PRID_IMP_NETLOGIC_XLS608: 1935 case PRID_IMP_NETLOGIC_XLS408: 1936 case PRID_IMP_NETLOGIC_XLS404: 1937 case PRID_IMP_NETLOGIC_XLS208: 1938 case PRID_IMP_NETLOGIC_XLS204: 1939 case PRID_IMP_NETLOGIC_XLS108: 1940 case PRID_IMP_NETLOGIC_XLS104: 1941 case PRID_IMP_NETLOGIC_XLS616B: 1942 case PRID_IMP_NETLOGIC_XLS608B: 1943 case PRID_IMP_NETLOGIC_XLS416B: 1944 case PRID_IMP_NETLOGIC_XLS412B: 1945 case PRID_IMP_NETLOGIC_XLS408B: 1946 case PRID_IMP_NETLOGIC_XLS404B: 1947 c->cputype = CPU_XLR; 1948 __cpu_name[cpu] = "Netlogic XLS"; 1949 break; 1950 1951 default: 1952 pr_info("Unknown Netlogic chip id [%02x]!\n", 1953 c->processor_id); 1954 c->cputype = CPU_XLR; 1955 break; 1956 } 1957 1958 if (c->cputype == CPU_XLP) { 1959 set_isa(c, MIPS_CPU_ISA_M64R2); 1960 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1961 /* This will be updated again after all threads are woken up */ 1962 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1963 } else { 1964 set_isa(c, MIPS_CPU_ISA_M64R1); 1965 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1966 } 1967 c->kscratch_mask = 0xf; 1968 } 1969 1970 #ifdef CONFIG_64BIT 1971 /* For use by uaccess.h */ 1972 u64 __ua_limit; 1973 EXPORT_SYMBOL(__ua_limit); 1974 #endif 1975 1976 const char *__cpu_name[NR_CPUS]; 1977 const char *__elf_platform; 1978 1979 void cpu_probe(void) 1980 { 1981 struct cpuinfo_mips *c = ¤t_cpu_data; 1982 unsigned int cpu = smp_processor_id(); 1983 1984 /* 1985 * Set a default elf platform, cpu probe may later 1986 * overwrite it with a more precise value 1987 */ 1988 set_elf_platform(cpu, "mips"); 1989 1990 c->processor_id = PRID_IMP_UNKNOWN; 1991 c->fpu_id = FPIR_IMP_NONE; 1992 c->cputype = CPU_UNKNOWN; 1993 c->writecombine = _CACHE_UNCACHED; 1994 1995 c->fpu_csr31 = FPU_CSR_RN; 1996 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1997 1998 c->processor_id = read_c0_prid(); 1999 switch (c->processor_id & PRID_COMP_MASK) { 2000 case PRID_COMP_LEGACY: 2001 cpu_probe_legacy(c, cpu); 2002 break; 2003 case PRID_COMP_MIPS: 2004 cpu_probe_mips(c, cpu); 2005 break; 2006 case PRID_COMP_ALCHEMY: 2007 cpu_probe_alchemy(c, cpu); 2008 break; 2009 case PRID_COMP_SIBYTE: 2010 cpu_probe_sibyte(c, cpu); 2011 break; 2012 case PRID_COMP_BROADCOM: 2013 cpu_probe_broadcom(c, cpu); 2014 break; 2015 case PRID_COMP_SANDCRAFT: 2016 cpu_probe_sandcraft(c, cpu); 2017 break; 2018 case PRID_COMP_NXP: 2019 cpu_probe_nxp(c, cpu); 2020 break; 2021 case PRID_COMP_CAVIUM: 2022 cpu_probe_cavium(c, cpu); 2023 break; 2024 case PRID_COMP_LOONGSON: 2025 cpu_probe_loongson(c, cpu); 2026 break; 2027 case PRID_COMP_INGENIC_D0: 2028 case PRID_COMP_INGENIC_D1: 2029 case PRID_COMP_INGENIC_E1: 2030 cpu_probe_ingenic(c, cpu); 2031 break; 2032 case PRID_COMP_NETLOGIC: 2033 cpu_probe_netlogic(c, cpu); 2034 break; 2035 } 2036 2037 BUG_ON(!__cpu_name[cpu]); 2038 BUG_ON(c->cputype == CPU_UNKNOWN); 2039 2040 /* 2041 * Platform code can force the cpu type to optimize code 2042 * generation. In that case be sure the cpu type is correctly 2043 * manually setup otherwise it could trigger some nasty bugs. 2044 */ 2045 BUG_ON(current_cpu_type() != c->cputype); 2046 2047 if (cpu_has_rixi) { 2048 /* Enable the RIXI exceptions */ 2049 set_c0_pagegrain(PG_IEC); 2050 back_to_back_c0_hazard(); 2051 /* Verify the IEC bit is set */ 2052 if (read_c0_pagegrain() & PG_IEC) 2053 c->options |= MIPS_CPU_RIXIEX; 2054 } 2055 2056 if (mips_fpu_disabled) 2057 c->options &= ~MIPS_CPU_FPU; 2058 2059 if (mips_dsp_disabled) 2060 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2061 2062 if (mips_htw_disabled) { 2063 c->options &= ~MIPS_CPU_HTW; 2064 write_c0_pwctl(read_c0_pwctl() & 2065 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2066 } 2067 2068 if (c->options & MIPS_CPU_FPU) 2069 cpu_set_fpu_opts(c); 2070 else 2071 cpu_set_nofpu_opts(c); 2072 2073 if (cpu_has_bp_ghist) 2074 write_c0_r10k_diag(read_c0_r10k_diag() | 2075 R10K_DIAG_E_GHIST); 2076 2077 if (cpu_has_mips_r2_r6) { 2078 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2079 /* R2 has Performance Counter Interrupt indicator */ 2080 c->options |= MIPS_CPU_PCI; 2081 } 2082 else 2083 c->srsets = 1; 2084 2085 if (cpu_has_mips_r6) 2086 elf_hwcap |= HWCAP_MIPS_R6; 2087 2088 if (cpu_has_msa) { 2089 c->msa_id = cpu_get_msa_id(); 2090 WARN(c->msa_id & MSA_IR_WRPF, 2091 "Vector register partitioning unimplemented!"); 2092 elf_hwcap |= HWCAP_MIPS_MSA; 2093 } 2094 2095 if (cpu_has_vz) 2096 cpu_probe_vz(c); 2097 2098 cpu_probe_vmbits(c); 2099 2100 #ifdef CONFIG_64BIT 2101 if (cpu == 0) 2102 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2103 #endif 2104 } 2105 2106 void cpu_report(void) 2107 { 2108 struct cpuinfo_mips *c = ¤t_cpu_data; 2109 2110 pr_info("CPU%d revision is: %08x (%s)\n", 2111 smp_processor_id(), c->processor_id, cpu_name_string()); 2112 if (c->options & MIPS_CPU_FPU) 2113 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2114 if (cpu_has_msa) 2115 pr_info("MSA revision is: %08x\n", c->msa_id); 2116 } 2117 2118 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) 2119 { 2120 /* Ensure the core number fits in the field */ 2121 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> 2122 MIPS_GLOBALNUMBER_CLUSTER_SHF)); 2123 2124 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; 2125 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; 2126 } 2127 2128 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) 2129 { 2130 /* Ensure the core number fits in the field */ 2131 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); 2132 2133 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; 2134 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; 2135 } 2136 2137 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) 2138 { 2139 /* Ensure the VP(E) ID fits in the field */ 2140 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); 2141 2142 /* Ensure we're not using VP(E)s without support */ 2143 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && 2144 !IS_ENABLED(CONFIG_CPU_MIPSR6)); 2145 2146 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; 2147 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; 2148 } 2149