1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) xxxx the Anonymous 6 * Copyright (C) 1994 - 2006 Ralf Baechle 7 * Copyright (C) 2003, 2004 Maciej W. Rozycki 8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/ptrace.h> 13 #include <linux/smp.h> 14 #include <linux/stddef.h> 15 #include <linux/export.h> 16 17 #include <asm/bugs.h> 18 #include <asm/cpu.h> 19 #include <asm/cpu-features.h> 20 #include <asm/cpu-type.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/mipsmtregs.h> 24 #include <asm/msa.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/pgtable-bits.h> 28 #include <asm/spram.h> 29 #include <linux/uaccess.h> 30 31 #include "fpu-probe.h" 32 33 #include <asm/mach-loongson64/cpucfg-emul.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 static inline unsigned long cpu_get_msa_id(void) 40 { 41 unsigned long status, msa_id; 42 43 status = read_c0_status(); 44 __enable_fpu(FPU_64BIT); 45 enable_msa(); 46 msa_id = read_msa_ir(); 47 disable_msa(); 48 write_c0_status(status); 49 return msa_id; 50 } 51 52 static int mips_dsp_disabled; 53 54 static int __init dsp_disable(char *s) 55 { 56 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 57 mips_dsp_disabled = 1; 58 59 return 1; 60 } 61 62 __setup("nodsp", dsp_disable); 63 64 static int mips_htw_disabled; 65 66 static int __init htw_disable(char *s) 67 { 68 mips_htw_disabled = 1; 69 cpu_data[0].options &= ~MIPS_CPU_HTW; 70 write_c0_pwctl(read_c0_pwctl() & 71 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 72 73 return 1; 74 } 75 76 __setup("nohtw", htw_disable); 77 78 static int mips_ftlb_disabled; 79 static int mips_has_ftlb_configured; 80 81 enum ftlb_flags { 82 FTLB_EN = 1 << 0, 83 FTLB_SET_PROB = 1 << 1, 84 }; 85 86 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 87 88 static int __init ftlb_disable(char *s) 89 { 90 unsigned int config4, mmuextdef; 91 92 /* 93 * If the core hasn't done any FTLB configuration, there is nothing 94 * for us to do here. 95 */ 96 if (!mips_has_ftlb_configured) 97 return 1; 98 99 /* Disable it in the boot cpu */ 100 if (set_ftlb_enable(&cpu_data[0], 0)) { 101 pr_warn("Can't turn FTLB off\n"); 102 return 1; 103 } 104 105 config4 = read_c0_config4(); 106 107 /* Check that FTLB has been disabled */ 108 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 109 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 110 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 111 /* This should never happen */ 112 pr_warn("FTLB could not be disabled!\n"); 113 return 1; 114 } 115 116 mips_ftlb_disabled = 1; 117 mips_has_ftlb_configured = 0; 118 119 /* 120 * noftlb is mainly used for debug purposes so print 121 * an informative message instead of using pr_debug() 122 */ 123 pr_info("FTLB has been disabled\n"); 124 125 /* 126 * Some of these bits are duplicated in the decode_config4. 127 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 128 * once FTLB has been disabled so undo what decode_config4 did. 129 */ 130 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 131 cpu_data[0].tlbsizeftlbsets; 132 cpu_data[0].tlbsizeftlbsets = 0; 133 cpu_data[0].tlbsizeftlbways = 0; 134 135 return 1; 136 } 137 138 __setup("noftlb", ftlb_disable); 139 140 /* 141 * Check if the CPU has per tc perf counters 142 */ 143 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) 144 { 145 if (read_c0_config7() & MTI_CONF7_PTC) 146 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; 147 } 148 149 static inline void check_errata(void) 150 { 151 struct cpuinfo_mips *c = ¤t_cpu_data; 152 153 switch (current_cpu_type()) { 154 case CPU_34K: 155 /* 156 * Erratum "RPS May Cause Incorrect Instruction Execution" 157 * This code only handles VPE0, any SMP/RTOS code 158 * making use of VPE1 will be responsable for that VPE. 159 */ 160 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 161 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 162 break; 163 default: 164 break; 165 } 166 } 167 168 void __init check_bugs32(void) 169 { 170 check_errata(); 171 } 172 173 /* 174 * Probe whether cpu has config register by trying to play with 175 * alternate cache bit and see whether it matters. 176 * It's used by cpu_probe to distinguish between R3000A and R3081. 177 */ 178 static inline int cpu_has_confreg(void) 179 { 180 #ifdef CONFIG_CPU_R3000 181 extern unsigned long r3k_cache_size(unsigned long); 182 unsigned long size1, size2; 183 unsigned long cfg = read_c0_conf(); 184 185 size1 = r3k_cache_size(ST0_ISC); 186 write_c0_conf(cfg ^ R30XX_CONF_AC); 187 size2 = r3k_cache_size(ST0_ISC); 188 write_c0_conf(cfg); 189 return size1 != size2; 190 #else 191 return 0; 192 #endif 193 } 194 195 static inline void set_elf_platform(int cpu, const char *plat) 196 { 197 if (cpu == 0) 198 __elf_platform = plat; 199 } 200 201 static inline void set_elf_base_platform(const char *plat) 202 { 203 if (__elf_base_platform == NULL) { 204 __elf_base_platform = plat; 205 } 206 } 207 208 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 209 { 210 #ifdef __NEED_VMBITS_PROBE 211 write_c0_entryhi(0x3fffffffffffe000ULL); 212 back_to_back_c0_hazard(); 213 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 214 #endif 215 } 216 217 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 218 { 219 switch (isa) { 220 case MIPS_CPU_ISA_M64R5: 221 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; 222 set_elf_base_platform("mips64r5"); 223 fallthrough; 224 case MIPS_CPU_ISA_M64R2: 225 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 226 set_elf_base_platform("mips64r2"); 227 fallthrough; 228 case MIPS_CPU_ISA_M64R1: 229 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 230 set_elf_base_platform("mips64"); 231 fallthrough; 232 case MIPS_CPU_ISA_V: 233 c->isa_level |= MIPS_CPU_ISA_V; 234 set_elf_base_platform("mips5"); 235 fallthrough; 236 case MIPS_CPU_ISA_IV: 237 c->isa_level |= MIPS_CPU_ISA_IV; 238 set_elf_base_platform("mips4"); 239 fallthrough; 240 case MIPS_CPU_ISA_III: 241 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 242 set_elf_base_platform("mips3"); 243 break; 244 245 /* R6 incompatible with everything else */ 246 case MIPS_CPU_ISA_M64R6: 247 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 248 set_elf_base_platform("mips64r6"); 249 fallthrough; 250 case MIPS_CPU_ISA_M32R6: 251 c->isa_level |= MIPS_CPU_ISA_M32R6; 252 set_elf_base_platform("mips32r6"); 253 /* Break here so we don't add incompatible ISAs */ 254 break; 255 case MIPS_CPU_ISA_M32R5: 256 c->isa_level |= MIPS_CPU_ISA_M32R5; 257 set_elf_base_platform("mips32r5"); 258 fallthrough; 259 case MIPS_CPU_ISA_M32R2: 260 c->isa_level |= MIPS_CPU_ISA_M32R2; 261 set_elf_base_platform("mips32r2"); 262 fallthrough; 263 case MIPS_CPU_ISA_M32R1: 264 c->isa_level |= MIPS_CPU_ISA_M32R1; 265 set_elf_base_platform("mips32"); 266 fallthrough; 267 case MIPS_CPU_ISA_II: 268 c->isa_level |= MIPS_CPU_ISA_II; 269 set_elf_base_platform("mips2"); 270 break; 271 } 272 } 273 274 static char unknown_isa[] = KERN_ERR \ 275 "Unsupported ISA type, c0.config0: %d."; 276 277 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 278 { 279 280 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 281 282 /* 283 * 0 = All TLBWR instructions go to FTLB 284 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 285 * FTLB and 1 goes to the VTLB. 286 * 2 = 7:1: As above with 7:1 ratio. 287 * 3 = 3:1: As above with 3:1 ratio. 288 * 289 * Use the linear midpoint as the probability threshold. 290 */ 291 if (probability >= 12) 292 return 1; 293 else if (probability >= 6) 294 return 2; 295 else 296 /* 297 * So FTLB is less than 4 times bigger than VTLB. 298 * A 3:1 ratio can still be useful though. 299 */ 300 return 3; 301 } 302 303 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 304 { 305 unsigned int config; 306 307 /* It's implementation dependent how the FTLB can be enabled */ 308 switch (c->cputype) { 309 case CPU_PROAPTIV: 310 case CPU_P5600: 311 case CPU_P6600: 312 /* proAptiv & related cores use Config6 to enable the FTLB */ 313 config = read_c0_config6(); 314 315 if (flags & FTLB_EN) 316 config |= MTI_CONF6_FTLBEN; 317 else 318 config &= ~MTI_CONF6_FTLBEN; 319 320 if (flags & FTLB_SET_PROB) { 321 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT); 322 config |= calculate_ftlb_probability(c) 323 << MTI_CONF6_FTLBP_SHIFT; 324 } 325 326 write_c0_config6(config); 327 back_to_back_c0_hazard(); 328 break; 329 case CPU_I6400: 330 case CPU_I6500: 331 /* There's no way to disable the FTLB */ 332 if (!(flags & FTLB_EN)) 333 return 1; 334 return 0; 335 case CPU_LOONGSON64: 336 /* Flush ITLB, DTLB, VTLB and FTLB */ 337 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 338 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 339 /* Loongson-3 cores use Config6 to enable the FTLB */ 340 config = read_c0_config6(); 341 if (flags & FTLB_EN) 342 /* Enable FTLB */ 343 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS); 344 else 345 /* Disable FTLB */ 346 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS); 347 break; 348 default: 349 return 1; 350 } 351 352 return 0; 353 } 354 355 static int mm_config(struct cpuinfo_mips *c) 356 { 357 unsigned int config0, update, mm; 358 359 config0 = read_c0_config(); 360 mm = config0 & MIPS_CONF_MM; 361 362 /* 363 * It's implementation dependent what type of write-merge is supported 364 * and whether it can be enabled/disabled. If it is settable lets make 365 * the merging allowed by default. Some platforms might have 366 * write-through caching unsupported. In this case just ignore the 367 * CP0.Config.MM bit field value. 368 */ 369 switch (c->cputype) { 370 case CPU_24K: 371 case CPU_34K: 372 case CPU_74K: 373 case CPU_P5600: 374 case CPU_P6600: 375 c->options |= MIPS_CPU_MM_FULL; 376 update = MIPS_CONF_MM_FULL; 377 break; 378 case CPU_1004K: 379 case CPU_1074K: 380 case CPU_INTERAPTIV: 381 case CPU_PROAPTIV: 382 mm = 0; 383 fallthrough; 384 default: 385 update = 0; 386 break; 387 } 388 389 if (update) { 390 config0 = (config0 & ~MIPS_CONF_MM) | update; 391 write_c0_config(config0); 392 } else if (mm == MIPS_CONF_MM_SYSAD) { 393 c->options |= MIPS_CPU_MM_SYSAD; 394 } else if (mm == MIPS_CONF_MM_FULL) { 395 c->options |= MIPS_CPU_MM_FULL; 396 } 397 398 return 0; 399 } 400 401 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 402 { 403 unsigned int config0; 404 int isa, mt; 405 406 config0 = read_c0_config(); 407 408 /* 409 * Look for Standard TLB or Dual VTLB and FTLB 410 */ 411 mt = config0 & MIPS_CONF_MT; 412 if (mt == MIPS_CONF_MT_TLB) 413 c->options |= MIPS_CPU_TLB; 414 else if (mt == MIPS_CONF_MT_FTLB) 415 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 416 417 isa = (config0 & MIPS_CONF_AT) >> 13; 418 switch (isa) { 419 case 0: 420 switch ((config0 & MIPS_CONF_AR) >> 10) { 421 case 0: 422 set_isa(c, MIPS_CPU_ISA_M32R1); 423 break; 424 case 1: 425 set_isa(c, MIPS_CPU_ISA_M32R2); 426 break; 427 case 2: 428 set_isa(c, MIPS_CPU_ISA_M32R6); 429 break; 430 default: 431 goto unknown; 432 } 433 break; 434 case 2: 435 switch ((config0 & MIPS_CONF_AR) >> 10) { 436 case 0: 437 set_isa(c, MIPS_CPU_ISA_M64R1); 438 break; 439 case 1: 440 set_isa(c, MIPS_CPU_ISA_M64R2); 441 break; 442 case 2: 443 set_isa(c, MIPS_CPU_ISA_M64R6); 444 break; 445 default: 446 goto unknown; 447 } 448 break; 449 default: 450 goto unknown; 451 } 452 453 return config0 & MIPS_CONF_M; 454 455 unknown: 456 panic(unknown_isa, config0); 457 } 458 459 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 460 { 461 unsigned int config1; 462 463 config1 = read_c0_config1(); 464 465 if (config1 & MIPS_CONF1_MD) 466 c->ases |= MIPS_ASE_MDMX; 467 if (config1 & MIPS_CONF1_PC) 468 c->options |= MIPS_CPU_PERF; 469 if (config1 & MIPS_CONF1_WR) 470 c->options |= MIPS_CPU_WATCH; 471 if (config1 & MIPS_CONF1_CA) 472 c->ases |= MIPS_ASE_MIPS16; 473 if (config1 & MIPS_CONF1_EP) 474 c->options |= MIPS_CPU_EJTAG; 475 if (config1 & MIPS_CONF1_FP) { 476 c->options |= MIPS_CPU_FPU; 477 c->options |= MIPS_CPU_32FPR; 478 } 479 if (cpu_has_tlb) { 480 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 481 c->tlbsizevtlb = c->tlbsize; 482 c->tlbsizeftlbsets = 0; 483 } 484 485 return config1 & MIPS_CONF_M; 486 } 487 488 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 489 { 490 unsigned int config2; 491 492 config2 = read_c0_config2(); 493 494 if (config2 & MIPS_CONF2_SL) 495 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 496 497 return config2 & MIPS_CONF_M; 498 } 499 500 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 501 { 502 unsigned int config3; 503 504 config3 = read_c0_config3(); 505 506 if (config3 & MIPS_CONF3_SM) { 507 c->ases |= MIPS_ASE_SMARTMIPS; 508 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 509 } 510 if (config3 & MIPS_CONF3_RXI) 511 c->options |= MIPS_CPU_RIXI; 512 if (config3 & MIPS_CONF3_CTXTC) 513 c->options |= MIPS_CPU_CTXTC; 514 if (config3 & MIPS_CONF3_DSP) 515 c->ases |= MIPS_ASE_DSP; 516 if (config3 & MIPS_CONF3_DSP2P) { 517 c->ases |= MIPS_ASE_DSP2P; 518 if (cpu_has_mips_r6) 519 c->ases |= MIPS_ASE_DSP3; 520 } 521 if (config3 & MIPS_CONF3_VINT) 522 c->options |= MIPS_CPU_VINT; 523 if (config3 & MIPS_CONF3_VEIC) 524 c->options |= MIPS_CPU_VEIC; 525 if (config3 & MIPS_CONF3_LPA) 526 c->options |= MIPS_CPU_LPA; 527 if (config3 & MIPS_CONF3_MT) 528 c->ases |= MIPS_ASE_MIPSMT; 529 if (config3 & MIPS_CONF3_ULRI) 530 c->options |= MIPS_CPU_ULRI; 531 if (config3 & MIPS_CONF3_ISA) 532 c->options |= MIPS_CPU_MICROMIPS; 533 if (config3 & MIPS_CONF3_VZ) 534 c->ases |= MIPS_ASE_VZ; 535 if (config3 & MIPS_CONF3_SC) 536 c->options |= MIPS_CPU_SEGMENTS; 537 if (config3 & MIPS_CONF3_BI) 538 c->options |= MIPS_CPU_BADINSTR; 539 if (config3 & MIPS_CONF3_BP) 540 c->options |= MIPS_CPU_BADINSTRP; 541 if (config3 & MIPS_CONF3_MSA) 542 c->ases |= MIPS_ASE_MSA; 543 if (config3 & MIPS_CONF3_PW) { 544 c->htw_seq = 0; 545 c->options |= MIPS_CPU_HTW; 546 } 547 if (config3 & MIPS_CONF3_CDMM) 548 c->options |= MIPS_CPU_CDMM; 549 if (config3 & MIPS_CONF3_SP) 550 c->options |= MIPS_CPU_SP; 551 552 return config3 & MIPS_CONF_M; 553 } 554 555 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 556 { 557 unsigned int config4; 558 unsigned int newcf4; 559 unsigned int mmuextdef; 560 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 561 unsigned long asid_mask; 562 563 config4 = read_c0_config4(); 564 565 if (cpu_has_tlb) { 566 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 567 c->options |= MIPS_CPU_TLBINV; 568 569 /* 570 * R6 has dropped the MMUExtDef field from config4. 571 * On R6 the fields always describe the FTLB, and only if it is 572 * present according to Config.MT. 573 */ 574 if (!cpu_has_mips_r6) 575 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 576 else if (cpu_has_ftlb) 577 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 578 else 579 mmuextdef = 0; 580 581 switch (mmuextdef) { 582 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 583 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 584 c->tlbsizevtlb = c->tlbsize; 585 break; 586 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 587 c->tlbsizevtlb += 588 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 589 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 590 c->tlbsize = c->tlbsizevtlb; 591 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 592 fallthrough; 593 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 594 if (mips_ftlb_disabled) 595 break; 596 newcf4 = (config4 & ~ftlb_page) | 597 (page_size_ftlb(mmuextdef) << 598 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 599 write_c0_config4(newcf4); 600 back_to_back_c0_hazard(); 601 config4 = read_c0_config4(); 602 if (config4 != newcf4) { 603 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 604 PAGE_SIZE, config4); 605 /* Switch FTLB off */ 606 set_ftlb_enable(c, 0); 607 mips_ftlb_disabled = 1; 608 break; 609 } 610 c->tlbsizeftlbsets = 1 << 611 ((config4 & MIPS_CONF4_FTLBSETS) >> 612 MIPS_CONF4_FTLBSETS_SHIFT); 613 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 614 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 615 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 616 mips_has_ftlb_configured = 1; 617 break; 618 } 619 } 620 621 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 622 >> MIPS_CONF4_KSCREXIST_SHIFT; 623 624 asid_mask = MIPS_ENTRYHI_ASID; 625 if (config4 & MIPS_CONF4_AE) 626 asid_mask |= MIPS_ENTRYHI_ASIDX; 627 set_cpu_asid_mask(c, asid_mask); 628 629 /* 630 * Warn if the computed ASID mask doesn't match the mask the kernel 631 * is built for. This may indicate either a serious problem or an 632 * easy optimisation opportunity, but either way should be addressed. 633 */ 634 WARN_ON(asid_mask != cpu_asid_mask(c)); 635 636 return config4 & MIPS_CONF_M; 637 } 638 639 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 640 { 641 unsigned int config5, max_mmid_width; 642 unsigned long asid_mask; 643 644 config5 = read_c0_config5(); 645 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 646 647 if (cpu_has_mips_r6) { 648 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid) 649 config5 |= MIPS_CONF5_MI; 650 else 651 config5 &= ~MIPS_CONF5_MI; 652 } 653 654 write_c0_config5(config5); 655 656 if (config5 & MIPS_CONF5_EVA) 657 c->options |= MIPS_CPU_EVA; 658 if (config5 & MIPS_CONF5_MRP) 659 c->options |= MIPS_CPU_MAAR; 660 if (config5 & MIPS_CONF5_LLB) 661 c->options |= MIPS_CPU_RW_LLB; 662 if (config5 & MIPS_CONF5_MVH) 663 c->options |= MIPS_CPU_MVH; 664 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 665 c->options |= MIPS_CPU_VP; 666 if (config5 & MIPS_CONF5_CA2) 667 c->ases |= MIPS_ASE_MIPS16E2; 668 669 if (config5 & MIPS_CONF5_CRCP) 670 elf_hwcap |= HWCAP_MIPS_CRC32; 671 672 if (cpu_has_mips_r6) { 673 /* Ensure the write to config5 above takes effect */ 674 back_to_back_c0_hazard(); 675 676 /* Check whether we successfully enabled MMID support */ 677 config5 = read_c0_config5(); 678 if (config5 & MIPS_CONF5_MI) 679 c->options |= MIPS_CPU_MMID; 680 681 /* 682 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable 683 * for the CPU we're running on, or if CPUs in an SMP system 684 * have inconsistent MMID support. 685 */ 686 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); 687 688 if (cpu_has_mmid) { 689 write_c0_memorymapid(~0ul); 690 back_to_back_c0_hazard(); 691 asid_mask = read_c0_memorymapid(); 692 693 /* 694 * We maintain a bitmap to track MMID allocation, and 695 * need a sensible upper bound on the size of that 696 * bitmap. The initial CPU with MMID support (I6500) 697 * supports 16 bit MMIDs, which gives us an 8KiB 698 * bitmap. The architecture recommends that hardware 699 * support 32 bit MMIDs, which would give us a 512MiB 700 * bitmap - that's too big in most cases. 701 * 702 * Cap MMID width at 16 bits for now & we can revisit 703 * this if & when hardware supports anything wider. 704 */ 705 max_mmid_width = 16; 706 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { 707 pr_info("Capping MMID width at %d bits", 708 max_mmid_width); 709 asid_mask = GENMASK(max_mmid_width - 1, 0); 710 } 711 712 set_cpu_asid_mask(c, asid_mask); 713 } 714 } 715 716 return config5 & MIPS_CONF_M; 717 } 718 719 static void decode_configs(struct cpuinfo_mips *c) 720 { 721 int ok; 722 723 /* MIPS32 or MIPS64 compliant CPU. */ 724 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 725 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 726 727 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 728 729 /* Enable FTLB if present and not disabled */ 730 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 731 732 ok = decode_config0(c); /* Read Config registers. */ 733 BUG_ON(!ok); /* Arch spec violation! */ 734 if (ok) 735 ok = decode_config1(c); 736 if (ok) 737 ok = decode_config2(c); 738 if (ok) 739 ok = decode_config3(c); 740 if (ok) 741 ok = decode_config4(c); 742 if (ok) 743 ok = decode_config5(c); 744 745 /* Probe the EBase.WG bit */ 746 if (cpu_has_mips_r2_r6) { 747 u64 ebase; 748 unsigned int status; 749 750 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 751 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 752 : (s32)read_c0_ebase(); 753 if (ebase & MIPS_EBASE_WG) { 754 /* WG bit already set, we can avoid the clumsy probe */ 755 c->options |= MIPS_CPU_EBASE_WG; 756 } else { 757 /* Its UNDEFINED to change EBase while BEV=0 */ 758 status = read_c0_status(); 759 write_c0_status(status | ST0_BEV); 760 irq_enable_hazard(); 761 /* 762 * On pre-r6 cores, this may well clobber the upper bits 763 * of EBase. This is hard to avoid without potentially 764 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 765 */ 766 if (cpu_has_mips64r6) 767 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 768 else 769 write_c0_ebase(ebase | MIPS_EBASE_WG); 770 back_to_back_c0_hazard(); 771 /* Restore BEV */ 772 write_c0_status(status); 773 if (read_c0_ebase() & MIPS_EBASE_WG) { 774 c->options |= MIPS_CPU_EBASE_WG; 775 write_c0_ebase(ebase); 776 } 777 } 778 } 779 780 /* configure the FTLB write probability */ 781 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 782 783 mips_probe_watch_registers(c); 784 785 #ifndef CONFIG_MIPS_CPS 786 if (cpu_has_mips_r2_r6) { 787 unsigned int core; 788 789 core = get_ebase_cpunum(); 790 if (cpu_has_mipsmt) 791 core >>= fls(core_nvpes()) - 1; 792 cpu_set_core(c, core); 793 } 794 #endif 795 } 796 797 /* 798 * Probe for certain guest capabilities by writing config bits and reading back. 799 * Finally write back the original value. 800 */ 801 #define probe_gc0_config(name, maxconf, bits) \ 802 do { \ 803 unsigned int tmp; \ 804 tmp = read_gc0_##name(); \ 805 write_gc0_##name(tmp | (bits)); \ 806 back_to_back_c0_hazard(); \ 807 maxconf = read_gc0_##name(); \ 808 write_gc0_##name(tmp); \ 809 } while (0) 810 811 /* 812 * Probe for dynamic guest capabilities by changing certain config bits and 813 * reading back to see if they change. Finally write back the original value. 814 */ 815 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 816 do { \ 817 maxconf = read_gc0_##name(); \ 818 write_gc0_##name(maxconf ^ (bits)); \ 819 back_to_back_c0_hazard(); \ 820 dynconf = maxconf ^ read_gc0_##name(); \ 821 write_gc0_##name(maxconf); \ 822 maxconf |= dynconf; \ 823 } while (0) 824 825 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 826 { 827 unsigned int config0; 828 829 probe_gc0_config(config, config0, MIPS_CONF_M); 830 831 if (config0 & MIPS_CONF_M) 832 c->guest.conf |= BIT(1); 833 return config0 & MIPS_CONF_M; 834 } 835 836 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 837 { 838 unsigned int config1, config1_dyn; 839 840 probe_gc0_config_dyn(config1, config1, config1_dyn, 841 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 842 MIPS_CONF1_FP); 843 844 if (config1 & MIPS_CONF1_FP) 845 c->guest.options |= MIPS_CPU_FPU; 846 if (config1_dyn & MIPS_CONF1_FP) 847 c->guest.options_dyn |= MIPS_CPU_FPU; 848 849 if (config1 & MIPS_CONF1_WR) 850 c->guest.options |= MIPS_CPU_WATCH; 851 if (config1_dyn & MIPS_CONF1_WR) 852 c->guest.options_dyn |= MIPS_CPU_WATCH; 853 854 if (config1 & MIPS_CONF1_PC) 855 c->guest.options |= MIPS_CPU_PERF; 856 if (config1_dyn & MIPS_CONF1_PC) 857 c->guest.options_dyn |= MIPS_CPU_PERF; 858 859 if (config1 & MIPS_CONF_M) 860 c->guest.conf |= BIT(2); 861 return config1 & MIPS_CONF_M; 862 } 863 864 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 865 { 866 unsigned int config2; 867 868 probe_gc0_config(config2, config2, MIPS_CONF_M); 869 870 if (config2 & MIPS_CONF_M) 871 c->guest.conf |= BIT(3); 872 return config2 & MIPS_CONF_M; 873 } 874 875 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 876 { 877 unsigned int config3, config3_dyn; 878 879 probe_gc0_config_dyn(config3, config3, config3_dyn, 880 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 881 MIPS_CONF3_CTXTC); 882 883 if (config3 & MIPS_CONF3_CTXTC) 884 c->guest.options |= MIPS_CPU_CTXTC; 885 if (config3_dyn & MIPS_CONF3_CTXTC) 886 c->guest.options_dyn |= MIPS_CPU_CTXTC; 887 888 if (config3 & MIPS_CONF3_PW) 889 c->guest.options |= MIPS_CPU_HTW; 890 891 if (config3 & MIPS_CONF3_ULRI) 892 c->guest.options |= MIPS_CPU_ULRI; 893 894 if (config3 & MIPS_CONF3_SC) 895 c->guest.options |= MIPS_CPU_SEGMENTS; 896 897 if (config3 & MIPS_CONF3_BI) 898 c->guest.options |= MIPS_CPU_BADINSTR; 899 if (config3 & MIPS_CONF3_BP) 900 c->guest.options |= MIPS_CPU_BADINSTRP; 901 902 if (config3 & MIPS_CONF3_MSA) 903 c->guest.ases |= MIPS_ASE_MSA; 904 if (config3_dyn & MIPS_CONF3_MSA) 905 c->guest.ases_dyn |= MIPS_ASE_MSA; 906 907 if (config3 & MIPS_CONF_M) 908 c->guest.conf |= BIT(4); 909 return config3 & MIPS_CONF_M; 910 } 911 912 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 913 { 914 unsigned int config4; 915 916 probe_gc0_config(config4, config4, 917 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 918 919 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 920 >> MIPS_CONF4_KSCREXIST_SHIFT; 921 922 if (config4 & MIPS_CONF_M) 923 c->guest.conf |= BIT(5); 924 return config4 & MIPS_CONF_M; 925 } 926 927 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 928 { 929 unsigned int config5, config5_dyn; 930 931 probe_gc0_config_dyn(config5, config5, config5_dyn, 932 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 933 934 if (config5 & MIPS_CONF5_MRP) 935 c->guest.options |= MIPS_CPU_MAAR; 936 if (config5_dyn & MIPS_CONF5_MRP) 937 c->guest.options_dyn |= MIPS_CPU_MAAR; 938 939 if (config5 & MIPS_CONF5_LLB) 940 c->guest.options |= MIPS_CPU_RW_LLB; 941 942 if (config5 & MIPS_CONF5_MVH) 943 c->guest.options |= MIPS_CPU_MVH; 944 945 if (config5 & MIPS_CONF_M) 946 c->guest.conf |= BIT(6); 947 return config5 & MIPS_CONF_M; 948 } 949 950 static inline void decode_guest_configs(struct cpuinfo_mips *c) 951 { 952 unsigned int ok; 953 954 ok = decode_guest_config0(c); 955 if (ok) 956 ok = decode_guest_config1(c); 957 if (ok) 958 ok = decode_guest_config2(c); 959 if (ok) 960 ok = decode_guest_config3(c); 961 if (ok) 962 ok = decode_guest_config4(c); 963 if (ok) 964 decode_guest_config5(c); 965 } 966 967 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 968 { 969 unsigned int guestctl0, temp; 970 971 guestctl0 = read_c0_guestctl0(); 972 973 if (guestctl0 & MIPS_GCTL0_G0E) 974 c->options |= MIPS_CPU_GUESTCTL0EXT; 975 if (guestctl0 & MIPS_GCTL0_G1) 976 c->options |= MIPS_CPU_GUESTCTL1; 977 if (guestctl0 & MIPS_GCTL0_G2) 978 c->options |= MIPS_CPU_GUESTCTL2; 979 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 980 c->options |= MIPS_CPU_GUESTID; 981 982 /* 983 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 984 * first, otherwise all data accesses will be fully virtualised 985 * as if they were performed by guest mode. 986 */ 987 write_c0_guestctl1(0); 988 tlbw_use_hazard(); 989 990 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 991 back_to_back_c0_hazard(); 992 temp = read_c0_guestctl0(); 993 994 if (temp & MIPS_GCTL0_DRG) { 995 write_c0_guestctl0(guestctl0); 996 c->options |= MIPS_CPU_DRG; 997 } 998 } 999 } 1000 1001 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1002 { 1003 if (cpu_has_guestid) { 1004 /* determine the number of bits of GuestID available */ 1005 write_c0_guestctl1(MIPS_GCTL1_ID); 1006 back_to_back_c0_hazard(); 1007 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1008 >> MIPS_GCTL1_ID_SHIFT; 1009 write_c0_guestctl1(0); 1010 } 1011 } 1012 1013 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1014 { 1015 /* determine the number of bits of GTOffset available */ 1016 write_c0_gtoffset(0xffffffff); 1017 back_to_back_c0_hazard(); 1018 c->gtoffset_mask = read_c0_gtoffset(); 1019 write_c0_gtoffset(0); 1020 } 1021 1022 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1023 { 1024 cpu_probe_guestctl0(c); 1025 if (cpu_has_guestctl1) 1026 cpu_probe_guestctl1(c); 1027 1028 cpu_probe_gtoffset(c); 1029 1030 decode_guest_configs(c); 1031 } 1032 1033 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1034 | MIPS_CPU_COUNTER) 1035 1036 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1037 { 1038 switch (c->processor_id & PRID_IMP_MASK) { 1039 case PRID_IMP_R2000: 1040 c->cputype = CPU_R2000; 1041 __cpu_name[cpu] = "R2000"; 1042 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1043 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1044 MIPS_CPU_NOFPUEX; 1045 if (__cpu_has_fpu()) 1046 c->options |= MIPS_CPU_FPU; 1047 c->tlbsize = 64; 1048 break; 1049 case PRID_IMP_R3000: 1050 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1051 if (cpu_has_confreg()) { 1052 c->cputype = CPU_R3081E; 1053 __cpu_name[cpu] = "R3081"; 1054 } else { 1055 c->cputype = CPU_R3000A; 1056 __cpu_name[cpu] = "R3000A"; 1057 } 1058 } else { 1059 c->cputype = CPU_R3000; 1060 __cpu_name[cpu] = "R3000"; 1061 } 1062 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1063 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1064 MIPS_CPU_NOFPUEX; 1065 if (__cpu_has_fpu()) 1066 c->options |= MIPS_CPU_FPU; 1067 c->tlbsize = 64; 1068 break; 1069 case PRID_IMP_R4000: 1070 if (read_c0_config() & CONF_SC) { 1071 if ((c->processor_id & PRID_REV_MASK) >= 1072 PRID_REV_R4400) { 1073 c->cputype = CPU_R4400PC; 1074 __cpu_name[cpu] = "R4400PC"; 1075 } else { 1076 c->cputype = CPU_R4000PC; 1077 __cpu_name[cpu] = "R4000PC"; 1078 } 1079 } else { 1080 int cca = read_c0_config() & CONF_CM_CMASK; 1081 int mc; 1082 1083 /* 1084 * SC and MC versions can't be reliably told apart, 1085 * but only the latter support coherent caching 1086 * modes so assume the firmware has set the KSEG0 1087 * coherency attribute reasonably (if uncached, we 1088 * assume SC). 1089 */ 1090 switch (cca) { 1091 case CONF_CM_CACHABLE_CE: 1092 case CONF_CM_CACHABLE_COW: 1093 case CONF_CM_CACHABLE_CUW: 1094 mc = 1; 1095 break; 1096 default: 1097 mc = 0; 1098 break; 1099 } 1100 if ((c->processor_id & PRID_REV_MASK) >= 1101 PRID_REV_R4400) { 1102 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1103 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1104 } else { 1105 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1106 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1107 } 1108 } 1109 1110 set_isa(c, MIPS_CPU_ISA_III); 1111 c->fpu_msk31 |= FPU_CSR_CONDX; 1112 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1113 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1114 MIPS_CPU_LLSC; 1115 c->tlbsize = 48; 1116 break; 1117 case PRID_IMP_VR41XX: 1118 set_isa(c, MIPS_CPU_ISA_III); 1119 c->fpu_msk31 |= FPU_CSR_CONDX; 1120 c->options = R4K_OPTS; 1121 c->tlbsize = 32; 1122 switch (c->processor_id & 0xf0) { 1123 case PRID_REV_VR4111: 1124 c->cputype = CPU_VR4111; 1125 __cpu_name[cpu] = "NEC VR4111"; 1126 break; 1127 case PRID_REV_VR4121: 1128 c->cputype = CPU_VR4121; 1129 __cpu_name[cpu] = "NEC VR4121"; 1130 break; 1131 case PRID_REV_VR4122: 1132 if ((c->processor_id & 0xf) < 0x3) { 1133 c->cputype = CPU_VR4122; 1134 __cpu_name[cpu] = "NEC VR4122"; 1135 } else { 1136 c->cputype = CPU_VR4181A; 1137 __cpu_name[cpu] = "NEC VR4181A"; 1138 } 1139 break; 1140 case PRID_REV_VR4130: 1141 if ((c->processor_id & 0xf) < 0x4) { 1142 c->cputype = CPU_VR4131; 1143 __cpu_name[cpu] = "NEC VR4131"; 1144 } else { 1145 c->cputype = CPU_VR4133; 1146 c->options |= MIPS_CPU_LLSC; 1147 __cpu_name[cpu] = "NEC VR4133"; 1148 } 1149 break; 1150 default: 1151 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1152 c->cputype = CPU_VR41XX; 1153 __cpu_name[cpu] = "NEC Vr41xx"; 1154 break; 1155 } 1156 break; 1157 case PRID_IMP_R4600: 1158 c->cputype = CPU_R4600; 1159 __cpu_name[cpu] = "R4600"; 1160 set_isa(c, MIPS_CPU_ISA_III); 1161 c->fpu_msk31 |= FPU_CSR_CONDX; 1162 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1163 MIPS_CPU_LLSC; 1164 c->tlbsize = 48; 1165 break; 1166 #if 0 1167 case PRID_IMP_R4650: 1168 /* 1169 * This processor doesn't have an MMU, so it's not 1170 * "real easy" to run Linux on it. It is left purely 1171 * for documentation. Commented out because it shares 1172 * it's c0_prid id number with the TX3900. 1173 */ 1174 c->cputype = CPU_R4650; 1175 __cpu_name[cpu] = "R4650"; 1176 set_isa(c, MIPS_CPU_ISA_III); 1177 c->fpu_msk31 |= FPU_CSR_CONDX; 1178 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1179 c->tlbsize = 48; 1180 break; 1181 #endif 1182 case PRID_IMP_TX39: 1183 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1184 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1185 1186 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1187 c->cputype = CPU_TX3927; 1188 __cpu_name[cpu] = "TX3927"; 1189 c->tlbsize = 64; 1190 } else { 1191 switch (c->processor_id & PRID_REV_MASK) { 1192 case PRID_REV_TX3912: 1193 c->cputype = CPU_TX3912; 1194 __cpu_name[cpu] = "TX3912"; 1195 c->tlbsize = 32; 1196 break; 1197 case PRID_REV_TX3922: 1198 c->cputype = CPU_TX3922; 1199 __cpu_name[cpu] = "TX3922"; 1200 c->tlbsize = 64; 1201 break; 1202 } 1203 } 1204 break; 1205 case PRID_IMP_R4700: 1206 c->cputype = CPU_R4700; 1207 __cpu_name[cpu] = "R4700"; 1208 set_isa(c, MIPS_CPU_ISA_III); 1209 c->fpu_msk31 |= FPU_CSR_CONDX; 1210 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1211 MIPS_CPU_LLSC; 1212 c->tlbsize = 48; 1213 break; 1214 case PRID_IMP_TX49: 1215 c->cputype = CPU_TX49XX; 1216 __cpu_name[cpu] = "R49XX"; 1217 set_isa(c, MIPS_CPU_ISA_III); 1218 c->fpu_msk31 |= FPU_CSR_CONDX; 1219 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1220 if (!(c->processor_id & 0x08)) 1221 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1222 c->tlbsize = 48; 1223 break; 1224 case PRID_IMP_R5000: 1225 c->cputype = CPU_R5000; 1226 __cpu_name[cpu] = "R5000"; 1227 set_isa(c, MIPS_CPU_ISA_IV); 1228 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1229 MIPS_CPU_LLSC; 1230 c->tlbsize = 48; 1231 break; 1232 case PRID_IMP_R5500: 1233 c->cputype = CPU_R5500; 1234 __cpu_name[cpu] = "R5500"; 1235 set_isa(c, MIPS_CPU_ISA_IV); 1236 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1237 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1238 c->tlbsize = 48; 1239 break; 1240 case PRID_IMP_NEVADA: 1241 c->cputype = CPU_NEVADA; 1242 __cpu_name[cpu] = "Nevada"; 1243 set_isa(c, MIPS_CPU_ISA_IV); 1244 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1245 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1246 c->tlbsize = 48; 1247 break; 1248 case PRID_IMP_RM7000: 1249 c->cputype = CPU_RM7000; 1250 __cpu_name[cpu] = "RM7000"; 1251 set_isa(c, MIPS_CPU_ISA_IV); 1252 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1253 MIPS_CPU_LLSC; 1254 /* 1255 * Undocumented RM7000: Bit 29 in the info register of 1256 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1257 * entries. 1258 * 1259 * 29 1 => 64 entry JTLB 1260 * 0 => 48 entry JTLB 1261 */ 1262 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1263 break; 1264 case PRID_IMP_R10000: 1265 c->cputype = CPU_R10000; 1266 __cpu_name[cpu] = "R10000"; 1267 set_isa(c, MIPS_CPU_ISA_IV); 1268 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1269 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1270 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1271 MIPS_CPU_LLSC; 1272 c->tlbsize = 64; 1273 break; 1274 case PRID_IMP_R12000: 1275 c->cputype = CPU_R12000; 1276 __cpu_name[cpu] = "R12000"; 1277 set_isa(c, MIPS_CPU_ISA_IV); 1278 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1279 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1280 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1281 MIPS_CPU_LLSC; 1282 c->tlbsize = 64; 1283 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1284 break; 1285 case PRID_IMP_R14000: 1286 if (((c->processor_id >> 4) & 0x0f) > 2) { 1287 c->cputype = CPU_R16000; 1288 __cpu_name[cpu] = "R16000"; 1289 } else { 1290 c->cputype = CPU_R14000; 1291 __cpu_name[cpu] = "R14000"; 1292 } 1293 set_isa(c, MIPS_CPU_ISA_IV); 1294 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1295 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1296 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1297 MIPS_CPU_LLSC; 1298 c->tlbsize = 64; 1299 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1300 break; 1301 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ 1302 switch (c->processor_id & PRID_REV_MASK) { 1303 case PRID_REV_LOONGSON2E: 1304 c->cputype = CPU_LOONGSON2EF; 1305 __cpu_name[cpu] = "ICT Loongson-2"; 1306 set_elf_platform(cpu, "loongson2e"); 1307 set_isa(c, MIPS_CPU_ISA_III); 1308 c->fpu_msk31 |= FPU_CSR_CONDX; 1309 break; 1310 case PRID_REV_LOONGSON2F: 1311 c->cputype = CPU_LOONGSON2EF; 1312 __cpu_name[cpu] = "ICT Loongson-2"; 1313 set_elf_platform(cpu, "loongson2f"); 1314 set_isa(c, MIPS_CPU_ISA_III); 1315 c->fpu_msk31 |= FPU_CSR_CONDX; 1316 break; 1317 case PRID_REV_LOONGSON3A_R1: 1318 c->cputype = CPU_LOONGSON64; 1319 __cpu_name[cpu] = "ICT Loongson-3"; 1320 set_elf_platform(cpu, "loongson3a"); 1321 set_isa(c, MIPS_CPU_ISA_M64R1); 1322 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1323 MIPS_ASE_LOONGSON_EXT); 1324 break; 1325 case PRID_REV_LOONGSON3B_R1: 1326 case PRID_REV_LOONGSON3B_R2: 1327 c->cputype = CPU_LOONGSON64; 1328 __cpu_name[cpu] = "ICT Loongson-3"; 1329 set_elf_platform(cpu, "loongson3b"); 1330 set_isa(c, MIPS_CPU_ISA_M64R1); 1331 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1332 MIPS_ASE_LOONGSON_EXT); 1333 break; 1334 } 1335 1336 c->options = R4K_OPTS | 1337 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1338 MIPS_CPU_32FPR; 1339 c->tlbsize = 64; 1340 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); 1341 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1342 break; 1343 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1344 decode_configs(c); 1345 1346 c->cputype = CPU_LOONGSON32; 1347 1348 switch (c->processor_id & PRID_REV_MASK) { 1349 case PRID_REV_LOONGSON1B: 1350 __cpu_name[cpu] = "Loongson 1B"; 1351 break; 1352 } 1353 1354 break; 1355 } 1356 } 1357 1358 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1359 { 1360 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1361 switch (c->processor_id & PRID_IMP_MASK) { 1362 case PRID_IMP_QEMU_GENERIC: 1363 c->writecombine = _CACHE_UNCACHED; 1364 c->cputype = CPU_QEMU_GENERIC; 1365 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1366 break; 1367 case PRID_IMP_4KC: 1368 c->cputype = CPU_4KC; 1369 c->writecombine = _CACHE_UNCACHED; 1370 __cpu_name[cpu] = "MIPS 4Kc"; 1371 break; 1372 case PRID_IMP_4KEC: 1373 case PRID_IMP_4KECR2: 1374 c->cputype = CPU_4KEC; 1375 c->writecombine = _CACHE_UNCACHED; 1376 __cpu_name[cpu] = "MIPS 4KEc"; 1377 break; 1378 case PRID_IMP_4KSC: 1379 case PRID_IMP_4KSD: 1380 c->cputype = CPU_4KSC; 1381 c->writecombine = _CACHE_UNCACHED; 1382 __cpu_name[cpu] = "MIPS 4KSc"; 1383 break; 1384 case PRID_IMP_5KC: 1385 c->cputype = CPU_5KC; 1386 c->writecombine = _CACHE_UNCACHED; 1387 __cpu_name[cpu] = "MIPS 5Kc"; 1388 break; 1389 case PRID_IMP_5KE: 1390 c->cputype = CPU_5KE; 1391 c->writecombine = _CACHE_UNCACHED; 1392 __cpu_name[cpu] = "MIPS 5KE"; 1393 break; 1394 case PRID_IMP_20KC: 1395 c->cputype = CPU_20KC; 1396 c->writecombine = _CACHE_UNCACHED; 1397 __cpu_name[cpu] = "MIPS 20Kc"; 1398 break; 1399 case PRID_IMP_24K: 1400 c->cputype = CPU_24K; 1401 c->writecombine = _CACHE_UNCACHED; 1402 __cpu_name[cpu] = "MIPS 24Kc"; 1403 break; 1404 case PRID_IMP_24KE: 1405 c->cputype = CPU_24K; 1406 c->writecombine = _CACHE_UNCACHED; 1407 __cpu_name[cpu] = "MIPS 24KEc"; 1408 break; 1409 case PRID_IMP_25KF: 1410 c->cputype = CPU_25KF; 1411 c->writecombine = _CACHE_UNCACHED; 1412 __cpu_name[cpu] = "MIPS 25Kc"; 1413 break; 1414 case PRID_IMP_34K: 1415 c->cputype = CPU_34K; 1416 c->writecombine = _CACHE_UNCACHED; 1417 __cpu_name[cpu] = "MIPS 34Kc"; 1418 cpu_set_mt_per_tc_perf(c); 1419 break; 1420 case PRID_IMP_74K: 1421 c->cputype = CPU_74K; 1422 c->writecombine = _CACHE_UNCACHED; 1423 __cpu_name[cpu] = "MIPS 74Kc"; 1424 break; 1425 case PRID_IMP_M14KC: 1426 c->cputype = CPU_M14KC; 1427 c->writecombine = _CACHE_UNCACHED; 1428 __cpu_name[cpu] = "MIPS M14Kc"; 1429 break; 1430 case PRID_IMP_M14KEC: 1431 c->cputype = CPU_M14KEC; 1432 c->writecombine = _CACHE_UNCACHED; 1433 __cpu_name[cpu] = "MIPS M14KEc"; 1434 break; 1435 case PRID_IMP_1004K: 1436 c->cputype = CPU_1004K; 1437 c->writecombine = _CACHE_UNCACHED; 1438 __cpu_name[cpu] = "MIPS 1004Kc"; 1439 cpu_set_mt_per_tc_perf(c); 1440 break; 1441 case PRID_IMP_1074K: 1442 c->cputype = CPU_1074K; 1443 c->writecombine = _CACHE_UNCACHED; 1444 __cpu_name[cpu] = "MIPS 1074Kc"; 1445 break; 1446 case PRID_IMP_INTERAPTIV_UP: 1447 c->cputype = CPU_INTERAPTIV; 1448 __cpu_name[cpu] = "MIPS interAptiv"; 1449 cpu_set_mt_per_tc_perf(c); 1450 break; 1451 case PRID_IMP_INTERAPTIV_MP: 1452 c->cputype = CPU_INTERAPTIV; 1453 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1454 cpu_set_mt_per_tc_perf(c); 1455 break; 1456 case PRID_IMP_PROAPTIV_UP: 1457 c->cputype = CPU_PROAPTIV; 1458 __cpu_name[cpu] = "MIPS proAptiv"; 1459 break; 1460 case PRID_IMP_PROAPTIV_MP: 1461 c->cputype = CPU_PROAPTIV; 1462 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1463 break; 1464 case PRID_IMP_P5600: 1465 c->cputype = CPU_P5600; 1466 __cpu_name[cpu] = "MIPS P5600"; 1467 break; 1468 case PRID_IMP_P6600: 1469 c->cputype = CPU_P6600; 1470 __cpu_name[cpu] = "MIPS P6600"; 1471 break; 1472 case PRID_IMP_I6400: 1473 c->cputype = CPU_I6400; 1474 __cpu_name[cpu] = "MIPS I6400"; 1475 break; 1476 case PRID_IMP_I6500: 1477 c->cputype = CPU_I6500; 1478 __cpu_name[cpu] = "MIPS I6500"; 1479 break; 1480 case PRID_IMP_M5150: 1481 c->cputype = CPU_M5150; 1482 __cpu_name[cpu] = "MIPS M5150"; 1483 break; 1484 case PRID_IMP_M6250: 1485 c->cputype = CPU_M6250; 1486 __cpu_name[cpu] = "MIPS M6250"; 1487 break; 1488 } 1489 1490 decode_configs(c); 1491 1492 spram_config(); 1493 1494 mm_config(c); 1495 1496 switch (__get_cpu_type(c->cputype)) { 1497 case CPU_M5150: 1498 case CPU_P5600: 1499 set_isa(c, MIPS_CPU_ISA_M32R5); 1500 break; 1501 case CPU_I6500: 1502 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1503 fallthrough; 1504 case CPU_I6400: 1505 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1506 fallthrough; 1507 default: 1508 break; 1509 } 1510 1511 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for 1512 * cache/FTLB parity exceptions. 1513 */ 1514 switch (__get_cpu_type(c->cputype)) { 1515 case CPU_PROAPTIV: 1516 case CPU_P5600: 1517 case CPU_P6600: 1518 case CPU_I6400: 1519 case CPU_I6500: 1520 c->options |= MIPS_CPU_FTLBPAREX; 1521 break; 1522 } 1523 } 1524 1525 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1526 { 1527 decode_configs(c); 1528 switch (c->processor_id & PRID_IMP_MASK) { 1529 case PRID_IMP_AU1_REV1: 1530 case PRID_IMP_AU1_REV2: 1531 c->cputype = CPU_ALCHEMY; 1532 switch ((c->processor_id >> 24) & 0xff) { 1533 case 0: 1534 __cpu_name[cpu] = "Au1000"; 1535 break; 1536 case 1: 1537 __cpu_name[cpu] = "Au1500"; 1538 break; 1539 case 2: 1540 __cpu_name[cpu] = "Au1100"; 1541 break; 1542 case 3: 1543 __cpu_name[cpu] = "Au1550"; 1544 break; 1545 case 4: 1546 __cpu_name[cpu] = "Au1200"; 1547 if ((c->processor_id & PRID_REV_MASK) == 2) 1548 __cpu_name[cpu] = "Au1250"; 1549 break; 1550 case 5: 1551 __cpu_name[cpu] = "Au1210"; 1552 break; 1553 default: 1554 __cpu_name[cpu] = "Au1xxx"; 1555 break; 1556 } 1557 break; 1558 } 1559 } 1560 1561 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1562 { 1563 decode_configs(c); 1564 1565 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1566 switch (c->processor_id & PRID_IMP_MASK) { 1567 case PRID_IMP_SB1: 1568 c->cputype = CPU_SB1; 1569 __cpu_name[cpu] = "SiByte SB1"; 1570 /* FPU in pass1 is known to have issues. */ 1571 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1572 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1573 break; 1574 case PRID_IMP_SB1A: 1575 c->cputype = CPU_SB1A; 1576 __cpu_name[cpu] = "SiByte SB1A"; 1577 break; 1578 } 1579 } 1580 1581 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1582 { 1583 decode_configs(c); 1584 switch (c->processor_id & PRID_IMP_MASK) { 1585 case PRID_IMP_SR71000: 1586 c->cputype = CPU_SR71000; 1587 __cpu_name[cpu] = "Sandcraft SR71000"; 1588 c->scache.ways = 8; 1589 c->tlbsize = 64; 1590 break; 1591 } 1592 } 1593 1594 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1595 { 1596 decode_configs(c); 1597 switch (c->processor_id & PRID_IMP_MASK) { 1598 case PRID_IMP_PR4450: 1599 c->cputype = CPU_PR4450; 1600 __cpu_name[cpu] = "Philips PR4450"; 1601 set_isa(c, MIPS_CPU_ISA_M32R1); 1602 break; 1603 } 1604 } 1605 1606 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1607 { 1608 decode_configs(c); 1609 switch (c->processor_id & PRID_IMP_MASK) { 1610 case PRID_IMP_BMIPS32_REV4: 1611 case PRID_IMP_BMIPS32_REV8: 1612 c->cputype = CPU_BMIPS32; 1613 __cpu_name[cpu] = "Broadcom BMIPS32"; 1614 set_elf_platform(cpu, "bmips32"); 1615 break; 1616 case PRID_IMP_BMIPS3300: 1617 case PRID_IMP_BMIPS3300_ALT: 1618 case PRID_IMP_BMIPS3300_BUG: 1619 c->cputype = CPU_BMIPS3300; 1620 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1621 set_elf_platform(cpu, "bmips3300"); 1622 break; 1623 case PRID_IMP_BMIPS43XX: { 1624 int rev = c->processor_id & PRID_REV_MASK; 1625 1626 if (rev >= PRID_REV_BMIPS4380_LO && 1627 rev <= PRID_REV_BMIPS4380_HI) { 1628 c->cputype = CPU_BMIPS4380; 1629 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1630 set_elf_platform(cpu, "bmips4380"); 1631 c->options |= MIPS_CPU_RIXI; 1632 } else { 1633 c->cputype = CPU_BMIPS4350; 1634 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1635 set_elf_platform(cpu, "bmips4350"); 1636 } 1637 break; 1638 } 1639 case PRID_IMP_BMIPS5000: 1640 case PRID_IMP_BMIPS5200: 1641 c->cputype = CPU_BMIPS5000; 1642 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1643 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1644 else 1645 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1646 set_elf_platform(cpu, "bmips5000"); 1647 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1648 break; 1649 } 1650 } 1651 1652 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1653 { 1654 decode_configs(c); 1655 switch (c->processor_id & PRID_IMP_MASK) { 1656 case PRID_IMP_CAVIUM_CN38XX: 1657 case PRID_IMP_CAVIUM_CN31XX: 1658 case PRID_IMP_CAVIUM_CN30XX: 1659 c->cputype = CPU_CAVIUM_OCTEON; 1660 __cpu_name[cpu] = "Cavium Octeon"; 1661 goto platform; 1662 case PRID_IMP_CAVIUM_CN58XX: 1663 case PRID_IMP_CAVIUM_CN56XX: 1664 case PRID_IMP_CAVIUM_CN50XX: 1665 case PRID_IMP_CAVIUM_CN52XX: 1666 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1667 __cpu_name[cpu] = "Cavium Octeon+"; 1668 platform: 1669 set_elf_platform(cpu, "octeon"); 1670 break; 1671 case PRID_IMP_CAVIUM_CN61XX: 1672 case PRID_IMP_CAVIUM_CN63XX: 1673 case PRID_IMP_CAVIUM_CN66XX: 1674 case PRID_IMP_CAVIUM_CN68XX: 1675 case PRID_IMP_CAVIUM_CNF71XX: 1676 c->cputype = CPU_CAVIUM_OCTEON2; 1677 __cpu_name[cpu] = "Cavium Octeon II"; 1678 set_elf_platform(cpu, "octeon2"); 1679 break; 1680 case PRID_IMP_CAVIUM_CN70XX: 1681 case PRID_IMP_CAVIUM_CN73XX: 1682 case PRID_IMP_CAVIUM_CNF75XX: 1683 case PRID_IMP_CAVIUM_CN78XX: 1684 c->cputype = CPU_CAVIUM_OCTEON3; 1685 __cpu_name[cpu] = "Cavium Octeon III"; 1686 set_elf_platform(cpu, "octeon3"); 1687 break; 1688 default: 1689 printk(KERN_INFO "Unknown Octeon chip!\n"); 1690 c->cputype = CPU_UNKNOWN; 1691 break; 1692 } 1693 } 1694 1695 #ifdef CONFIG_CPU_LOONGSON64 1696 #include <loongson_regs.h> 1697 1698 static inline void decode_cpucfg(struct cpuinfo_mips *c) 1699 { 1700 u32 cfg1 = read_cpucfg(LOONGSON_CFG1); 1701 u32 cfg2 = read_cpucfg(LOONGSON_CFG2); 1702 u32 cfg3 = read_cpucfg(LOONGSON_CFG3); 1703 1704 if (cfg1 & LOONGSON_CFG1_MMI) 1705 c->ases |= MIPS_ASE_LOONGSON_MMI; 1706 1707 if (cfg2 & LOONGSON_CFG2_LEXT1) 1708 c->ases |= MIPS_ASE_LOONGSON_EXT; 1709 1710 if (cfg2 & LOONGSON_CFG2_LEXT2) 1711 c->ases |= MIPS_ASE_LOONGSON_EXT2; 1712 1713 if (cfg2 & LOONGSON_CFG2_LSPW) { 1714 c->options |= MIPS_CPU_LDPTE; 1715 c->guest.options |= MIPS_CPU_LDPTE; 1716 } 1717 1718 if (cfg3 & LOONGSON_CFG3_LCAMP) 1719 c->ases |= MIPS_ASE_LOONGSON_CAM; 1720 } 1721 1722 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1723 { 1724 decode_configs(c); 1725 1726 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ 1727 c->options |= MIPS_CPU_GSEXCEX; 1728 1729 switch (c->processor_id & PRID_IMP_MASK) { 1730 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ 1731 switch (c->processor_id & PRID_REV_MASK) { 1732 case PRID_REV_LOONGSON2K_R1_0: 1733 case PRID_REV_LOONGSON2K_R1_1: 1734 case PRID_REV_LOONGSON2K_R1_2: 1735 case PRID_REV_LOONGSON2K_R1_3: 1736 c->cputype = CPU_LOONGSON64; 1737 __cpu_name[cpu] = "Loongson-2K"; 1738 set_elf_platform(cpu, "gs264e"); 1739 set_isa(c, MIPS_CPU_ISA_M64R2); 1740 break; 1741 } 1742 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1743 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | 1744 MIPS_ASE_LOONGSON_EXT2); 1745 break; 1746 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ 1747 switch (c->processor_id & PRID_REV_MASK) { 1748 case PRID_REV_LOONGSON3A_R2_0: 1749 case PRID_REV_LOONGSON3A_R2_1: 1750 c->cputype = CPU_LOONGSON64; 1751 __cpu_name[cpu] = "ICT Loongson-3"; 1752 set_elf_platform(cpu, "loongson3a"); 1753 set_isa(c, MIPS_CPU_ISA_M64R2); 1754 break; 1755 case PRID_REV_LOONGSON3A_R3_0: 1756 case PRID_REV_LOONGSON3A_R3_1: 1757 c->cputype = CPU_LOONGSON64; 1758 __cpu_name[cpu] = "ICT Loongson-3"; 1759 set_elf_platform(cpu, "loongson3a"); 1760 set_isa(c, MIPS_CPU_ISA_M64R2); 1761 break; 1762 } 1763 /* 1764 * Loongson-3 Classic did not implement MIPS standard TLBINV 1765 * but implemented TLBINVF and EHINV. As currently we're only 1766 * using these two features, enable MIPS_CPU_TLBINV as well. 1767 * 1768 * Also some early Loongson-3A2000 had wrong TLB type in Config 1769 * register, we correct it here. 1770 */ 1771 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1772 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1773 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1774 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); 1775 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ 1776 break; 1777 case PRID_IMP_LOONGSON_64G: 1778 c->cputype = CPU_LOONGSON64; 1779 __cpu_name[cpu] = "ICT Loongson-3"; 1780 set_elf_platform(cpu, "loongson3a"); 1781 set_isa(c, MIPS_CPU_ISA_M64R2); 1782 decode_cpucfg(c); 1783 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1784 break; 1785 default: 1786 panic("Unknown Loongson Processor ID!"); 1787 break; 1788 } 1789 } 1790 #else 1791 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { } 1792 #endif 1793 1794 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1795 { 1796 decode_configs(c); 1797 1798 /* 1799 * XBurst misses a config2 register, so config3 decode was skipped in 1800 * decode_configs(). 1801 */ 1802 decode_config3(c); 1803 1804 /* XBurst does not implement the CP0 counter. */ 1805 c->options &= ~MIPS_CPU_COUNTER; 1806 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); 1807 1808 /* XBurst has virtually tagged icache */ 1809 c->icache.flags |= MIPS_CACHE_VTAG; 1810 1811 switch (c->processor_id & PRID_IMP_MASK) { 1812 1813 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ 1814 case PRID_IMP_XBURST_REV1: 1815 1816 /* 1817 * The XBurst core by default attempts to avoid branch target 1818 * buffer lookups by detecting & special casing loops. This 1819 * feature will cause BogoMIPS and lpj calculate in error. 1820 * Set cp0 config7 bit 4 to disable this feature. 1821 */ 1822 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); 1823 1824 switch (c->processor_id & PRID_COMP_MASK) { 1825 1826 /* 1827 * The config0 register in the XBurst CPUs with a processor ID of 1828 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1829 * but they don't actually support this ISA. 1830 */ 1831 case PRID_COMP_INGENIC_D0: 1832 c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1833 break; 1834 1835 /* 1836 * The config0 register in the XBurst CPUs with a processor ID of 1837 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this 1838 * mode is not compatible with the MIPS standard, it will cause 1839 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S) 1840 * when starting the init process. After chip reset, the default 1841 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to 1842 * switch back to VTLB mode to prevent getting stuck. 1843 */ 1844 case PRID_COMP_INGENIC_D1: 1845 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); 1846 break; 1847 1848 default: 1849 break; 1850 } 1851 fallthrough; 1852 1853 /* XBurst®1 with MXU2.0 SIMD ISA */ 1854 case PRID_IMP_XBURST_REV2: 1855 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 1856 c->writecombine = _CACHE_CACHABLE_WA; 1857 c->cputype = CPU_XBURST; 1858 __cpu_name[cpu] = "Ingenic XBurst"; 1859 break; 1860 1861 /* XBurst®2 with MXU2.1 SIMD ISA */ 1862 case PRID_IMP_XBURST2: 1863 c->cputype = CPU_XBURST; 1864 __cpu_name[cpu] = "Ingenic XBurst II"; 1865 break; 1866 1867 default: 1868 panic("Unknown Ingenic Processor ID!"); 1869 break; 1870 } 1871 } 1872 1873 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1874 { 1875 decode_configs(c); 1876 1877 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1878 c->cputype = CPU_ALCHEMY; 1879 __cpu_name[cpu] = "Au1300"; 1880 /* following stuff is not for Alchemy */ 1881 return; 1882 } 1883 1884 c->options = (MIPS_CPU_TLB | 1885 MIPS_CPU_4KEX | 1886 MIPS_CPU_COUNTER | 1887 MIPS_CPU_DIVEC | 1888 MIPS_CPU_WATCH | 1889 MIPS_CPU_EJTAG | 1890 MIPS_CPU_LLSC); 1891 1892 switch (c->processor_id & PRID_IMP_MASK) { 1893 case PRID_IMP_NETLOGIC_XLP2XX: 1894 case PRID_IMP_NETLOGIC_XLP9XX: 1895 case PRID_IMP_NETLOGIC_XLP5XX: 1896 c->cputype = CPU_XLP; 1897 __cpu_name[cpu] = "Broadcom XLPII"; 1898 break; 1899 1900 case PRID_IMP_NETLOGIC_XLP8XX: 1901 case PRID_IMP_NETLOGIC_XLP3XX: 1902 c->cputype = CPU_XLP; 1903 __cpu_name[cpu] = "Netlogic XLP"; 1904 break; 1905 1906 case PRID_IMP_NETLOGIC_XLR732: 1907 case PRID_IMP_NETLOGIC_XLR716: 1908 case PRID_IMP_NETLOGIC_XLR532: 1909 case PRID_IMP_NETLOGIC_XLR308: 1910 case PRID_IMP_NETLOGIC_XLR532C: 1911 case PRID_IMP_NETLOGIC_XLR516C: 1912 case PRID_IMP_NETLOGIC_XLR508C: 1913 case PRID_IMP_NETLOGIC_XLR308C: 1914 c->cputype = CPU_XLR; 1915 __cpu_name[cpu] = "Netlogic XLR"; 1916 break; 1917 1918 case PRID_IMP_NETLOGIC_XLS608: 1919 case PRID_IMP_NETLOGIC_XLS408: 1920 case PRID_IMP_NETLOGIC_XLS404: 1921 case PRID_IMP_NETLOGIC_XLS208: 1922 case PRID_IMP_NETLOGIC_XLS204: 1923 case PRID_IMP_NETLOGIC_XLS108: 1924 case PRID_IMP_NETLOGIC_XLS104: 1925 case PRID_IMP_NETLOGIC_XLS616B: 1926 case PRID_IMP_NETLOGIC_XLS608B: 1927 case PRID_IMP_NETLOGIC_XLS416B: 1928 case PRID_IMP_NETLOGIC_XLS412B: 1929 case PRID_IMP_NETLOGIC_XLS408B: 1930 case PRID_IMP_NETLOGIC_XLS404B: 1931 c->cputype = CPU_XLR; 1932 __cpu_name[cpu] = "Netlogic XLS"; 1933 break; 1934 1935 default: 1936 pr_info("Unknown Netlogic chip id [%02x]!\n", 1937 c->processor_id); 1938 c->cputype = CPU_XLR; 1939 break; 1940 } 1941 1942 if (c->cputype == CPU_XLP) { 1943 set_isa(c, MIPS_CPU_ISA_M64R2); 1944 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1945 /* This will be updated again after all threads are woken up */ 1946 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1947 } else { 1948 set_isa(c, MIPS_CPU_ISA_M64R1); 1949 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1950 } 1951 c->kscratch_mask = 0xf; 1952 } 1953 1954 #ifdef CONFIG_64BIT 1955 /* For use by uaccess.h */ 1956 u64 __ua_limit; 1957 EXPORT_SYMBOL(__ua_limit); 1958 #endif 1959 1960 const char *__cpu_name[NR_CPUS]; 1961 const char *__elf_platform; 1962 const char *__elf_base_platform; 1963 1964 void cpu_probe(void) 1965 { 1966 struct cpuinfo_mips *c = ¤t_cpu_data; 1967 unsigned int cpu = smp_processor_id(); 1968 1969 /* 1970 * Set a default elf platform, cpu probe may later 1971 * overwrite it with a more precise value 1972 */ 1973 set_elf_platform(cpu, "mips"); 1974 1975 c->processor_id = PRID_IMP_UNKNOWN; 1976 c->fpu_id = FPIR_IMP_NONE; 1977 c->cputype = CPU_UNKNOWN; 1978 c->writecombine = _CACHE_UNCACHED; 1979 1980 c->fpu_csr31 = FPU_CSR_RN; 1981 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1982 1983 c->processor_id = read_c0_prid(); 1984 switch (c->processor_id & PRID_COMP_MASK) { 1985 case PRID_COMP_LEGACY: 1986 cpu_probe_legacy(c, cpu); 1987 break; 1988 case PRID_COMP_MIPS: 1989 cpu_probe_mips(c, cpu); 1990 break; 1991 case PRID_COMP_ALCHEMY: 1992 cpu_probe_alchemy(c, cpu); 1993 break; 1994 case PRID_COMP_SIBYTE: 1995 cpu_probe_sibyte(c, cpu); 1996 break; 1997 case PRID_COMP_BROADCOM: 1998 cpu_probe_broadcom(c, cpu); 1999 break; 2000 case PRID_COMP_SANDCRAFT: 2001 cpu_probe_sandcraft(c, cpu); 2002 break; 2003 case PRID_COMP_NXP: 2004 cpu_probe_nxp(c, cpu); 2005 break; 2006 case PRID_COMP_CAVIUM: 2007 cpu_probe_cavium(c, cpu); 2008 break; 2009 case PRID_COMP_LOONGSON: 2010 cpu_probe_loongson(c, cpu); 2011 break; 2012 case PRID_COMP_INGENIC_13: 2013 case PRID_COMP_INGENIC_D0: 2014 case PRID_COMP_INGENIC_D1: 2015 case PRID_COMP_INGENIC_E1: 2016 cpu_probe_ingenic(c, cpu); 2017 break; 2018 case PRID_COMP_NETLOGIC: 2019 cpu_probe_netlogic(c, cpu); 2020 break; 2021 } 2022 2023 BUG_ON(!__cpu_name[cpu]); 2024 BUG_ON(c->cputype == CPU_UNKNOWN); 2025 2026 /* 2027 * Platform code can force the cpu type to optimize code 2028 * generation. In that case be sure the cpu type is correctly 2029 * manually setup otherwise it could trigger some nasty bugs. 2030 */ 2031 BUG_ON(current_cpu_type() != c->cputype); 2032 2033 if (cpu_has_rixi) { 2034 /* Enable the RIXI exceptions */ 2035 set_c0_pagegrain(PG_IEC); 2036 back_to_back_c0_hazard(); 2037 /* Verify the IEC bit is set */ 2038 if (read_c0_pagegrain() & PG_IEC) 2039 c->options |= MIPS_CPU_RIXIEX; 2040 } 2041 2042 if (mips_fpu_disabled) 2043 c->options &= ~MIPS_CPU_FPU; 2044 2045 if (mips_dsp_disabled) 2046 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2047 2048 if (mips_htw_disabled) { 2049 c->options &= ~MIPS_CPU_HTW; 2050 write_c0_pwctl(read_c0_pwctl() & 2051 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2052 } 2053 2054 if (c->options & MIPS_CPU_FPU) 2055 cpu_set_fpu_opts(c); 2056 else 2057 cpu_set_nofpu_opts(c); 2058 2059 if (cpu_has_mips_r2_r6) { 2060 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2061 /* R2 has Performance Counter Interrupt indicator */ 2062 c->options |= MIPS_CPU_PCI; 2063 } 2064 else 2065 c->srsets = 1; 2066 2067 if (cpu_has_mips_r6) 2068 elf_hwcap |= HWCAP_MIPS_R6; 2069 2070 if (cpu_has_msa) { 2071 c->msa_id = cpu_get_msa_id(); 2072 WARN(c->msa_id & MSA_IR_WRPF, 2073 "Vector register partitioning unimplemented!"); 2074 elf_hwcap |= HWCAP_MIPS_MSA; 2075 } 2076 2077 if (cpu_has_mips16) 2078 elf_hwcap |= HWCAP_MIPS_MIPS16; 2079 2080 if (cpu_has_mdmx) 2081 elf_hwcap |= HWCAP_MIPS_MDMX; 2082 2083 if (cpu_has_mips3d) 2084 elf_hwcap |= HWCAP_MIPS_MIPS3D; 2085 2086 if (cpu_has_smartmips) 2087 elf_hwcap |= HWCAP_MIPS_SMARTMIPS; 2088 2089 if (cpu_has_dsp) 2090 elf_hwcap |= HWCAP_MIPS_DSP; 2091 2092 if (cpu_has_dsp2) 2093 elf_hwcap |= HWCAP_MIPS_DSP2; 2094 2095 if (cpu_has_dsp3) 2096 elf_hwcap |= HWCAP_MIPS_DSP3; 2097 2098 if (cpu_has_mips16e2) 2099 elf_hwcap |= HWCAP_MIPS_MIPS16E2; 2100 2101 if (cpu_has_loongson_mmi) 2102 elf_hwcap |= HWCAP_LOONGSON_MMI; 2103 2104 if (cpu_has_loongson_ext) 2105 elf_hwcap |= HWCAP_LOONGSON_EXT; 2106 2107 if (cpu_has_loongson_ext2) 2108 elf_hwcap |= HWCAP_LOONGSON_EXT2; 2109 2110 if (cpu_has_vz) 2111 cpu_probe_vz(c); 2112 2113 cpu_probe_vmbits(c); 2114 2115 /* Synthesize CPUCFG data if running on Loongson processors; 2116 * no-op otherwise. 2117 * 2118 * This looks at previously probed features, so keep this at bottom. 2119 */ 2120 loongson3_cpucfg_synthesize_data(c); 2121 2122 #ifdef CONFIG_64BIT 2123 if (cpu == 0) 2124 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2125 #endif 2126 } 2127 2128 void cpu_report(void) 2129 { 2130 struct cpuinfo_mips *c = ¤t_cpu_data; 2131 2132 pr_info("CPU%d revision is: %08x (%s)\n", 2133 smp_processor_id(), c->processor_id, cpu_name_string()); 2134 if (c->options & MIPS_CPU_FPU) 2135 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2136 if (cpu_has_msa) 2137 pr_info("MSA revision is: %08x\n", c->msa_id); 2138 } 2139 2140 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) 2141 { 2142 /* Ensure the core number fits in the field */ 2143 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> 2144 MIPS_GLOBALNUMBER_CLUSTER_SHF)); 2145 2146 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; 2147 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; 2148 } 2149 2150 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) 2151 { 2152 /* Ensure the core number fits in the field */ 2153 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); 2154 2155 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; 2156 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; 2157 } 2158 2159 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) 2160 { 2161 /* Ensure the VP(E) ID fits in the field */ 2162 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); 2163 2164 /* Ensure we're not using VP(E)s without support */ 2165 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && 2166 !IS_ENABLED(CONFIG_CPU_MIPSR6)); 2167 2168 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; 2169 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; 2170 } 2171