1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/mipsmtregs.h> 27 #include <asm/msa.h> 28 #include <asm/watch.h> 29 #include <asm/elf.h> 30 #include <asm/spram.h> 31 #include <asm/uaccess.h> 32 33 static int mips_fpu_disabled; 34 35 static int __init fpu_disable(char *s) 36 { 37 cpu_data[0].options &= ~MIPS_CPU_FPU; 38 mips_fpu_disabled = 1; 39 40 return 1; 41 } 42 43 __setup("nofpu", fpu_disable); 44 45 int mips_dsp_disabled; 46 47 static int __init dsp_disable(char *s) 48 { 49 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 50 mips_dsp_disabled = 1; 51 52 return 1; 53 } 54 55 __setup("nodsp", dsp_disable); 56 57 static inline void check_errata(void) 58 { 59 struct cpuinfo_mips *c = ¤t_cpu_data; 60 61 switch (current_cpu_type()) { 62 case CPU_34K: 63 /* 64 * Erratum "RPS May Cause Incorrect Instruction Execution" 65 * This code only handles VPE0, any SMP/SMTC/RTOS code 66 * making use of VPE1 will be responsable for that VPE. 67 */ 68 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 69 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 70 break; 71 default: 72 break; 73 } 74 } 75 76 void __init check_bugs32(void) 77 { 78 check_errata(); 79 } 80 81 /* 82 * Probe whether cpu has config register by trying to play with 83 * alternate cache bit and see whether it matters. 84 * It's used by cpu_probe to distinguish between R3000A and R3081. 85 */ 86 static inline int cpu_has_confreg(void) 87 { 88 #ifdef CONFIG_CPU_R3000 89 extern unsigned long r3k_cache_size(unsigned long); 90 unsigned long size1, size2; 91 unsigned long cfg = read_c0_conf(); 92 93 size1 = r3k_cache_size(ST0_ISC); 94 write_c0_conf(cfg ^ R30XX_CONF_AC); 95 size2 = r3k_cache_size(ST0_ISC); 96 write_c0_conf(cfg); 97 return size1 != size2; 98 #else 99 return 0; 100 #endif 101 } 102 103 static inline void set_elf_platform(int cpu, const char *plat) 104 { 105 if (cpu == 0) 106 __elf_platform = plat; 107 } 108 109 /* 110 * Get the FPU Implementation/Revision. 111 */ 112 static inline unsigned long cpu_get_fpu_id(void) 113 { 114 unsigned long tmp, fpu_id; 115 116 tmp = read_c0_status(); 117 __enable_fpu(FPU_AS_IS); 118 fpu_id = read_32bit_cp1_register(CP1_REVISION); 119 write_c0_status(tmp); 120 return fpu_id; 121 } 122 123 /* 124 * Check the CPU has an FPU the official way. 125 */ 126 static inline int __cpu_has_fpu(void) 127 { 128 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); 129 } 130 131 static inline unsigned long cpu_get_msa_id(void) 132 { 133 unsigned long status, conf5, msa_id; 134 135 status = read_c0_status(); 136 __enable_fpu(FPU_64BIT); 137 conf5 = read_c0_config5(); 138 enable_msa(); 139 msa_id = read_msa_ir(); 140 write_c0_config5(conf5); 141 write_c0_status(status); 142 return msa_id; 143 } 144 145 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 146 { 147 #ifdef __NEED_VMBITS_PROBE 148 write_c0_entryhi(0x3fffffffffffe000ULL); 149 back_to_back_c0_hazard(); 150 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 151 #endif 152 } 153 154 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 155 { 156 switch (isa) { 157 case MIPS_CPU_ISA_M64R2: 158 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 159 case MIPS_CPU_ISA_M64R1: 160 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 161 case MIPS_CPU_ISA_V: 162 c->isa_level |= MIPS_CPU_ISA_V; 163 case MIPS_CPU_ISA_IV: 164 c->isa_level |= MIPS_CPU_ISA_IV; 165 case MIPS_CPU_ISA_III: 166 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 167 break; 168 169 case MIPS_CPU_ISA_M32R2: 170 c->isa_level |= MIPS_CPU_ISA_M32R2; 171 case MIPS_CPU_ISA_M32R1: 172 c->isa_level |= MIPS_CPU_ISA_M32R1; 173 case MIPS_CPU_ISA_II: 174 c->isa_level |= MIPS_CPU_ISA_II; 175 break; 176 } 177 } 178 179 static char unknown_isa[] = KERN_ERR \ 180 "Unsupported ISA type, c0.config0: %d."; 181 182 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 183 { 184 unsigned int config6; 185 186 /* It's implementation dependent how the FTLB can be enabled */ 187 switch (c->cputype) { 188 case CPU_PROAPTIV: 189 case CPU_P5600: 190 /* proAptiv & related cores use Config6 to enable the FTLB */ 191 config6 = read_c0_config6(); 192 if (enable) 193 /* Enable FTLB */ 194 write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 195 else 196 /* Disable FTLB */ 197 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 198 back_to_back_c0_hazard(); 199 break; 200 } 201 } 202 203 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 204 { 205 unsigned int config0; 206 int isa; 207 208 config0 = read_c0_config(); 209 210 /* 211 * Look for Standard TLB or Dual VTLB and FTLB 212 */ 213 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 214 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 215 c->options |= MIPS_CPU_TLB; 216 217 isa = (config0 & MIPS_CONF_AT) >> 13; 218 switch (isa) { 219 case 0: 220 switch ((config0 & MIPS_CONF_AR) >> 10) { 221 case 0: 222 set_isa(c, MIPS_CPU_ISA_M32R1); 223 break; 224 case 1: 225 set_isa(c, MIPS_CPU_ISA_M32R2); 226 break; 227 default: 228 goto unknown; 229 } 230 break; 231 case 2: 232 switch ((config0 & MIPS_CONF_AR) >> 10) { 233 case 0: 234 set_isa(c, MIPS_CPU_ISA_M64R1); 235 break; 236 case 1: 237 set_isa(c, MIPS_CPU_ISA_M64R2); 238 break; 239 default: 240 goto unknown; 241 } 242 break; 243 default: 244 goto unknown; 245 } 246 247 return config0 & MIPS_CONF_M; 248 249 unknown: 250 panic(unknown_isa, config0); 251 } 252 253 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 254 { 255 unsigned int config1; 256 257 config1 = read_c0_config1(); 258 259 if (config1 & MIPS_CONF1_MD) 260 c->ases |= MIPS_ASE_MDMX; 261 if (config1 & MIPS_CONF1_WR) 262 c->options |= MIPS_CPU_WATCH; 263 if (config1 & MIPS_CONF1_CA) 264 c->ases |= MIPS_ASE_MIPS16; 265 if (config1 & MIPS_CONF1_EP) 266 c->options |= MIPS_CPU_EJTAG; 267 if (config1 & MIPS_CONF1_FP) { 268 c->options |= MIPS_CPU_FPU; 269 c->options |= MIPS_CPU_32FPR; 270 } 271 if (cpu_has_tlb) { 272 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 273 c->tlbsizevtlb = c->tlbsize; 274 c->tlbsizeftlbsets = 0; 275 } 276 277 return config1 & MIPS_CONF_M; 278 } 279 280 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 281 { 282 unsigned int config2; 283 284 config2 = read_c0_config2(); 285 286 if (config2 & MIPS_CONF2_SL) 287 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 288 289 return config2 & MIPS_CONF_M; 290 } 291 292 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 293 { 294 unsigned int config3; 295 296 config3 = read_c0_config3(); 297 298 if (config3 & MIPS_CONF3_SM) { 299 c->ases |= MIPS_ASE_SMARTMIPS; 300 c->options |= MIPS_CPU_RIXI; 301 } 302 if (config3 & MIPS_CONF3_RXI) 303 c->options |= MIPS_CPU_RIXI; 304 if (config3 & MIPS_CONF3_DSP) 305 c->ases |= MIPS_ASE_DSP; 306 if (config3 & MIPS_CONF3_DSP2P) 307 c->ases |= MIPS_ASE_DSP2P; 308 if (config3 & MIPS_CONF3_VINT) 309 c->options |= MIPS_CPU_VINT; 310 if (config3 & MIPS_CONF3_VEIC) 311 c->options |= MIPS_CPU_VEIC; 312 if (config3 & MIPS_CONF3_MT) 313 c->ases |= MIPS_ASE_MIPSMT; 314 if (config3 & MIPS_CONF3_ULRI) 315 c->options |= MIPS_CPU_ULRI; 316 if (config3 & MIPS_CONF3_ISA) 317 c->options |= MIPS_CPU_MICROMIPS; 318 if (config3 & MIPS_CONF3_VZ) 319 c->ases |= MIPS_ASE_VZ; 320 if (config3 & MIPS_CONF3_SC) 321 c->options |= MIPS_CPU_SEGMENTS; 322 if (config3 & MIPS_CONF3_MSA) 323 c->ases |= MIPS_ASE_MSA; 324 325 return config3 & MIPS_CONF_M; 326 } 327 328 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 329 { 330 unsigned int config4; 331 unsigned int newcf4; 332 unsigned int mmuextdef; 333 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 334 335 config4 = read_c0_config4(); 336 337 if (cpu_has_tlb) { 338 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 339 c->options |= MIPS_CPU_TLBINV; 340 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 341 switch (mmuextdef) { 342 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 343 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 344 c->tlbsizevtlb = c->tlbsize; 345 break; 346 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 347 c->tlbsizevtlb += 348 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 349 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 350 c->tlbsize = c->tlbsizevtlb; 351 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 352 /* fall through */ 353 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 354 newcf4 = (config4 & ~ftlb_page) | 355 (page_size_ftlb(mmuextdef) << 356 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 357 write_c0_config4(newcf4); 358 back_to_back_c0_hazard(); 359 config4 = read_c0_config4(); 360 if (config4 != newcf4) { 361 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 362 PAGE_SIZE, config4); 363 /* Switch FTLB off */ 364 set_ftlb_enable(c, 0); 365 break; 366 } 367 c->tlbsizeftlbsets = 1 << 368 ((config4 & MIPS_CONF4_FTLBSETS) >> 369 MIPS_CONF4_FTLBSETS_SHIFT); 370 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 371 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 372 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 373 break; 374 } 375 } 376 377 c->kscratch_mask = (config4 >> 16) & 0xff; 378 379 return config4 & MIPS_CONF_M; 380 } 381 382 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 383 { 384 unsigned int config5; 385 386 config5 = read_c0_config5(); 387 config5 &= ~MIPS_CONF5_UFR; 388 write_c0_config5(config5); 389 390 if (config5 & MIPS_CONF5_EVA) 391 c->options |= MIPS_CPU_EVA; 392 393 return config5 & MIPS_CONF_M; 394 } 395 396 static void decode_configs(struct cpuinfo_mips *c) 397 { 398 int ok; 399 400 /* MIPS32 or MIPS64 compliant CPU. */ 401 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 402 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 403 404 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 405 406 /* Enable FTLB if present */ 407 set_ftlb_enable(c, 1); 408 409 ok = decode_config0(c); /* Read Config registers. */ 410 BUG_ON(!ok); /* Arch spec violation! */ 411 if (ok) 412 ok = decode_config1(c); 413 if (ok) 414 ok = decode_config2(c); 415 if (ok) 416 ok = decode_config3(c); 417 if (ok) 418 ok = decode_config4(c); 419 if (ok) 420 ok = decode_config5(c); 421 422 mips_probe_watch_registers(c); 423 424 #ifndef CONFIG_MIPS_CPS 425 if (cpu_has_mips_r2) { 426 c->core = read_c0_ebase() & 0x3ff; 427 if (cpu_has_mipsmt) 428 c->core >>= fls(core_nvpes()) - 1; 429 } 430 #endif 431 } 432 433 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 434 | MIPS_CPU_COUNTER) 435 436 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 437 { 438 switch (c->processor_id & PRID_IMP_MASK) { 439 case PRID_IMP_R2000: 440 c->cputype = CPU_R2000; 441 __cpu_name[cpu] = "R2000"; 442 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 443 MIPS_CPU_NOFPUEX; 444 if (__cpu_has_fpu()) 445 c->options |= MIPS_CPU_FPU; 446 c->tlbsize = 64; 447 break; 448 case PRID_IMP_R3000: 449 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 450 if (cpu_has_confreg()) { 451 c->cputype = CPU_R3081E; 452 __cpu_name[cpu] = "R3081"; 453 } else { 454 c->cputype = CPU_R3000A; 455 __cpu_name[cpu] = "R3000A"; 456 } 457 } else { 458 c->cputype = CPU_R3000; 459 __cpu_name[cpu] = "R3000"; 460 } 461 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 462 MIPS_CPU_NOFPUEX; 463 if (__cpu_has_fpu()) 464 c->options |= MIPS_CPU_FPU; 465 c->tlbsize = 64; 466 break; 467 case PRID_IMP_R4000: 468 if (read_c0_config() & CONF_SC) { 469 if ((c->processor_id & PRID_REV_MASK) >= 470 PRID_REV_R4400) { 471 c->cputype = CPU_R4400PC; 472 __cpu_name[cpu] = "R4400PC"; 473 } else { 474 c->cputype = CPU_R4000PC; 475 __cpu_name[cpu] = "R4000PC"; 476 } 477 } else { 478 int cca = read_c0_config() & CONF_CM_CMASK; 479 int mc; 480 481 /* 482 * SC and MC versions can't be reliably told apart, 483 * but only the latter support coherent caching 484 * modes so assume the firmware has set the KSEG0 485 * coherency attribute reasonably (if uncached, we 486 * assume SC). 487 */ 488 switch (cca) { 489 case CONF_CM_CACHABLE_CE: 490 case CONF_CM_CACHABLE_COW: 491 case CONF_CM_CACHABLE_CUW: 492 mc = 1; 493 break; 494 default: 495 mc = 0; 496 break; 497 } 498 if ((c->processor_id & PRID_REV_MASK) >= 499 PRID_REV_R4400) { 500 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 501 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 502 } else { 503 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 504 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 505 } 506 } 507 508 set_isa(c, MIPS_CPU_ISA_III); 509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 510 MIPS_CPU_WATCH | MIPS_CPU_VCE | 511 MIPS_CPU_LLSC; 512 c->tlbsize = 48; 513 break; 514 case PRID_IMP_VR41XX: 515 set_isa(c, MIPS_CPU_ISA_III); 516 c->options = R4K_OPTS; 517 c->tlbsize = 32; 518 switch (c->processor_id & 0xf0) { 519 case PRID_REV_VR4111: 520 c->cputype = CPU_VR4111; 521 __cpu_name[cpu] = "NEC VR4111"; 522 break; 523 case PRID_REV_VR4121: 524 c->cputype = CPU_VR4121; 525 __cpu_name[cpu] = "NEC VR4121"; 526 break; 527 case PRID_REV_VR4122: 528 if ((c->processor_id & 0xf) < 0x3) { 529 c->cputype = CPU_VR4122; 530 __cpu_name[cpu] = "NEC VR4122"; 531 } else { 532 c->cputype = CPU_VR4181A; 533 __cpu_name[cpu] = "NEC VR4181A"; 534 } 535 break; 536 case PRID_REV_VR4130: 537 if ((c->processor_id & 0xf) < 0x4) { 538 c->cputype = CPU_VR4131; 539 __cpu_name[cpu] = "NEC VR4131"; 540 } else { 541 c->cputype = CPU_VR4133; 542 c->options |= MIPS_CPU_LLSC; 543 __cpu_name[cpu] = "NEC VR4133"; 544 } 545 break; 546 default: 547 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 548 c->cputype = CPU_VR41XX; 549 __cpu_name[cpu] = "NEC Vr41xx"; 550 break; 551 } 552 break; 553 case PRID_IMP_R4300: 554 c->cputype = CPU_R4300; 555 __cpu_name[cpu] = "R4300"; 556 set_isa(c, MIPS_CPU_ISA_III); 557 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 558 MIPS_CPU_LLSC; 559 c->tlbsize = 32; 560 break; 561 case PRID_IMP_R4600: 562 c->cputype = CPU_R4600; 563 __cpu_name[cpu] = "R4600"; 564 set_isa(c, MIPS_CPU_ISA_III); 565 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 566 MIPS_CPU_LLSC; 567 c->tlbsize = 48; 568 break; 569 #if 0 570 case PRID_IMP_R4650: 571 /* 572 * This processor doesn't have an MMU, so it's not 573 * "real easy" to run Linux on it. It is left purely 574 * for documentation. Commented out because it shares 575 * it's c0_prid id number with the TX3900. 576 */ 577 c->cputype = CPU_R4650; 578 __cpu_name[cpu] = "R4650"; 579 set_isa(c, MIPS_CPU_ISA_III); 580 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 581 c->tlbsize = 48; 582 break; 583 #endif 584 case PRID_IMP_TX39: 585 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 586 587 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 588 c->cputype = CPU_TX3927; 589 __cpu_name[cpu] = "TX3927"; 590 c->tlbsize = 64; 591 } else { 592 switch (c->processor_id & PRID_REV_MASK) { 593 case PRID_REV_TX3912: 594 c->cputype = CPU_TX3912; 595 __cpu_name[cpu] = "TX3912"; 596 c->tlbsize = 32; 597 break; 598 case PRID_REV_TX3922: 599 c->cputype = CPU_TX3922; 600 __cpu_name[cpu] = "TX3922"; 601 c->tlbsize = 64; 602 break; 603 } 604 } 605 break; 606 case PRID_IMP_R4700: 607 c->cputype = CPU_R4700; 608 __cpu_name[cpu] = "R4700"; 609 set_isa(c, MIPS_CPU_ISA_III); 610 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 611 MIPS_CPU_LLSC; 612 c->tlbsize = 48; 613 break; 614 case PRID_IMP_TX49: 615 c->cputype = CPU_TX49XX; 616 __cpu_name[cpu] = "R49XX"; 617 set_isa(c, MIPS_CPU_ISA_III); 618 c->options = R4K_OPTS | MIPS_CPU_LLSC; 619 if (!(c->processor_id & 0x08)) 620 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 621 c->tlbsize = 48; 622 break; 623 case PRID_IMP_R5000: 624 c->cputype = CPU_R5000; 625 __cpu_name[cpu] = "R5000"; 626 set_isa(c, MIPS_CPU_ISA_IV); 627 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 628 MIPS_CPU_LLSC; 629 c->tlbsize = 48; 630 break; 631 case PRID_IMP_R5432: 632 c->cputype = CPU_R5432; 633 __cpu_name[cpu] = "R5432"; 634 set_isa(c, MIPS_CPU_ISA_IV); 635 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 636 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 637 c->tlbsize = 48; 638 break; 639 case PRID_IMP_R5500: 640 c->cputype = CPU_R5500; 641 __cpu_name[cpu] = "R5500"; 642 set_isa(c, MIPS_CPU_ISA_IV); 643 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 644 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 645 c->tlbsize = 48; 646 break; 647 case PRID_IMP_NEVADA: 648 c->cputype = CPU_NEVADA; 649 __cpu_name[cpu] = "Nevada"; 650 set_isa(c, MIPS_CPU_ISA_IV); 651 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 653 c->tlbsize = 48; 654 break; 655 case PRID_IMP_R6000: 656 c->cputype = CPU_R6000; 657 __cpu_name[cpu] = "R6000"; 658 set_isa(c, MIPS_CPU_ISA_II); 659 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 660 MIPS_CPU_LLSC; 661 c->tlbsize = 32; 662 break; 663 case PRID_IMP_R6000A: 664 c->cputype = CPU_R6000A; 665 __cpu_name[cpu] = "R6000A"; 666 set_isa(c, MIPS_CPU_ISA_II); 667 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 668 MIPS_CPU_LLSC; 669 c->tlbsize = 32; 670 break; 671 case PRID_IMP_RM7000: 672 c->cputype = CPU_RM7000; 673 __cpu_name[cpu] = "RM7000"; 674 set_isa(c, MIPS_CPU_ISA_IV); 675 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 676 MIPS_CPU_LLSC; 677 /* 678 * Undocumented RM7000: Bit 29 in the info register of 679 * the RM7000 v2.0 indicates if the TLB has 48 or 64 680 * entries. 681 * 682 * 29 1 => 64 entry JTLB 683 * 0 => 48 entry JTLB 684 */ 685 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 686 break; 687 case PRID_IMP_RM9000: 688 c->cputype = CPU_RM9000; 689 __cpu_name[cpu] = "RM9000"; 690 set_isa(c, MIPS_CPU_ISA_IV); 691 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 692 MIPS_CPU_LLSC; 693 /* 694 * Bit 29 in the info register of the RM9000 695 * indicates if the TLB has 48 or 64 entries. 696 * 697 * 29 1 => 64 entry JTLB 698 * 0 => 48 entry JTLB 699 */ 700 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 701 break; 702 case PRID_IMP_R8000: 703 c->cputype = CPU_R8000; 704 __cpu_name[cpu] = "RM8000"; 705 set_isa(c, MIPS_CPU_ISA_IV); 706 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 707 MIPS_CPU_FPU | MIPS_CPU_32FPR | 708 MIPS_CPU_LLSC; 709 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 710 break; 711 case PRID_IMP_R10000: 712 c->cputype = CPU_R10000; 713 __cpu_name[cpu] = "R10000"; 714 set_isa(c, MIPS_CPU_ISA_IV); 715 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 716 MIPS_CPU_FPU | MIPS_CPU_32FPR | 717 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 718 MIPS_CPU_LLSC; 719 c->tlbsize = 64; 720 break; 721 case PRID_IMP_R12000: 722 c->cputype = CPU_R12000; 723 __cpu_name[cpu] = "R12000"; 724 set_isa(c, MIPS_CPU_ISA_IV); 725 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 726 MIPS_CPU_FPU | MIPS_CPU_32FPR | 727 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 728 MIPS_CPU_LLSC; 729 c->tlbsize = 64; 730 break; 731 case PRID_IMP_R14000: 732 c->cputype = CPU_R14000; 733 __cpu_name[cpu] = "R14000"; 734 set_isa(c, MIPS_CPU_ISA_IV); 735 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 736 MIPS_CPU_FPU | MIPS_CPU_32FPR | 737 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 738 MIPS_CPU_LLSC; 739 c->tlbsize = 64; 740 break; 741 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 742 switch (c->processor_id & PRID_REV_MASK) { 743 case PRID_REV_LOONGSON2E: 744 c->cputype = CPU_LOONGSON2; 745 __cpu_name[cpu] = "ICT Loongson-2"; 746 set_elf_platform(cpu, "loongson2e"); 747 break; 748 case PRID_REV_LOONGSON2F: 749 c->cputype = CPU_LOONGSON2; 750 __cpu_name[cpu] = "ICT Loongson-2"; 751 set_elf_platform(cpu, "loongson2f"); 752 break; 753 case PRID_REV_LOONGSON3A: 754 c->cputype = CPU_LOONGSON3; 755 __cpu_name[cpu] = "ICT Loongson-3"; 756 set_elf_platform(cpu, "loongson3a"); 757 break; 758 } 759 760 set_isa(c, MIPS_CPU_ISA_III); 761 c->options = R4K_OPTS | 762 MIPS_CPU_FPU | MIPS_CPU_LLSC | 763 MIPS_CPU_32FPR; 764 c->tlbsize = 64; 765 break; 766 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 767 decode_configs(c); 768 769 c->cputype = CPU_LOONGSON1; 770 771 switch (c->processor_id & PRID_REV_MASK) { 772 case PRID_REV_LOONGSON1B: 773 __cpu_name[cpu] = "Loongson 1B"; 774 break; 775 } 776 777 break; 778 } 779 } 780 781 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 782 { 783 switch (c->processor_id & PRID_IMP_MASK) { 784 case PRID_IMP_4KC: 785 c->cputype = CPU_4KC; 786 __cpu_name[cpu] = "MIPS 4Kc"; 787 break; 788 case PRID_IMP_4KEC: 789 case PRID_IMP_4KECR2: 790 c->cputype = CPU_4KEC; 791 __cpu_name[cpu] = "MIPS 4KEc"; 792 break; 793 case PRID_IMP_4KSC: 794 case PRID_IMP_4KSD: 795 c->cputype = CPU_4KSC; 796 __cpu_name[cpu] = "MIPS 4KSc"; 797 break; 798 case PRID_IMP_5KC: 799 c->cputype = CPU_5KC; 800 __cpu_name[cpu] = "MIPS 5Kc"; 801 break; 802 case PRID_IMP_5KE: 803 c->cputype = CPU_5KE; 804 __cpu_name[cpu] = "MIPS 5KE"; 805 break; 806 case PRID_IMP_20KC: 807 c->cputype = CPU_20KC; 808 __cpu_name[cpu] = "MIPS 20Kc"; 809 break; 810 case PRID_IMP_24K: 811 c->cputype = CPU_24K; 812 __cpu_name[cpu] = "MIPS 24Kc"; 813 break; 814 case PRID_IMP_24KE: 815 c->cputype = CPU_24K; 816 __cpu_name[cpu] = "MIPS 24KEc"; 817 break; 818 case PRID_IMP_25KF: 819 c->cputype = CPU_25KF; 820 __cpu_name[cpu] = "MIPS 25Kc"; 821 break; 822 case PRID_IMP_34K: 823 c->cputype = CPU_34K; 824 __cpu_name[cpu] = "MIPS 34Kc"; 825 break; 826 case PRID_IMP_74K: 827 c->cputype = CPU_74K; 828 __cpu_name[cpu] = "MIPS 74Kc"; 829 break; 830 case PRID_IMP_M14KC: 831 c->cputype = CPU_M14KC; 832 __cpu_name[cpu] = "MIPS M14Kc"; 833 break; 834 case PRID_IMP_M14KEC: 835 c->cputype = CPU_M14KEC; 836 __cpu_name[cpu] = "MIPS M14KEc"; 837 break; 838 case PRID_IMP_1004K: 839 c->cputype = CPU_1004K; 840 __cpu_name[cpu] = "MIPS 1004Kc"; 841 break; 842 case PRID_IMP_1074K: 843 c->cputype = CPU_1074K; 844 __cpu_name[cpu] = "MIPS 1074Kc"; 845 break; 846 case PRID_IMP_INTERAPTIV_UP: 847 c->cputype = CPU_INTERAPTIV; 848 __cpu_name[cpu] = "MIPS interAptiv"; 849 break; 850 case PRID_IMP_INTERAPTIV_MP: 851 c->cputype = CPU_INTERAPTIV; 852 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 853 break; 854 case PRID_IMP_PROAPTIV_UP: 855 c->cputype = CPU_PROAPTIV; 856 __cpu_name[cpu] = "MIPS proAptiv"; 857 break; 858 case PRID_IMP_PROAPTIV_MP: 859 c->cputype = CPU_PROAPTIV; 860 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 861 break; 862 case PRID_IMP_P5600: 863 c->cputype = CPU_P5600; 864 __cpu_name[cpu] = "MIPS P5600"; 865 break; 866 case PRID_IMP_M5150: 867 c->cputype = CPU_M5150; 868 __cpu_name[cpu] = "MIPS M5150"; 869 break; 870 } 871 872 decode_configs(c); 873 874 spram_config(); 875 } 876 877 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 878 { 879 decode_configs(c); 880 switch (c->processor_id & PRID_IMP_MASK) { 881 case PRID_IMP_AU1_REV1: 882 case PRID_IMP_AU1_REV2: 883 c->cputype = CPU_ALCHEMY; 884 switch ((c->processor_id >> 24) & 0xff) { 885 case 0: 886 __cpu_name[cpu] = "Au1000"; 887 break; 888 case 1: 889 __cpu_name[cpu] = "Au1500"; 890 break; 891 case 2: 892 __cpu_name[cpu] = "Au1100"; 893 break; 894 case 3: 895 __cpu_name[cpu] = "Au1550"; 896 break; 897 case 4: 898 __cpu_name[cpu] = "Au1200"; 899 if ((c->processor_id & PRID_REV_MASK) == 2) 900 __cpu_name[cpu] = "Au1250"; 901 break; 902 case 5: 903 __cpu_name[cpu] = "Au1210"; 904 break; 905 default: 906 __cpu_name[cpu] = "Au1xxx"; 907 break; 908 } 909 break; 910 } 911 } 912 913 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 914 { 915 decode_configs(c); 916 917 switch (c->processor_id & PRID_IMP_MASK) { 918 case PRID_IMP_SB1: 919 c->cputype = CPU_SB1; 920 __cpu_name[cpu] = "SiByte SB1"; 921 /* FPU in pass1 is known to have issues. */ 922 if ((c->processor_id & PRID_REV_MASK) < 0x02) 923 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 924 break; 925 case PRID_IMP_SB1A: 926 c->cputype = CPU_SB1A; 927 __cpu_name[cpu] = "SiByte SB1A"; 928 break; 929 } 930 } 931 932 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 933 { 934 decode_configs(c); 935 switch (c->processor_id & PRID_IMP_MASK) { 936 case PRID_IMP_SR71000: 937 c->cputype = CPU_SR71000; 938 __cpu_name[cpu] = "Sandcraft SR71000"; 939 c->scache.ways = 8; 940 c->tlbsize = 64; 941 break; 942 } 943 } 944 945 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 946 { 947 decode_configs(c); 948 switch (c->processor_id & PRID_IMP_MASK) { 949 case PRID_IMP_PR4450: 950 c->cputype = CPU_PR4450; 951 __cpu_name[cpu] = "Philips PR4450"; 952 set_isa(c, MIPS_CPU_ISA_M32R1); 953 break; 954 } 955 } 956 957 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 958 { 959 decode_configs(c); 960 switch (c->processor_id & PRID_IMP_MASK) { 961 case PRID_IMP_BMIPS32_REV4: 962 case PRID_IMP_BMIPS32_REV8: 963 c->cputype = CPU_BMIPS32; 964 __cpu_name[cpu] = "Broadcom BMIPS32"; 965 set_elf_platform(cpu, "bmips32"); 966 break; 967 case PRID_IMP_BMIPS3300: 968 case PRID_IMP_BMIPS3300_ALT: 969 case PRID_IMP_BMIPS3300_BUG: 970 c->cputype = CPU_BMIPS3300; 971 __cpu_name[cpu] = "Broadcom BMIPS3300"; 972 set_elf_platform(cpu, "bmips3300"); 973 break; 974 case PRID_IMP_BMIPS43XX: { 975 int rev = c->processor_id & PRID_REV_MASK; 976 977 if (rev >= PRID_REV_BMIPS4380_LO && 978 rev <= PRID_REV_BMIPS4380_HI) { 979 c->cputype = CPU_BMIPS4380; 980 __cpu_name[cpu] = "Broadcom BMIPS4380"; 981 set_elf_platform(cpu, "bmips4380"); 982 } else { 983 c->cputype = CPU_BMIPS4350; 984 __cpu_name[cpu] = "Broadcom BMIPS4350"; 985 set_elf_platform(cpu, "bmips4350"); 986 } 987 break; 988 } 989 case PRID_IMP_BMIPS5000: 990 c->cputype = CPU_BMIPS5000; 991 __cpu_name[cpu] = "Broadcom BMIPS5000"; 992 set_elf_platform(cpu, "bmips5000"); 993 c->options |= MIPS_CPU_ULRI; 994 break; 995 } 996 } 997 998 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 999 { 1000 decode_configs(c); 1001 switch (c->processor_id & PRID_IMP_MASK) { 1002 case PRID_IMP_CAVIUM_CN38XX: 1003 case PRID_IMP_CAVIUM_CN31XX: 1004 case PRID_IMP_CAVIUM_CN30XX: 1005 c->cputype = CPU_CAVIUM_OCTEON; 1006 __cpu_name[cpu] = "Cavium Octeon"; 1007 goto platform; 1008 case PRID_IMP_CAVIUM_CN58XX: 1009 case PRID_IMP_CAVIUM_CN56XX: 1010 case PRID_IMP_CAVIUM_CN50XX: 1011 case PRID_IMP_CAVIUM_CN52XX: 1012 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1013 __cpu_name[cpu] = "Cavium Octeon+"; 1014 platform: 1015 set_elf_platform(cpu, "octeon"); 1016 break; 1017 case PRID_IMP_CAVIUM_CN61XX: 1018 case PRID_IMP_CAVIUM_CN63XX: 1019 case PRID_IMP_CAVIUM_CN66XX: 1020 case PRID_IMP_CAVIUM_CN68XX: 1021 case PRID_IMP_CAVIUM_CNF71XX: 1022 c->cputype = CPU_CAVIUM_OCTEON2; 1023 __cpu_name[cpu] = "Cavium Octeon II"; 1024 set_elf_platform(cpu, "octeon2"); 1025 break; 1026 case PRID_IMP_CAVIUM_CN70XX: 1027 case PRID_IMP_CAVIUM_CN78XX: 1028 c->cputype = CPU_CAVIUM_OCTEON3; 1029 __cpu_name[cpu] = "Cavium Octeon III"; 1030 set_elf_platform(cpu, "octeon3"); 1031 break; 1032 default: 1033 printk(KERN_INFO "Unknown Octeon chip!\n"); 1034 c->cputype = CPU_UNKNOWN; 1035 break; 1036 } 1037 } 1038 1039 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1040 { 1041 decode_configs(c); 1042 /* JZRISC does not implement the CP0 counter. */ 1043 c->options &= ~MIPS_CPU_COUNTER; 1044 switch (c->processor_id & PRID_IMP_MASK) { 1045 case PRID_IMP_JZRISC: 1046 c->cputype = CPU_JZRISC; 1047 __cpu_name[cpu] = "Ingenic JZRISC"; 1048 break; 1049 default: 1050 panic("Unknown Ingenic Processor ID!"); 1051 break; 1052 } 1053 } 1054 1055 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1056 { 1057 decode_configs(c); 1058 1059 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1060 c->cputype = CPU_ALCHEMY; 1061 __cpu_name[cpu] = "Au1300"; 1062 /* following stuff is not for Alchemy */ 1063 return; 1064 } 1065 1066 c->options = (MIPS_CPU_TLB | 1067 MIPS_CPU_4KEX | 1068 MIPS_CPU_COUNTER | 1069 MIPS_CPU_DIVEC | 1070 MIPS_CPU_WATCH | 1071 MIPS_CPU_EJTAG | 1072 MIPS_CPU_LLSC); 1073 1074 switch (c->processor_id & PRID_IMP_MASK) { 1075 case PRID_IMP_NETLOGIC_XLP2XX: 1076 case PRID_IMP_NETLOGIC_XLP9XX: 1077 c->cputype = CPU_XLP; 1078 __cpu_name[cpu] = "Broadcom XLPII"; 1079 break; 1080 1081 case PRID_IMP_NETLOGIC_XLP8XX: 1082 case PRID_IMP_NETLOGIC_XLP3XX: 1083 c->cputype = CPU_XLP; 1084 __cpu_name[cpu] = "Netlogic XLP"; 1085 break; 1086 1087 case PRID_IMP_NETLOGIC_XLR732: 1088 case PRID_IMP_NETLOGIC_XLR716: 1089 case PRID_IMP_NETLOGIC_XLR532: 1090 case PRID_IMP_NETLOGIC_XLR308: 1091 case PRID_IMP_NETLOGIC_XLR532C: 1092 case PRID_IMP_NETLOGIC_XLR516C: 1093 case PRID_IMP_NETLOGIC_XLR508C: 1094 case PRID_IMP_NETLOGIC_XLR308C: 1095 c->cputype = CPU_XLR; 1096 __cpu_name[cpu] = "Netlogic XLR"; 1097 break; 1098 1099 case PRID_IMP_NETLOGIC_XLS608: 1100 case PRID_IMP_NETLOGIC_XLS408: 1101 case PRID_IMP_NETLOGIC_XLS404: 1102 case PRID_IMP_NETLOGIC_XLS208: 1103 case PRID_IMP_NETLOGIC_XLS204: 1104 case PRID_IMP_NETLOGIC_XLS108: 1105 case PRID_IMP_NETLOGIC_XLS104: 1106 case PRID_IMP_NETLOGIC_XLS616B: 1107 case PRID_IMP_NETLOGIC_XLS608B: 1108 case PRID_IMP_NETLOGIC_XLS416B: 1109 case PRID_IMP_NETLOGIC_XLS412B: 1110 case PRID_IMP_NETLOGIC_XLS408B: 1111 case PRID_IMP_NETLOGIC_XLS404B: 1112 c->cputype = CPU_XLR; 1113 __cpu_name[cpu] = "Netlogic XLS"; 1114 break; 1115 1116 default: 1117 pr_info("Unknown Netlogic chip id [%02x]!\n", 1118 c->processor_id); 1119 c->cputype = CPU_XLR; 1120 break; 1121 } 1122 1123 if (c->cputype == CPU_XLP) { 1124 set_isa(c, MIPS_CPU_ISA_M64R2); 1125 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1126 /* This will be updated again after all threads are woken up */ 1127 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1128 } else { 1129 set_isa(c, MIPS_CPU_ISA_M64R1); 1130 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1131 } 1132 c->kscratch_mask = 0xf; 1133 } 1134 1135 #ifdef CONFIG_64BIT 1136 /* For use by uaccess.h */ 1137 u64 __ua_limit; 1138 EXPORT_SYMBOL(__ua_limit); 1139 #endif 1140 1141 const char *__cpu_name[NR_CPUS]; 1142 const char *__elf_platform; 1143 1144 void cpu_probe(void) 1145 { 1146 struct cpuinfo_mips *c = ¤t_cpu_data; 1147 unsigned int cpu = smp_processor_id(); 1148 1149 c->processor_id = PRID_IMP_UNKNOWN; 1150 c->fpu_id = FPIR_IMP_NONE; 1151 c->cputype = CPU_UNKNOWN; 1152 1153 c->processor_id = read_c0_prid(); 1154 switch (c->processor_id & PRID_COMP_MASK) { 1155 case PRID_COMP_LEGACY: 1156 cpu_probe_legacy(c, cpu); 1157 break; 1158 case PRID_COMP_MIPS: 1159 cpu_probe_mips(c, cpu); 1160 break; 1161 case PRID_COMP_ALCHEMY: 1162 cpu_probe_alchemy(c, cpu); 1163 break; 1164 case PRID_COMP_SIBYTE: 1165 cpu_probe_sibyte(c, cpu); 1166 break; 1167 case PRID_COMP_BROADCOM: 1168 cpu_probe_broadcom(c, cpu); 1169 break; 1170 case PRID_COMP_SANDCRAFT: 1171 cpu_probe_sandcraft(c, cpu); 1172 break; 1173 case PRID_COMP_NXP: 1174 cpu_probe_nxp(c, cpu); 1175 break; 1176 case PRID_COMP_CAVIUM: 1177 cpu_probe_cavium(c, cpu); 1178 break; 1179 case PRID_COMP_INGENIC: 1180 cpu_probe_ingenic(c, cpu); 1181 break; 1182 case PRID_COMP_NETLOGIC: 1183 cpu_probe_netlogic(c, cpu); 1184 break; 1185 } 1186 1187 BUG_ON(!__cpu_name[cpu]); 1188 BUG_ON(c->cputype == CPU_UNKNOWN); 1189 1190 /* 1191 * Platform code can force the cpu type to optimize code 1192 * generation. In that case be sure the cpu type is correctly 1193 * manually setup otherwise it could trigger some nasty bugs. 1194 */ 1195 BUG_ON(current_cpu_type() != c->cputype); 1196 1197 if (mips_fpu_disabled) 1198 c->options &= ~MIPS_CPU_FPU; 1199 1200 if (mips_dsp_disabled) 1201 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1202 1203 if (c->options & MIPS_CPU_FPU) { 1204 c->fpu_id = cpu_get_fpu_id(); 1205 1206 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1207 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1208 if (c->fpu_id & MIPS_FPIR_3D) 1209 c->ases |= MIPS_ASE_MIPS3D; 1210 } 1211 } 1212 1213 if (cpu_has_mips_r2) { 1214 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1215 /* R2 has Performance Counter Interrupt indicator */ 1216 c->options |= MIPS_CPU_PCI; 1217 } 1218 else 1219 c->srsets = 1; 1220 1221 if (cpu_has_msa) { 1222 c->msa_id = cpu_get_msa_id(); 1223 WARN(c->msa_id & MSA_IR_WRPF, 1224 "Vector register partitioning unimplemented!"); 1225 } 1226 1227 cpu_probe_vmbits(c); 1228 1229 #ifdef CONFIG_64BIT 1230 if (cpu == 0) 1231 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1232 #endif 1233 } 1234 1235 void cpu_report(void) 1236 { 1237 struct cpuinfo_mips *c = ¤t_cpu_data; 1238 1239 pr_info("CPU%d revision is: %08x (%s)\n", 1240 smp_processor_id(), c->processor_id, cpu_name_string()); 1241 if (c->options & MIPS_CPU_FPU) 1242 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1243 if (cpu_has_msa) 1244 pr_info("MSA revision is: %08x\n", c->msa_id); 1245 } 1246