1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) xxxx the Anonymous 6 * Copyright (C) 1994 - 2006 Ralf Baechle 7 * Copyright (C) 2003, 2004 Maciej W. Rozycki 8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/ptrace.h> 13 #include <linux/smp.h> 14 #include <linux/stddef.h> 15 #include <linux/export.h> 16 17 #include <asm/bugs.h> 18 #include <asm/cpu.h> 19 #include <asm/cpu-features.h> 20 #include <asm/cpu-type.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/mipsmtregs.h> 24 #include <asm/msa.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/pgtable-bits.h> 28 #include <asm/spram.h> 29 #include <linux/uaccess.h> 30 31 /* Hardware capabilities */ 32 unsigned int elf_hwcap __read_mostly; 33 EXPORT_SYMBOL_GPL(elf_hwcap); 34 35 #ifdef CONFIG_MIPS_FP_SUPPORT 36 37 /* 38 * Get the FPU Implementation/Revision. 39 */ 40 static inline unsigned long cpu_get_fpu_id(void) 41 { 42 unsigned long tmp, fpu_id; 43 44 tmp = read_c0_status(); 45 __enable_fpu(FPU_AS_IS); 46 fpu_id = read_32bit_cp1_register(CP1_REVISION); 47 write_c0_status(tmp); 48 return fpu_id; 49 } 50 51 /* 52 * Check if the CPU has an external FPU. 53 */ 54 static inline int __cpu_has_fpu(void) 55 { 56 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 57 } 58 59 /* 60 * Determine the FCSR mask for FPU hardware. 61 */ 62 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 63 { 64 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 65 66 fcsr = c->fpu_csr31; 67 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 68 69 sr = read_c0_status(); 70 __enable_fpu(FPU_AS_IS); 71 72 fcsr0 = fcsr & mask; 73 write_32bit_cp1_register(CP1_STATUS, fcsr0); 74 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 75 76 fcsr1 = fcsr | ~mask; 77 write_32bit_cp1_register(CP1_STATUS, fcsr1); 78 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 79 80 write_32bit_cp1_register(CP1_STATUS, fcsr); 81 82 write_c0_status(sr); 83 84 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 85 } 86 87 /* 88 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 89 * supported by FPU hardware. 90 */ 91 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 92 { 93 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 94 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 95 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 96 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 97 98 sr = read_c0_status(); 99 __enable_fpu(FPU_AS_IS); 100 101 fir = read_32bit_cp1_register(CP1_REVISION); 102 if (fir & MIPS_FPIR_HAS2008) { 103 fcsr = read_32bit_cp1_register(CP1_STATUS); 104 105 /* 106 * MAC2008 toolchain never landed in real world, so we're only 107 * testing wether it can be disabled and don't try to enabled 108 * it. 109 */ 110 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | FPU_CSR_MAC2008); 111 write_32bit_cp1_register(CP1_STATUS, fcsr0); 112 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 113 114 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 115 write_32bit_cp1_register(CP1_STATUS, fcsr1); 116 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 117 118 write_32bit_cp1_register(CP1_STATUS, fcsr); 119 120 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2)) { 121 /* 122 * The bit for MAC2008 might be reused by R6 in future, 123 * so we only test for R2-R5. 124 */ 125 if (fcsr0 & FPU_CSR_MAC2008) 126 c->options |= MIPS_CPU_MAC_2008_ONLY; 127 } 128 129 if (!(fcsr0 & FPU_CSR_NAN2008)) 130 c->options |= MIPS_CPU_NAN_LEGACY; 131 if (fcsr1 & FPU_CSR_NAN2008) 132 c->options |= MIPS_CPU_NAN_2008; 133 134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 135 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 136 else 137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 138 139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 140 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 141 else 142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 143 } else { 144 c->options |= MIPS_CPU_NAN_LEGACY; 145 } 146 147 write_c0_status(sr); 148 } else { 149 c->options |= MIPS_CPU_NAN_LEGACY; 150 } 151 } 152 153 /* 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 155 * ABS.fmt/NEG.fmt execution mode. 156 */ 157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 158 159 /* 160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 161 * to support by the FPU emulator according to the IEEE 754 conformance 162 * mode selected. Note that "relaxed" straps the emulator so that it 163 * allows 2008-NaN binaries even for legacy processors. 164 */ 165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 166 { 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 171 switch (ieee754) { 172 case STRICT: 173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 177 } else { 178 c->options |= MIPS_CPU_NAN_LEGACY; 179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 180 } 181 break; 182 case LEGACY: 183 c->options |= MIPS_CPU_NAN_LEGACY; 184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 185 break; 186 case STD2008: 187 c->options |= MIPS_CPU_NAN_2008; 188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 break; 191 case RELAXED: 192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 193 break; 194 } 195 } 196 197 /* 198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 199 * according to the "ieee754=" parameter. 200 */ 201 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 202 { 203 switch (ieee754) { 204 case STRICT: 205 mips_use_nan_legacy = !!cpu_has_nan_legacy; 206 mips_use_nan_2008 = !!cpu_has_nan_2008; 207 break; 208 case LEGACY: 209 mips_use_nan_legacy = !!cpu_has_nan_legacy; 210 mips_use_nan_2008 = !cpu_has_nan_legacy; 211 break; 212 case STD2008: 213 mips_use_nan_legacy = !cpu_has_nan_2008; 214 mips_use_nan_2008 = !!cpu_has_nan_2008; 215 break; 216 case RELAXED: 217 mips_use_nan_legacy = true; 218 mips_use_nan_2008 = true; 219 break; 220 } 221 } 222 223 /* 224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 225 * settings: 226 * 227 * strict: accept binaries that request a NaN encoding supported by the FPU 228 * legacy: only accept legacy-NaN binaries 229 * 2008: only accept 2008-NaN binaries 230 * relaxed: accept any binaries regardless of whether supported by the FPU 231 */ 232 static int __init ieee754_setup(char *s) 233 { 234 if (!s) 235 return -1; 236 else if (!strcmp(s, "strict")) 237 ieee754 = STRICT; 238 else if (!strcmp(s, "legacy")) 239 ieee754 = LEGACY; 240 else if (!strcmp(s, "2008")) 241 ieee754 = STD2008; 242 else if (!strcmp(s, "relaxed")) 243 ieee754 = RELAXED; 244 else 245 return -1; 246 247 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 248 cpu_set_nofpu_2008(&boot_cpu_data); 249 cpu_set_nan_2008(&boot_cpu_data); 250 251 return 0; 252 } 253 254 early_param("ieee754", ieee754_setup); 255 256 /* 257 * Set the FIR feature flags for the FPU emulator. 258 */ 259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 260 { 261 u32 value; 262 263 value = 0; 264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 267 value |= MIPS_FPIR_D | MIPS_FPIR_S; 268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 271 if (c->options & MIPS_CPU_NAN_2008) 272 value |= MIPS_FPIR_HAS2008; 273 c->fpu_id = value; 274 } 275 276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 277 static unsigned int mips_nofpu_msk31; 278 279 /* 280 * Set options for FPU hardware. 281 */ 282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 283 { 284 c->fpu_id = cpu_get_fpu_id(); 285 mips_nofpu_msk31 = c->fpu_msk31; 286 287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 290 if (c->fpu_id & MIPS_FPIR_3D) 291 c->ases |= MIPS_ASE_MIPS3D; 292 if (c->fpu_id & MIPS_FPIR_UFRP) 293 c->options |= MIPS_CPU_UFR; 294 if (c->fpu_id & MIPS_FPIR_FREP) 295 c->options |= MIPS_CPU_FRE; 296 } 297 298 cpu_set_fpu_fcsr_mask(c); 299 cpu_set_fpu_2008(c); 300 cpu_set_nan_2008(c); 301 } 302 303 /* 304 * Set options for the FPU emulator. 305 */ 306 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 307 { 308 c->options &= ~MIPS_CPU_FPU; 309 c->fpu_msk31 = mips_nofpu_msk31; 310 311 cpu_set_nofpu_2008(c); 312 cpu_set_nan_2008(c); 313 cpu_set_nofpu_id(c); 314 } 315 316 static int mips_fpu_disabled; 317 318 static int __init fpu_disable(char *s) 319 { 320 cpu_set_nofpu_opts(&boot_cpu_data); 321 mips_fpu_disabled = 1; 322 323 return 1; 324 } 325 326 __setup("nofpu", fpu_disable); 327 328 #else /* !CONFIG_MIPS_FP_SUPPORT */ 329 330 #define mips_fpu_disabled 1 331 332 static inline unsigned long cpu_get_fpu_id(void) 333 { 334 return FPIR_IMP_NONE; 335 } 336 337 static inline int __cpu_has_fpu(void) 338 { 339 return 0; 340 } 341 342 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 343 { 344 /* no-op */ 345 } 346 347 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 348 { 349 /* no-op */ 350 } 351 352 #endif /* CONFIG_MIPS_FP_SUPPORT */ 353 354 static inline unsigned long cpu_get_msa_id(void) 355 { 356 unsigned long status, msa_id; 357 358 status = read_c0_status(); 359 __enable_fpu(FPU_64BIT); 360 enable_msa(); 361 msa_id = read_msa_ir(); 362 disable_msa(); 363 write_c0_status(status); 364 return msa_id; 365 } 366 367 static int mips_dsp_disabled; 368 369 static int __init dsp_disable(char *s) 370 { 371 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 372 mips_dsp_disabled = 1; 373 374 return 1; 375 } 376 377 __setup("nodsp", dsp_disable); 378 379 static int mips_htw_disabled; 380 381 static int __init htw_disable(char *s) 382 { 383 mips_htw_disabled = 1; 384 cpu_data[0].options &= ~MIPS_CPU_HTW; 385 write_c0_pwctl(read_c0_pwctl() & 386 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 387 388 return 1; 389 } 390 391 __setup("nohtw", htw_disable); 392 393 static int mips_ftlb_disabled; 394 static int mips_has_ftlb_configured; 395 396 enum ftlb_flags { 397 FTLB_EN = 1 << 0, 398 FTLB_SET_PROB = 1 << 1, 399 }; 400 401 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 402 403 static int __init ftlb_disable(char *s) 404 { 405 unsigned int config4, mmuextdef; 406 407 /* 408 * If the core hasn't done any FTLB configuration, there is nothing 409 * for us to do here. 410 */ 411 if (!mips_has_ftlb_configured) 412 return 1; 413 414 /* Disable it in the boot cpu */ 415 if (set_ftlb_enable(&cpu_data[0], 0)) { 416 pr_warn("Can't turn FTLB off\n"); 417 return 1; 418 } 419 420 config4 = read_c0_config4(); 421 422 /* Check that FTLB has been disabled */ 423 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 424 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 425 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 426 /* This should never happen */ 427 pr_warn("FTLB could not be disabled!\n"); 428 return 1; 429 } 430 431 mips_ftlb_disabled = 1; 432 mips_has_ftlb_configured = 0; 433 434 /* 435 * noftlb is mainly used for debug purposes so print 436 * an informative message instead of using pr_debug() 437 */ 438 pr_info("FTLB has been disabled\n"); 439 440 /* 441 * Some of these bits are duplicated in the decode_config4. 442 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 443 * once FTLB has been disabled so undo what decode_config4 did. 444 */ 445 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 446 cpu_data[0].tlbsizeftlbsets; 447 cpu_data[0].tlbsizeftlbsets = 0; 448 cpu_data[0].tlbsizeftlbways = 0; 449 450 return 1; 451 } 452 453 __setup("noftlb", ftlb_disable); 454 455 /* 456 * Check if the CPU has per tc perf counters 457 */ 458 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) 459 { 460 if (read_c0_config7() & MTI_CONF7_PTC) 461 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; 462 } 463 464 static inline void check_errata(void) 465 { 466 struct cpuinfo_mips *c = ¤t_cpu_data; 467 468 switch (current_cpu_type()) { 469 case CPU_34K: 470 /* 471 * Erratum "RPS May Cause Incorrect Instruction Execution" 472 * This code only handles VPE0, any SMP/RTOS code 473 * making use of VPE1 will be responsable for that VPE. 474 */ 475 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 476 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 477 break; 478 default: 479 break; 480 } 481 } 482 483 void __init check_bugs32(void) 484 { 485 check_errata(); 486 } 487 488 /* 489 * Probe whether cpu has config register by trying to play with 490 * alternate cache bit and see whether it matters. 491 * It's used by cpu_probe to distinguish between R3000A and R3081. 492 */ 493 static inline int cpu_has_confreg(void) 494 { 495 #ifdef CONFIG_CPU_R3000 496 extern unsigned long r3k_cache_size(unsigned long); 497 unsigned long size1, size2; 498 unsigned long cfg = read_c0_conf(); 499 500 size1 = r3k_cache_size(ST0_ISC); 501 write_c0_conf(cfg ^ R30XX_CONF_AC); 502 size2 = r3k_cache_size(ST0_ISC); 503 write_c0_conf(cfg); 504 return size1 != size2; 505 #else 506 return 0; 507 #endif 508 } 509 510 static inline void set_elf_platform(int cpu, const char *plat) 511 { 512 if (cpu == 0) 513 __elf_platform = plat; 514 } 515 516 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 517 { 518 #ifdef __NEED_VMBITS_PROBE 519 write_c0_entryhi(0x3fffffffffffe000ULL); 520 back_to_back_c0_hazard(); 521 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 522 #endif 523 } 524 525 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 526 { 527 switch (isa) { 528 case MIPS_CPU_ISA_M64R2: 529 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 530 /* fall through */ 531 case MIPS_CPU_ISA_M64R1: 532 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 533 /* fall through */ 534 case MIPS_CPU_ISA_V: 535 c->isa_level |= MIPS_CPU_ISA_V; 536 /* fall through */ 537 case MIPS_CPU_ISA_IV: 538 c->isa_level |= MIPS_CPU_ISA_IV; 539 /* fall through */ 540 case MIPS_CPU_ISA_III: 541 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 542 break; 543 544 /* R6 incompatible with everything else */ 545 case MIPS_CPU_ISA_M64R6: 546 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 547 /* fall through */ 548 case MIPS_CPU_ISA_M32R6: 549 c->isa_level |= MIPS_CPU_ISA_M32R6; 550 /* Break here so we don't add incompatible ISAs */ 551 break; 552 case MIPS_CPU_ISA_M32R2: 553 c->isa_level |= MIPS_CPU_ISA_M32R2; 554 /* fall through */ 555 case MIPS_CPU_ISA_M32R1: 556 c->isa_level |= MIPS_CPU_ISA_M32R1; 557 /* fall through */ 558 case MIPS_CPU_ISA_II: 559 c->isa_level |= MIPS_CPU_ISA_II; 560 break; 561 } 562 } 563 564 static char unknown_isa[] = KERN_ERR \ 565 "Unsupported ISA type, c0.config0: %d."; 566 567 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 568 { 569 570 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 571 572 /* 573 * 0 = All TLBWR instructions go to FTLB 574 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 575 * FTLB and 1 goes to the VTLB. 576 * 2 = 7:1: As above with 7:1 ratio. 577 * 3 = 3:1: As above with 3:1 ratio. 578 * 579 * Use the linear midpoint as the probability threshold. 580 */ 581 if (probability >= 12) 582 return 1; 583 else if (probability >= 6) 584 return 2; 585 else 586 /* 587 * So FTLB is less than 4 times bigger than VTLB. 588 * A 3:1 ratio can still be useful though. 589 */ 590 return 3; 591 } 592 593 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 594 { 595 unsigned int config; 596 597 /* It's implementation dependent how the FTLB can be enabled */ 598 switch (c->cputype) { 599 case CPU_PROAPTIV: 600 case CPU_P5600: 601 case CPU_P6600: 602 /* proAptiv & related cores use Config6 to enable the FTLB */ 603 config = read_c0_config6(); 604 605 if (flags & FTLB_EN) 606 config |= MIPS_CONF6_FTLBEN; 607 else 608 config &= ~MIPS_CONF6_FTLBEN; 609 610 if (flags & FTLB_SET_PROB) { 611 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 612 config |= calculate_ftlb_probability(c) 613 << MIPS_CONF6_FTLBP_SHIFT; 614 } 615 616 write_c0_config6(config); 617 back_to_back_c0_hazard(); 618 break; 619 case CPU_I6400: 620 case CPU_I6500: 621 /* There's no way to disable the FTLB */ 622 if (!(flags & FTLB_EN)) 623 return 1; 624 return 0; 625 case CPU_LOONGSON64: 626 /* Flush ITLB, DTLB, VTLB and FTLB */ 627 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 628 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 629 /* Loongson-3 cores use Config6 to enable the FTLB */ 630 config = read_c0_config6(); 631 if (flags & FTLB_EN) 632 /* Enable FTLB */ 633 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); 634 else 635 /* Disable FTLB */ 636 write_c0_config6(config | MIPS_CONF6_FTLBDIS); 637 break; 638 default: 639 return 1; 640 } 641 642 return 0; 643 } 644 645 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 646 { 647 unsigned int config0; 648 int isa, mt; 649 650 config0 = read_c0_config(); 651 652 /* 653 * Look for Standard TLB or Dual VTLB and FTLB 654 */ 655 mt = config0 & MIPS_CONF_MT; 656 if (mt == MIPS_CONF_MT_TLB) 657 c->options |= MIPS_CPU_TLB; 658 else if (mt == MIPS_CONF_MT_FTLB) 659 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 660 661 isa = (config0 & MIPS_CONF_AT) >> 13; 662 switch (isa) { 663 case 0: 664 switch ((config0 & MIPS_CONF_AR) >> 10) { 665 case 0: 666 set_isa(c, MIPS_CPU_ISA_M32R1); 667 break; 668 case 1: 669 set_isa(c, MIPS_CPU_ISA_M32R2); 670 break; 671 case 2: 672 set_isa(c, MIPS_CPU_ISA_M32R6); 673 break; 674 default: 675 goto unknown; 676 } 677 break; 678 case 2: 679 switch ((config0 & MIPS_CONF_AR) >> 10) { 680 case 0: 681 set_isa(c, MIPS_CPU_ISA_M64R1); 682 break; 683 case 1: 684 set_isa(c, MIPS_CPU_ISA_M64R2); 685 break; 686 case 2: 687 set_isa(c, MIPS_CPU_ISA_M64R6); 688 break; 689 default: 690 goto unknown; 691 } 692 break; 693 default: 694 goto unknown; 695 } 696 697 return config0 & MIPS_CONF_M; 698 699 unknown: 700 panic(unknown_isa, config0); 701 } 702 703 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 704 { 705 unsigned int config1; 706 707 config1 = read_c0_config1(); 708 709 if (config1 & MIPS_CONF1_MD) 710 c->ases |= MIPS_ASE_MDMX; 711 if (config1 & MIPS_CONF1_PC) 712 c->options |= MIPS_CPU_PERF; 713 if (config1 & MIPS_CONF1_WR) 714 c->options |= MIPS_CPU_WATCH; 715 if (config1 & MIPS_CONF1_CA) 716 c->ases |= MIPS_ASE_MIPS16; 717 if (config1 & MIPS_CONF1_EP) 718 c->options |= MIPS_CPU_EJTAG; 719 if (config1 & MIPS_CONF1_FP) { 720 c->options |= MIPS_CPU_FPU; 721 c->options |= MIPS_CPU_32FPR; 722 } 723 if (cpu_has_tlb) { 724 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 725 c->tlbsizevtlb = c->tlbsize; 726 c->tlbsizeftlbsets = 0; 727 } 728 729 return config1 & MIPS_CONF_M; 730 } 731 732 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 733 { 734 unsigned int config2; 735 736 config2 = read_c0_config2(); 737 738 if (config2 & MIPS_CONF2_SL) 739 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 740 741 return config2 & MIPS_CONF_M; 742 } 743 744 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 745 { 746 unsigned int config3; 747 748 config3 = read_c0_config3(); 749 750 if (config3 & MIPS_CONF3_SM) { 751 c->ases |= MIPS_ASE_SMARTMIPS; 752 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 753 } 754 if (config3 & MIPS_CONF3_RXI) 755 c->options |= MIPS_CPU_RIXI; 756 if (config3 & MIPS_CONF3_CTXTC) 757 c->options |= MIPS_CPU_CTXTC; 758 if (config3 & MIPS_CONF3_DSP) 759 c->ases |= MIPS_ASE_DSP; 760 if (config3 & MIPS_CONF3_DSP2P) { 761 c->ases |= MIPS_ASE_DSP2P; 762 if (cpu_has_mips_r6) 763 c->ases |= MIPS_ASE_DSP3; 764 } 765 if (config3 & MIPS_CONF3_VINT) 766 c->options |= MIPS_CPU_VINT; 767 if (config3 & MIPS_CONF3_VEIC) 768 c->options |= MIPS_CPU_VEIC; 769 if (config3 & MIPS_CONF3_LPA) 770 c->options |= MIPS_CPU_LPA; 771 if (config3 & MIPS_CONF3_MT) 772 c->ases |= MIPS_ASE_MIPSMT; 773 if (config3 & MIPS_CONF3_ULRI) 774 c->options |= MIPS_CPU_ULRI; 775 if (config3 & MIPS_CONF3_ISA) 776 c->options |= MIPS_CPU_MICROMIPS; 777 if (config3 & MIPS_CONF3_VZ) 778 c->ases |= MIPS_ASE_VZ; 779 if (config3 & MIPS_CONF3_SC) 780 c->options |= MIPS_CPU_SEGMENTS; 781 if (config3 & MIPS_CONF3_BI) 782 c->options |= MIPS_CPU_BADINSTR; 783 if (config3 & MIPS_CONF3_BP) 784 c->options |= MIPS_CPU_BADINSTRP; 785 if (config3 & MIPS_CONF3_MSA) 786 c->ases |= MIPS_ASE_MSA; 787 if (config3 & MIPS_CONF3_PW) { 788 c->htw_seq = 0; 789 c->options |= MIPS_CPU_HTW; 790 } 791 if (config3 & MIPS_CONF3_CDMM) 792 c->options |= MIPS_CPU_CDMM; 793 if (config3 & MIPS_CONF3_SP) 794 c->options |= MIPS_CPU_SP; 795 796 return config3 & MIPS_CONF_M; 797 } 798 799 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 800 { 801 unsigned int config4; 802 unsigned int newcf4; 803 unsigned int mmuextdef; 804 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 805 unsigned long asid_mask; 806 807 config4 = read_c0_config4(); 808 809 if (cpu_has_tlb) { 810 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 811 c->options |= MIPS_CPU_TLBINV; 812 813 /* 814 * R6 has dropped the MMUExtDef field from config4. 815 * On R6 the fields always describe the FTLB, and only if it is 816 * present according to Config.MT. 817 */ 818 if (!cpu_has_mips_r6) 819 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 820 else if (cpu_has_ftlb) 821 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 822 else 823 mmuextdef = 0; 824 825 switch (mmuextdef) { 826 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 827 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 828 c->tlbsizevtlb = c->tlbsize; 829 break; 830 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 831 c->tlbsizevtlb += 832 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 833 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 834 c->tlbsize = c->tlbsizevtlb; 835 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 836 /* fall through */ 837 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 838 if (mips_ftlb_disabled) 839 break; 840 newcf4 = (config4 & ~ftlb_page) | 841 (page_size_ftlb(mmuextdef) << 842 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 843 write_c0_config4(newcf4); 844 back_to_back_c0_hazard(); 845 config4 = read_c0_config4(); 846 if (config4 != newcf4) { 847 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 848 PAGE_SIZE, config4); 849 /* Switch FTLB off */ 850 set_ftlb_enable(c, 0); 851 mips_ftlb_disabled = 1; 852 break; 853 } 854 c->tlbsizeftlbsets = 1 << 855 ((config4 & MIPS_CONF4_FTLBSETS) >> 856 MIPS_CONF4_FTLBSETS_SHIFT); 857 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 858 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 859 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 860 mips_has_ftlb_configured = 1; 861 break; 862 } 863 } 864 865 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 866 >> MIPS_CONF4_KSCREXIST_SHIFT; 867 868 asid_mask = MIPS_ENTRYHI_ASID; 869 if (config4 & MIPS_CONF4_AE) 870 asid_mask |= MIPS_ENTRYHI_ASIDX; 871 set_cpu_asid_mask(c, asid_mask); 872 873 /* 874 * Warn if the computed ASID mask doesn't match the mask the kernel 875 * is built for. This may indicate either a serious problem or an 876 * easy optimisation opportunity, but either way should be addressed. 877 */ 878 WARN_ON(asid_mask != cpu_asid_mask(c)); 879 880 return config4 & MIPS_CONF_M; 881 } 882 883 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 884 { 885 unsigned int config5, max_mmid_width; 886 unsigned long asid_mask; 887 888 config5 = read_c0_config5(); 889 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 890 891 if (cpu_has_mips_r6) { 892 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid) 893 config5 |= MIPS_CONF5_MI; 894 else 895 config5 &= ~MIPS_CONF5_MI; 896 } 897 898 write_c0_config5(config5); 899 900 if (config5 & MIPS_CONF5_EVA) 901 c->options |= MIPS_CPU_EVA; 902 if (config5 & MIPS_CONF5_MRP) 903 c->options |= MIPS_CPU_MAAR; 904 if (config5 & MIPS_CONF5_LLB) 905 c->options |= MIPS_CPU_RW_LLB; 906 if (config5 & MIPS_CONF5_MVH) 907 c->options |= MIPS_CPU_MVH; 908 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 909 c->options |= MIPS_CPU_VP; 910 if (config5 & MIPS_CONF5_CA2) 911 c->ases |= MIPS_ASE_MIPS16E2; 912 913 if (config5 & MIPS_CONF5_CRCP) 914 elf_hwcap |= HWCAP_MIPS_CRC32; 915 916 if (cpu_has_mips_r6) { 917 /* Ensure the write to config5 above takes effect */ 918 back_to_back_c0_hazard(); 919 920 /* Check whether we successfully enabled MMID support */ 921 config5 = read_c0_config5(); 922 if (config5 & MIPS_CONF5_MI) 923 c->options |= MIPS_CPU_MMID; 924 925 /* 926 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable 927 * for the CPU we're running on, or if CPUs in an SMP system 928 * have inconsistent MMID support. 929 */ 930 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); 931 932 if (cpu_has_mmid) { 933 write_c0_memorymapid(~0ul); 934 back_to_back_c0_hazard(); 935 asid_mask = read_c0_memorymapid(); 936 937 /* 938 * We maintain a bitmap to track MMID allocation, and 939 * need a sensible upper bound on the size of that 940 * bitmap. The initial CPU with MMID support (I6500) 941 * supports 16 bit MMIDs, which gives us an 8KiB 942 * bitmap. The architecture recommends that hardware 943 * support 32 bit MMIDs, which would give us a 512MiB 944 * bitmap - that's too big in most cases. 945 * 946 * Cap MMID width at 16 bits for now & we can revisit 947 * this if & when hardware supports anything wider. 948 */ 949 max_mmid_width = 16; 950 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { 951 pr_info("Capping MMID width at %d bits", 952 max_mmid_width); 953 asid_mask = GENMASK(max_mmid_width - 1, 0); 954 } 955 956 set_cpu_asid_mask(c, asid_mask); 957 } 958 } 959 960 return config5 & MIPS_CONF_M; 961 } 962 963 static void decode_configs(struct cpuinfo_mips *c) 964 { 965 int ok; 966 967 /* MIPS32 or MIPS64 compliant CPU. */ 968 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 969 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 970 971 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 972 973 /* Enable FTLB if present and not disabled */ 974 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 975 976 ok = decode_config0(c); /* Read Config registers. */ 977 BUG_ON(!ok); /* Arch spec violation! */ 978 if (ok) 979 ok = decode_config1(c); 980 if (ok) 981 ok = decode_config2(c); 982 if (ok) 983 ok = decode_config3(c); 984 if (ok) 985 ok = decode_config4(c); 986 if (ok) 987 ok = decode_config5(c); 988 989 /* Probe the EBase.WG bit */ 990 if (cpu_has_mips_r2_r6) { 991 u64 ebase; 992 unsigned int status; 993 994 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 995 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 996 : (s32)read_c0_ebase(); 997 if (ebase & MIPS_EBASE_WG) { 998 /* WG bit already set, we can avoid the clumsy probe */ 999 c->options |= MIPS_CPU_EBASE_WG; 1000 } else { 1001 /* Its UNDEFINED to change EBase while BEV=0 */ 1002 status = read_c0_status(); 1003 write_c0_status(status | ST0_BEV); 1004 irq_enable_hazard(); 1005 /* 1006 * On pre-r6 cores, this may well clobber the upper bits 1007 * of EBase. This is hard to avoid without potentially 1008 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 1009 */ 1010 if (cpu_has_mips64r6) 1011 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 1012 else 1013 write_c0_ebase(ebase | MIPS_EBASE_WG); 1014 back_to_back_c0_hazard(); 1015 /* Restore BEV */ 1016 write_c0_status(status); 1017 if (read_c0_ebase() & MIPS_EBASE_WG) { 1018 c->options |= MIPS_CPU_EBASE_WG; 1019 write_c0_ebase(ebase); 1020 } 1021 } 1022 } 1023 1024 /* configure the FTLB write probability */ 1025 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 1026 1027 mips_probe_watch_registers(c); 1028 1029 #ifndef CONFIG_MIPS_CPS 1030 if (cpu_has_mips_r2_r6) { 1031 unsigned int core; 1032 1033 core = get_ebase_cpunum(); 1034 if (cpu_has_mipsmt) 1035 core >>= fls(core_nvpes()) - 1; 1036 cpu_set_core(c, core); 1037 } 1038 #endif 1039 } 1040 1041 /* 1042 * Probe for certain guest capabilities by writing config bits and reading back. 1043 * Finally write back the original value. 1044 */ 1045 #define probe_gc0_config(name, maxconf, bits) \ 1046 do { \ 1047 unsigned int tmp; \ 1048 tmp = read_gc0_##name(); \ 1049 write_gc0_##name(tmp | (bits)); \ 1050 back_to_back_c0_hazard(); \ 1051 maxconf = read_gc0_##name(); \ 1052 write_gc0_##name(tmp); \ 1053 } while (0) 1054 1055 /* 1056 * Probe for dynamic guest capabilities by changing certain config bits and 1057 * reading back to see if they change. Finally write back the original value. 1058 */ 1059 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 1060 do { \ 1061 maxconf = read_gc0_##name(); \ 1062 write_gc0_##name(maxconf ^ (bits)); \ 1063 back_to_back_c0_hazard(); \ 1064 dynconf = maxconf ^ read_gc0_##name(); \ 1065 write_gc0_##name(maxconf); \ 1066 maxconf |= dynconf; \ 1067 } while (0) 1068 1069 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 1070 { 1071 unsigned int config0; 1072 1073 probe_gc0_config(config, config0, MIPS_CONF_M); 1074 1075 if (config0 & MIPS_CONF_M) 1076 c->guest.conf |= BIT(1); 1077 return config0 & MIPS_CONF_M; 1078 } 1079 1080 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 1081 { 1082 unsigned int config1, config1_dyn; 1083 1084 probe_gc0_config_dyn(config1, config1, config1_dyn, 1085 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 1086 MIPS_CONF1_FP); 1087 1088 if (config1 & MIPS_CONF1_FP) 1089 c->guest.options |= MIPS_CPU_FPU; 1090 if (config1_dyn & MIPS_CONF1_FP) 1091 c->guest.options_dyn |= MIPS_CPU_FPU; 1092 1093 if (config1 & MIPS_CONF1_WR) 1094 c->guest.options |= MIPS_CPU_WATCH; 1095 if (config1_dyn & MIPS_CONF1_WR) 1096 c->guest.options_dyn |= MIPS_CPU_WATCH; 1097 1098 if (config1 & MIPS_CONF1_PC) 1099 c->guest.options |= MIPS_CPU_PERF; 1100 if (config1_dyn & MIPS_CONF1_PC) 1101 c->guest.options_dyn |= MIPS_CPU_PERF; 1102 1103 if (config1 & MIPS_CONF_M) 1104 c->guest.conf |= BIT(2); 1105 return config1 & MIPS_CONF_M; 1106 } 1107 1108 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 1109 { 1110 unsigned int config2; 1111 1112 probe_gc0_config(config2, config2, MIPS_CONF_M); 1113 1114 if (config2 & MIPS_CONF_M) 1115 c->guest.conf |= BIT(3); 1116 return config2 & MIPS_CONF_M; 1117 } 1118 1119 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 1120 { 1121 unsigned int config3, config3_dyn; 1122 1123 probe_gc0_config_dyn(config3, config3, config3_dyn, 1124 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 1125 MIPS_CONF3_CTXTC); 1126 1127 if (config3 & MIPS_CONF3_CTXTC) 1128 c->guest.options |= MIPS_CPU_CTXTC; 1129 if (config3_dyn & MIPS_CONF3_CTXTC) 1130 c->guest.options_dyn |= MIPS_CPU_CTXTC; 1131 1132 if (config3 & MIPS_CONF3_PW) 1133 c->guest.options |= MIPS_CPU_HTW; 1134 1135 if (config3 & MIPS_CONF3_ULRI) 1136 c->guest.options |= MIPS_CPU_ULRI; 1137 1138 if (config3 & MIPS_CONF3_SC) 1139 c->guest.options |= MIPS_CPU_SEGMENTS; 1140 1141 if (config3 & MIPS_CONF3_BI) 1142 c->guest.options |= MIPS_CPU_BADINSTR; 1143 if (config3 & MIPS_CONF3_BP) 1144 c->guest.options |= MIPS_CPU_BADINSTRP; 1145 1146 if (config3 & MIPS_CONF3_MSA) 1147 c->guest.ases |= MIPS_ASE_MSA; 1148 if (config3_dyn & MIPS_CONF3_MSA) 1149 c->guest.ases_dyn |= MIPS_ASE_MSA; 1150 1151 if (config3 & MIPS_CONF_M) 1152 c->guest.conf |= BIT(4); 1153 return config3 & MIPS_CONF_M; 1154 } 1155 1156 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 1157 { 1158 unsigned int config4; 1159 1160 probe_gc0_config(config4, config4, 1161 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 1162 1163 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 1164 >> MIPS_CONF4_KSCREXIST_SHIFT; 1165 1166 if (config4 & MIPS_CONF_M) 1167 c->guest.conf |= BIT(5); 1168 return config4 & MIPS_CONF_M; 1169 } 1170 1171 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 1172 { 1173 unsigned int config5, config5_dyn; 1174 1175 probe_gc0_config_dyn(config5, config5, config5_dyn, 1176 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 1177 1178 if (config5 & MIPS_CONF5_MRP) 1179 c->guest.options |= MIPS_CPU_MAAR; 1180 if (config5_dyn & MIPS_CONF5_MRP) 1181 c->guest.options_dyn |= MIPS_CPU_MAAR; 1182 1183 if (config5 & MIPS_CONF5_LLB) 1184 c->guest.options |= MIPS_CPU_RW_LLB; 1185 1186 if (config5 & MIPS_CONF5_MVH) 1187 c->guest.options |= MIPS_CPU_MVH; 1188 1189 if (config5 & MIPS_CONF_M) 1190 c->guest.conf |= BIT(6); 1191 return config5 & MIPS_CONF_M; 1192 } 1193 1194 static inline void decode_guest_configs(struct cpuinfo_mips *c) 1195 { 1196 unsigned int ok; 1197 1198 ok = decode_guest_config0(c); 1199 if (ok) 1200 ok = decode_guest_config1(c); 1201 if (ok) 1202 ok = decode_guest_config2(c); 1203 if (ok) 1204 ok = decode_guest_config3(c); 1205 if (ok) 1206 ok = decode_guest_config4(c); 1207 if (ok) 1208 decode_guest_config5(c); 1209 } 1210 1211 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 1212 { 1213 unsigned int guestctl0, temp; 1214 1215 guestctl0 = read_c0_guestctl0(); 1216 1217 if (guestctl0 & MIPS_GCTL0_G0E) 1218 c->options |= MIPS_CPU_GUESTCTL0EXT; 1219 if (guestctl0 & MIPS_GCTL0_G1) 1220 c->options |= MIPS_CPU_GUESTCTL1; 1221 if (guestctl0 & MIPS_GCTL0_G2) 1222 c->options |= MIPS_CPU_GUESTCTL2; 1223 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 1224 c->options |= MIPS_CPU_GUESTID; 1225 1226 /* 1227 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 1228 * first, otherwise all data accesses will be fully virtualised 1229 * as if they were performed by guest mode. 1230 */ 1231 write_c0_guestctl1(0); 1232 tlbw_use_hazard(); 1233 1234 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 1235 back_to_back_c0_hazard(); 1236 temp = read_c0_guestctl0(); 1237 1238 if (temp & MIPS_GCTL0_DRG) { 1239 write_c0_guestctl0(guestctl0); 1240 c->options |= MIPS_CPU_DRG; 1241 } 1242 } 1243 } 1244 1245 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1246 { 1247 if (cpu_has_guestid) { 1248 /* determine the number of bits of GuestID available */ 1249 write_c0_guestctl1(MIPS_GCTL1_ID); 1250 back_to_back_c0_hazard(); 1251 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1252 >> MIPS_GCTL1_ID_SHIFT; 1253 write_c0_guestctl1(0); 1254 } 1255 } 1256 1257 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1258 { 1259 /* determine the number of bits of GTOffset available */ 1260 write_c0_gtoffset(0xffffffff); 1261 back_to_back_c0_hazard(); 1262 c->gtoffset_mask = read_c0_gtoffset(); 1263 write_c0_gtoffset(0); 1264 } 1265 1266 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1267 { 1268 cpu_probe_guestctl0(c); 1269 if (cpu_has_guestctl1) 1270 cpu_probe_guestctl1(c); 1271 1272 cpu_probe_gtoffset(c); 1273 1274 decode_guest_configs(c); 1275 } 1276 1277 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1278 | MIPS_CPU_COUNTER) 1279 1280 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1281 { 1282 switch (c->processor_id & PRID_IMP_MASK) { 1283 case PRID_IMP_R2000: 1284 c->cputype = CPU_R2000; 1285 __cpu_name[cpu] = "R2000"; 1286 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1287 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1288 MIPS_CPU_NOFPUEX; 1289 if (__cpu_has_fpu()) 1290 c->options |= MIPS_CPU_FPU; 1291 c->tlbsize = 64; 1292 break; 1293 case PRID_IMP_R3000: 1294 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1295 if (cpu_has_confreg()) { 1296 c->cputype = CPU_R3081E; 1297 __cpu_name[cpu] = "R3081"; 1298 } else { 1299 c->cputype = CPU_R3000A; 1300 __cpu_name[cpu] = "R3000A"; 1301 } 1302 } else { 1303 c->cputype = CPU_R3000; 1304 __cpu_name[cpu] = "R3000"; 1305 } 1306 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1307 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1308 MIPS_CPU_NOFPUEX; 1309 if (__cpu_has_fpu()) 1310 c->options |= MIPS_CPU_FPU; 1311 c->tlbsize = 64; 1312 break; 1313 case PRID_IMP_R4000: 1314 if (read_c0_config() & CONF_SC) { 1315 if ((c->processor_id & PRID_REV_MASK) >= 1316 PRID_REV_R4400) { 1317 c->cputype = CPU_R4400PC; 1318 __cpu_name[cpu] = "R4400PC"; 1319 } else { 1320 c->cputype = CPU_R4000PC; 1321 __cpu_name[cpu] = "R4000PC"; 1322 } 1323 } else { 1324 int cca = read_c0_config() & CONF_CM_CMASK; 1325 int mc; 1326 1327 /* 1328 * SC and MC versions can't be reliably told apart, 1329 * but only the latter support coherent caching 1330 * modes so assume the firmware has set the KSEG0 1331 * coherency attribute reasonably (if uncached, we 1332 * assume SC). 1333 */ 1334 switch (cca) { 1335 case CONF_CM_CACHABLE_CE: 1336 case CONF_CM_CACHABLE_COW: 1337 case CONF_CM_CACHABLE_CUW: 1338 mc = 1; 1339 break; 1340 default: 1341 mc = 0; 1342 break; 1343 } 1344 if ((c->processor_id & PRID_REV_MASK) >= 1345 PRID_REV_R4400) { 1346 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1347 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1348 } else { 1349 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1350 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1351 } 1352 } 1353 1354 set_isa(c, MIPS_CPU_ISA_III); 1355 c->fpu_msk31 |= FPU_CSR_CONDX; 1356 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1357 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1358 MIPS_CPU_LLSC; 1359 c->tlbsize = 48; 1360 break; 1361 case PRID_IMP_VR41XX: 1362 set_isa(c, MIPS_CPU_ISA_III); 1363 c->fpu_msk31 |= FPU_CSR_CONDX; 1364 c->options = R4K_OPTS; 1365 c->tlbsize = 32; 1366 switch (c->processor_id & 0xf0) { 1367 case PRID_REV_VR4111: 1368 c->cputype = CPU_VR4111; 1369 __cpu_name[cpu] = "NEC VR4111"; 1370 break; 1371 case PRID_REV_VR4121: 1372 c->cputype = CPU_VR4121; 1373 __cpu_name[cpu] = "NEC VR4121"; 1374 break; 1375 case PRID_REV_VR4122: 1376 if ((c->processor_id & 0xf) < 0x3) { 1377 c->cputype = CPU_VR4122; 1378 __cpu_name[cpu] = "NEC VR4122"; 1379 } else { 1380 c->cputype = CPU_VR4181A; 1381 __cpu_name[cpu] = "NEC VR4181A"; 1382 } 1383 break; 1384 case PRID_REV_VR4130: 1385 if ((c->processor_id & 0xf) < 0x4) { 1386 c->cputype = CPU_VR4131; 1387 __cpu_name[cpu] = "NEC VR4131"; 1388 } else { 1389 c->cputype = CPU_VR4133; 1390 c->options |= MIPS_CPU_LLSC; 1391 __cpu_name[cpu] = "NEC VR4133"; 1392 } 1393 break; 1394 default: 1395 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1396 c->cputype = CPU_VR41XX; 1397 __cpu_name[cpu] = "NEC Vr41xx"; 1398 break; 1399 } 1400 break; 1401 case PRID_IMP_R4600: 1402 c->cputype = CPU_R4600; 1403 __cpu_name[cpu] = "R4600"; 1404 set_isa(c, MIPS_CPU_ISA_III); 1405 c->fpu_msk31 |= FPU_CSR_CONDX; 1406 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1407 MIPS_CPU_LLSC; 1408 c->tlbsize = 48; 1409 break; 1410 #if 0 1411 case PRID_IMP_R4650: 1412 /* 1413 * This processor doesn't have an MMU, so it's not 1414 * "real easy" to run Linux on it. It is left purely 1415 * for documentation. Commented out because it shares 1416 * it's c0_prid id number with the TX3900. 1417 */ 1418 c->cputype = CPU_R4650; 1419 __cpu_name[cpu] = "R4650"; 1420 set_isa(c, MIPS_CPU_ISA_III); 1421 c->fpu_msk31 |= FPU_CSR_CONDX; 1422 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1423 c->tlbsize = 48; 1424 break; 1425 #endif 1426 case PRID_IMP_TX39: 1427 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1428 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1429 1430 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1431 c->cputype = CPU_TX3927; 1432 __cpu_name[cpu] = "TX3927"; 1433 c->tlbsize = 64; 1434 } else { 1435 switch (c->processor_id & PRID_REV_MASK) { 1436 case PRID_REV_TX3912: 1437 c->cputype = CPU_TX3912; 1438 __cpu_name[cpu] = "TX3912"; 1439 c->tlbsize = 32; 1440 break; 1441 case PRID_REV_TX3922: 1442 c->cputype = CPU_TX3922; 1443 __cpu_name[cpu] = "TX3922"; 1444 c->tlbsize = 64; 1445 break; 1446 } 1447 } 1448 break; 1449 case PRID_IMP_R4700: 1450 c->cputype = CPU_R4700; 1451 __cpu_name[cpu] = "R4700"; 1452 set_isa(c, MIPS_CPU_ISA_III); 1453 c->fpu_msk31 |= FPU_CSR_CONDX; 1454 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1455 MIPS_CPU_LLSC; 1456 c->tlbsize = 48; 1457 break; 1458 case PRID_IMP_TX49: 1459 c->cputype = CPU_TX49XX; 1460 __cpu_name[cpu] = "R49XX"; 1461 set_isa(c, MIPS_CPU_ISA_III); 1462 c->fpu_msk31 |= FPU_CSR_CONDX; 1463 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1464 if (!(c->processor_id & 0x08)) 1465 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1466 c->tlbsize = 48; 1467 break; 1468 case PRID_IMP_R5000: 1469 c->cputype = CPU_R5000; 1470 __cpu_name[cpu] = "R5000"; 1471 set_isa(c, MIPS_CPU_ISA_IV); 1472 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1473 MIPS_CPU_LLSC; 1474 c->tlbsize = 48; 1475 break; 1476 case PRID_IMP_R5500: 1477 c->cputype = CPU_R5500; 1478 __cpu_name[cpu] = "R5500"; 1479 set_isa(c, MIPS_CPU_ISA_IV); 1480 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1481 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1482 c->tlbsize = 48; 1483 break; 1484 case PRID_IMP_NEVADA: 1485 c->cputype = CPU_NEVADA; 1486 __cpu_name[cpu] = "Nevada"; 1487 set_isa(c, MIPS_CPU_ISA_IV); 1488 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1489 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1490 c->tlbsize = 48; 1491 break; 1492 case PRID_IMP_RM7000: 1493 c->cputype = CPU_RM7000; 1494 __cpu_name[cpu] = "RM7000"; 1495 set_isa(c, MIPS_CPU_ISA_IV); 1496 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1497 MIPS_CPU_LLSC; 1498 /* 1499 * Undocumented RM7000: Bit 29 in the info register of 1500 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1501 * entries. 1502 * 1503 * 29 1 => 64 entry JTLB 1504 * 0 => 48 entry JTLB 1505 */ 1506 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1507 break; 1508 case PRID_IMP_R10000: 1509 c->cputype = CPU_R10000; 1510 __cpu_name[cpu] = "R10000"; 1511 set_isa(c, MIPS_CPU_ISA_IV); 1512 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1513 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1514 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1515 MIPS_CPU_LLSC; 1516 c->tlbsize = 64; 1517 break; 1518 case PRID_IMP_R12000: 1519 c->cputype = CPU_R12000; 1520 __cpu_name[cpu] = "R12000"; 1521 set_isa(c, MIPS_CPU_ISA_IV); 1522 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1523 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1524 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1525 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1526 c->tlbsize = 64; 1527 break; 1528 case PRID_IMP_R14000: 1529 if (((c->processor_id >> 4) & 0x0f) > 2) { 1530 c->cputype = CPU_R16000; 1531 __cpu_name[cpu] = "R16000"; 1532 } else { 1533 c->cputype = CPU_R14000; 1534 __cpu_name[cpu] = "R14000"; 1535 } 1536 set_isa(c, MIPS_CPU_ISA_IV); 1537 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1538 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1539 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1540 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1541 c->tlbsize = 64; 1542 break; 1543 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ 1544 switch (c->processor_id & PRID_REV_MASK) { 1545 case PRID_REV_LOONGSON2E: 1546 c->cputype = CPU_LOONGSON2EF; 1547 __cpu_name[cpu] = "ICT Loongson-2"; 1548 set_elf_platform(cpu, "loongson2e"); 1549 set_isa(c, MIPS_CPU_ISA_III); 1550 c->fpu_msk31 |= FPU_CSR_CONDX; 1551 break; 1552 case PRID_REV_LOONGSON2F: 1553 c->cputype = CPU_LOONGSON2EF; 1554 __cpu_name[cpu] = "ICT Loongson-2"; 1555 set_elf_platform(cpu, "loongson2f"); 1556 set_isa(c, MIPS_CPU_ISA_III); 1557 c->fpu_msk31 |= FPU_CSR_CONDX; 1558 break; 1559 case PRID_REV_LOONGSON3A_R1: 1560 c->cputype = CPU_LOONGSON64; 1561 __cpu_name[cpu] = "ICT Loongson-3"; 1562 set_elf_platform(cpu, "loongson3a"); 1563 set_isa(c, MIPS_CPU_ISA_M64R1); 1564 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1565 MIPS_ASE_LOONGSON_EXT); 1566 break; 1567 case PRID_REV_LOONGSON3B_R1: 1568 case PRID_REV_LOONGSON3B_R2: 1569 c->cputype = CPU_LOONGSON64; 1570 __cpu_name[cpu] = "ICT Loongson-3"; 1571 set_elf_platform(cpu, "loongson3b"); 1572 set_isa(c, MIPS_CPU_ISA_M64R1); 1573 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1574 MIPS_ASE_LOONGSON_EXT); 1575 break; 1576 } 1577 1578 c->options = R4K_OPTS | 1579 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1580 MIPS_CPU_32FPR; 1581 c->tlbsize = 64; 1582 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); 1583 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1584 break; 1585 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1586 decode_configs(c); 1587 1588 c->cputype = CPU_LOONGSON32; 1589 1590 switch (c->processor_id & PRID_REV_MASK) { 1591 case PRID_REV_LOONGSON1B: 1592 __cpu_name[cpu] = "Loongson 1B"; 1593 break; 1594 } 1595 1596 break; 1597 } 1598 } 1599 1600 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1601 { 1602 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1603 switch (c->processor_id & PRID_IMP_MASK) { 1604 case PRID_IMP_QEMU_GENERIC: 1605 c->writecombine = _CACHE_UNCACHED; 1606 c->cputype = CPU_QEMU_GENERIC; 1607 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1608 break; 1609 case PRID_IMP_4KC: 1610 c->cputype = CPU_4KC; 1611 c->writecombine = _CACHE_UNCACHED; 1612 __cpu_name[cpu] = "MIPS 4Kc"; 1613 break; 1614 case PRID_IMP_4KEC: 1615 case PRID_IMP_4KECR2: 1616 c->cputype = CPU_4KEC; 1617 c->writecombine = _CACHE_UNCACHED; 1618 __cpu_name[cpu] = "MIPS 4KEc"; 1619 break; 1620 case PRID_IMP_4KSC: 1621 case PRID_IMP_4KSD: 1622 c->cputype = CPU_4KSC; 1623 c->writecombine = _CACHE_UNCACHED; 1624 __cpu_name[cpu] = "MIPS 4KSc"; 1625 break; 1626 case PRID_IMP_5KC: 1627 c->cputype = CPU_5KC; 1628 c->writecombine = _CACHE_UNCACHED; 1629 __cpu_name[cpu] = "MIPS 5Kc"; 1630 break; 1631 case PRID_IMP_5KE: 1632 c->cputype = CPU_5KE; 1633 c->writecombine = _CACHE_UNCACHED; 1634 __cpu_name[cpu] = "MIPS 5KE"; 1635 break; 1636 case PRID_IMP_20KC: 1637 c->cputype = CPU_20KC; 1638 c->writecombine = _CACHE_UNCACHED; 1639 __cpu_name[cpu] = "MIPS 20Kc"; 1640 break; 1641 case PRID_IMP_24K: 1642 c->cputype = CPU_24K; 1643 c->writecombine = _CACHE_UNCACHED; 1644 __cpu_name[cpu] = "MIPS 24Kc"; 1645 break; 1646 case PRID_IMP_24KE: 1647 c->cputype = CPU_24K; 1648 c->writecombine = _CACHE_UNCACHED; 1649 __cpu_name[cpu] = "MIPS 24KEc"; 1650 break; 1651 case PRID_IMP_25KF: 1652 c->cputype = CPU_25KF; 1653 c->writecombine = _CACHE_UNCACHED; 1654 __cpu_name[cpu] = "MIPS 25Kc"; 1655 break; 1656 case PRID_IMP_34K: 1657 c->cputype = CPU_34K; 1658 c->writecombine = _CACHE_UNCACHED; 1659 __cpu_name[cpu] = "MIPS 34Kc"; 1660 cpu_set_mt_per_tc_perf(c); 1661 break; 1662 case PRID_IMP_74K: 1663 c->cputype = CPU_74K; 1664 c->writecombine = _CACHE_UNCACHED; 1665 __cpu_name[cpu] = "MIPS 74Kc"; 1666 break; 1667 case PRID_IMP_M14KC: 1668 c->cputype = CPU_M14KC; 1669 c->writecombine = _CACHE_UNCACHED; 1670 __cpu_name[cpu] = "MIPS M14Kc"; 1671 break; 1672 case PRID_IMP_M14KEC: 1673 c->cputype = CPU_M14KEC; 1674 c->writecombine = _CACHE_UNCACHED; 1675 __cpu_name[cpu] = "MIPS M14KEc"; 1676 break; 1677 case PRID_IMP_1004K: 1678 c->cputype = CPU_1004K; 1679 c->writecombine = _CACHE_UNCACHED; 1680 __cpu_name[cpu] = "MIPS 1004Kc"; 1681 cpu_set_mt_per_tc_perf(c); 1682 break; 1683 case PRID_IMP_1074K: 1684 c->cputype = CPU_1074K; 1685 c->writecombine = _CACHE_UNCACHED; 1686 __cpu_name[cpu] = "MIPS 1074Kc"; 1687 break; 1688 case PRID_IMP_INTERAPTIV_UP: 1689 c->cputype = CPU_INTERAPTIV; 1690 __cpu_name[cpu] = "MIPS interAptiv"; 1691 cpu_set_mt_per_tc_perf(c); 1692 break; 1693 case PRID_IMP_INTERAPTIV_MP: 1694 c->cputype = CPU_INTERAPTIV; 1695 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1696 cpu_set_mt_per_tc_perf(c); 1697 break; 1698 case PRID_IMP_PROAPTIV_UP: 1699 c->cputype = CPU_PROAPTIV; 1700 __cpu_name[cpu] = "MIPS proAptiv"; 1701 break; 1702 case PRID_IMP_PROAPTIV_MP: 1703 c->cputype = CPU_PROAPTIV; 1704 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1705 break; 1706 case PRID_IMP_P5600: 1707 c->cputype = CPU_P5600; 1708 __cpu_name[cpu] = "MIPS P5600"; 1709 break; 1710 case PRID_IMP_P6600: 1711 c->cputype = CPU_P6600; 1712 __cpu_name[cpu] = "MIPS P6600"; 1713 break; 1714 case PRID_IMP_I6400: 1715 c->cputype = CPU_I6400; 1716 __cpu_name[cpu] = "MIPS I6400"; 1717 break; 1718 case PRID_IMP_I6500: 1719 c->cputype = CPU_I6500; 1720 __cpu_name[cpu] = "MIPS I6500"; 1721 break; 1722 case PRID_IMP_M5150: 1723 c->cputype = CPU_M5150; 1724 __cpu_name[cpu] = "MIPS M5150"; 1725 break; 1726 case PRID_IMP_M6250: 1727 c->cputype = CPU_M6250; 1728 __cpu_name[cpu] = "MIPS M6250"; 1729 break; 1730 } 1731 1732 decode_configs(c); 1733 1734 spram_config(); 1735 1736 switch (__get_cpu_type(c->cputype)) { 1737 case CPU_I6500: 1738 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1739 /* fall-through */ 1740 case CPU_I6400: 1741 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1742 /* fall-through */ 1743 default: 1744 break; 1745 } 1746 } 1747 1748 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1749 { 1750 decode_configs(c); 1751 switch (c->processor_id & PRID_IMP_MASK) { 1752 case PRID_IMP_AU1_REV1: 1753 case PRID_IMP_AU1_REV2: 1754 c->cputype = CPU_ALCHEMY; 1755 switch ((c->processor_id >> 24) & 0xff) { 1756 case 0: 1757 __cpu_name[cpu] = "Au1000"; 1758 break; 1759 case 1: 1760 __cpu_name[cpu] = "Au1500"; 1761 break; 1762 case 2: 1763 __cpu_name[cpu] = "Au1100"; 1764 break; 1765 case 3: 1766 __cpu_name[cpu] = "Au1550"; 1767 break; 1768 case 4: 1769 __cpu_name[cpu] = "Au1200"; 1770 if ((c->processor_id & PRID_REV_MASK) == 2) 1771 __cpu_name[cpu] = "Au1250"; 1772 break; 1773 case 5: 1774 __cpu_name[cpu] = "Au1210"; 1775 break; 1776 default: 1777 __cpu_name[cpu] = "Au1xxx"; 1778 break; 1779 } 1780 break; 1781 } 1782 } 1783 1784 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1785 { 1786 decode_configs(c); 1787 1788 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1789 switch (c->processor_id & PRID_IMP_MASK) { 1790 case PRID_IMP_SB1: 1791 c->cputype = CPU_SB1; 1792 __cpu_name[cpu] = "SiByte SB1"; 1793 /* FPU in pass1 is known to have issues. */ 1794 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1795 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1796 break; 1797 case PRID_IMP_SB1A: 1798 c->cputype = CPU_SB1A; 1799 __cpu_name[cpu] = "SiByte SB1A"; 1800 break; 1801 } 1802 } 1803 1804 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1805 { 1806 decode_configs(c); 1807 switch (c->processor_id & PRID_IMP_MASK) { 1808 case PRID_IMP_SR71000: 1809 c->cputype = CPU_SR71000; 1810 __cpu_name[cpu] = "Sandcraft SR71000"; 1811 c->scache.ways = 8; 1812 c->tlbsize = 64; 1813 break; 1814 } 1815 } 1816 1817 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1818 { 1819 decode_configs(c); 1820 switch (c->processor_id & PRID_IMP_MASK) { 1821 case PRID_IMP_PR4450: 1822 c->cputype = CPU_PR4450; 1823 __cpu_name[cpu] = "Philips PR4450"; 1824 set_isa(c, MIPS_CPU_ISA_M32R1); 1825 break; 1826 } 1827 } 1828 1829 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1830 { 1831 decode_configs(c); 1832 switch (c->processor_id & PRID_IMP_MASK) { 1833 case PRID_IMP_BMIPS32_REV4: 1834 case PRID_IMP_BMIPS32_REV8: 1835 c->cputype = CPU_BMIPS32; 1836 __cpu_name[cpu] = "Broadcom BMIPS32"; 1837 set_elf_platform(cpu, "bmips32"); 1838 break; 1839 case PRID_IMP_BMIPS3300: 1840 case PRID_IMP_BMIPS3300_ALT: 1841 case PRID_IMP_BMIPS3300_BUG: 1842 c->cputype = CPU_BMIPS3300; 1843 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1844 set_elf_platform(cpu, "bmips3300"); 1845 break; 1846 case PRID_IMP_BMIPS43XX: { 1847 int rev = c->processor_id & PRID_REV_MASK; 1848 1849 if (rev >= PRID_REV_BMIPS4380_LO && 1850 rev <= PRID_REV_BMIPS4380_HI) { 1851 c->cputype = CPU_BMIPS4380; 1852 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1853 set_elf_platform(cpu, "bmips4380"); 1854 c->options |= MIPS_CPU_RIXI; 1855 } else { 1856 c->cputype = CPU_BMIPS4350; 1857 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1858 set_elf_platform(cpu, "bmips4350"); 1859 } 1860 break; 1861 } 1862 case PRID_IMP_BMIPS5000: 1863 case PRID_IMP_BMIPS5200: 1864 c->cputype = CPU_BMIPS5000; 1865 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1866 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1867 else 1868 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1869 set_elf_platform(cpu, "bmips5000"); 1870 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1871 break; 1872 } 1873 } 1874 1875 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1876 { 1877 decode_configs(c); 1878 switch (c->processor_id & PRID_IMP_MASK) { 1879 case PRID_IMP_CAVIUM_CN38XX: 1880 case PRID_IMP_CAVIUM_CN31XX: 1881 case PRID_IMP_CAVIUM_CN30XX: 1882 c->cputype = CPU_CAVIUM_OCTEON; 1883 __cpu_name[cpu] = "Cavium Octeon"; 1884 goto platform; 1885 case PRID_IMP_CAVIUM_CN58XX: 1886 case PRID_IMP_CAVIUM_CN56XX: 1887 case PRID_IMP_CAVIUM_CN50XX: 1888 case PRID_IMP_CAVIUM_CN52XX: 1889 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1890 __cpu_name[cpu] = "Cavium Octeon+"; 1891 platform: 1892 set_elf_platform(cpu, "octeon"); 1893 break; 1894 case PRID_IMP_CAVIUM_CN61XX: 1895 case PRID_IMP_CAVIUM_CN63XX: 1896 case PRID_IMP_CAVIUM_CN66XX: 1897 case PRID_IMP_CAVIUM_CN68XX: 1898 case PRID_IMP_CAVIUM_CNF71XX: 1899 c->cputype = CPU_CAVIUM_OCTEON2; 1900 __cpu_name[cpu] = "Cavium Octeon II"; 1901 set_elf_platform(cpu, "octeon2"); 1902 break; 1903 case PRID_IMP_CAVIUM_CN70XX: 1904 case PRID_IMP_CAVIUM_CN73XX: 1905 case PRID_IMP_CAVIUM_CNF75XX: 1906 case PRID_IMP_CAVIUM_CN78XX: 1907 c->cputype = CPU_CAVIUM_OCTEON3; 1908 __cpu_name[cpu] = "Cavium Octeon III"; 1909 set_elf_platform(cpu, "octeon3"); 1910 break; 1911 default: 1912 printk(KERN_INFO "Unknown Octeon chip!\n"); 1913 c->cputype = CPU_UNKNOWN; 1914 break; 1915 } 1916 } 1917 1918 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1919 { 1920 switch (c->processor_id & PRID_IMP_MASK) { 1921 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ 1922 switch (c->processor_id & PRID_REV_MASK) { 1923 case PRID_REV_LOONGSON3A_R2_0: 1924 case PRID_REV_LOONGSON3A_R2_1: 1925 c->cputype = CPU_LOONGSON64; 1926 __cpu_name[cpu] = "ICT Loongson-3"; 1927 set_elf_platform(cpu, "loongson3a"); 1928 set_isa(c, MIPS_CPU_ISA_M64R2); 1929 break; 1930 case PRID_REV_LOONGSON3A_R3_0: 1931 case PRID_REV_LOONGSON3A_R3_1: 1932 c->cputype = CPU_LOONGSON64; 1933 __cpu_name[cpu] = "ICT Loongson-3"; 1934 set_elf_platform(cpu, "loongson3a"); 1935 set_isa(c, MIPS_CPU_ISA_M64R2); 1936 break; 1937 } 1938 1939 decode_configs(c); 1940 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1941 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1942 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1943 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); 1944 break; 1945 case PRID_IMP_LOONGSON_64G: 1946 c->cputype = CPU_LOONGSON64; 1947 __cpu_name[cpu] = "ICT Loongson-3"; 1948 set_elf_platform(cpu, "loongson3a"); 1949 set_isa(c, MIPS_CPU_ISA_M64R2); 1950 decode_configs(c); 1951 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1952 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1953 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1954 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); 1955 break; 1956 default: 1957 panic("Unknown Loongson Processor ID!"); 1958 break; 1959 } 1960 } 1961 1962 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1963 { 1964 decode_configs(c); 1965 1966 /* 1967 * XBurst misses a config2 register, so config3 decode was skipped in 1968 * decode_configs(). 1969 */ 1970 decode_config3(c); 1971 1972 /* XBurst does not implement the CP0 counter. */ 1973 c->options &= ~MIPS_CPU_COUNTER; 1974 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1975 1976 switch (c->processor_id & PRID_IMP_MASK) { 1977 case PRID_IMP_XBURST_REV1: 1978 1979 /* 1980 * The XBurst core by default attempts to avoid branch target 1981 * buffer lookups by detecting & special casing loops. This 1982 * feature will cause BogoMIPS and lpj calculate in error. 1983 * Set cp0 config7 bit 4 to disable this feature. 1984 */ 1985 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); 1986 1987 switch (c->processor_id & PRID_COMP_MASK) { 1988 1989 /* 1990 * The config0 register in the XBurst CPUs with a processor ID of 1991 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1992 * but they don't actually support this ISA. 1993 */ 1994 case PRID_COMP_INGENIC_D0: 1995 c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1996 break; 1997 1998 /* 1999 * The config0 register in the XBurst CPUs with a processor ID of 2000 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this 2001 * mode is not compatible with the MIPS standard, it will cause 2002 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S) 2003 * when starting the init process. After chip reset, the default 2004 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to 2005 * switch back to VTLB mode to prevent getting stuck. 2006 */ 2007 case PRID_COMP_INGENIC_D1: 2008 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); 2009 break; 2010 2011 default: 2012 break; 2013 } 2014 /* fall-through */ 2015 case PRID_IMP_XBURST_REV2: 2016 c->cputype = CPU_XBURST; 2017 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 2018 __cpu_name[cpu] = "Ingenic XBurst"; 2019 break; 2020 2021 default: 2022 panic("Unknown Ingenic Processor ID!"); 2023 break; 2024 } 2025 } 2026 2027 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 2028 { 2029 decode_configs(c); 2030 2031 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 2032 c->cputype = CPU_ALCHEMY; 2033 __cpu_name[cpu] = "Au1300"; 2034 /* following stuff is not for Alchemy */ 2035 return; 2036 } 2037 2038 c->options = (MIPS_CPU_TLB | 2039 MIPS_CPU_4KEX | 2040 MIPS_CPU_COUNTER | 2041 MIPS_CPU_DIVEC | 2042 MIPS_CPU_WATCH | 2043 MIPS_CPU_EJTAG | 2044 MIPS_CPU_LLSC); 2045 2046 switch (c->processor_id & PRID_IMP_MASK) { 2047 case PRID_IMP_NETLOGIC_XLP2XX: 2048 case PRID_IMP_NETLOGIC_XLP9XX: 2049 case PRID_IMP_NETLOGIC_XLP5XX: 2050 c->cputype = CPU_XLP; 2051 __cpu_name[cpu] = "Broadcom XLPII"; 2052 break; 2053 2054 case PRID_IMP_NETLOGIC_XLP8XX: 2055 case PRID_IMP_NETLOGIC_XLP3XX: 2056 c->cputype = CPU_XLP; 2057 __cpu_name[cpu] = "Netlogic XLP"; 2058 break; 2059 2060 case PRID_IMP_NETLOGIC_XLR732: 2061 case PRID_IMP_NETLOGIC_XLR716: 2062 case PRID_IMP_NETLOGIC_XLR532: 2063 case PRID_IMP_NETLOGIC_XLR308: 2064 case PRID_IMP_NETLOGIC_XLR532C: 2065 case PRID_IMP_NETLOGIC_XLR516C: 2066 case PRID_IMP_NETLOGIC_XLR508C: 2067 case PRID_IMP_NETLOGIC_XLR308C: 2068 c->cputype = CPU_XLR; 2069 __cpu_name[cpu] = "Netlogic XLR"; 2070 break; 2071 2072 case PRID_IMP_NETLOGIC_XLS608: 2073 case PRID_IMP_NETLOGIC_XLS408: 2074 case PRID_IMP_NETLOGIC_XLS404: 2075 case PRID_IMP_NETLOGIC_XLS208: 2076 case PRID_IMP_NETLOGIC_XLS204: 2077 case PRID_IMP_NETLOGIC_XLS108: 2078 case PRID_IMP_NETLOGIC_XLS104: 2079 case PRID_IMP_NETLOGIC_XLS616B: 2080 case PRID_IMP_NETLOGIC_XLS608B: 2081 case PRID_IMP_NETLOGIC_XLS416B: 2082 case PRID_IMP_NETLOGIC_XLS412B: 2083 case PRID_IMP_NETLOGIC_XLS408B: 2084 case PRID_IMP_NETLOGIC_XLS404B: 2085 c->cputype = CPU_XLR; 2086 __cpu_name[cpu] = "Netlogic XLS"; 2087 break; 2088 2089 default: 2090 pr_info("Unknown Netlogic chip id [%02x]!\n", 2091 c->processor_id); 2092 c->cputype = CPU_XLR; 2093 break; 2094 } 2095 2096 if (c->cputype == CPU_XLP) { 2097 set_isa(c, MIPS_CPU_ISA_M64R2); 2098 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 2099 /* This will be updated again after all threads are woken up */ 2100 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 2101 } else { 2102 set_isa(c, MIPS_CPU_ISA_M64R1); 2103 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 2104 } 2105 c->kscratch_mask = 0xf; 2106 } 2107 2108 #ifdef CONFIG_64BIT 2109 /* For use by uaccess.h */ 2110 u64 __ua_limit; 2111 EXPORT_SYMBOL(__ua_limit); 2112 #endif 2113 2114 const char *__cpu_name[NR_CPUS]; 2115 const char *__elf_platform; 2116 2117 void cpu_probe(void) 2118 { 2119 struct cpuinfo_mips *c = ¤t_cpu_data; 2120 unsigned int cpu = smp_processor_id(); 2121 2122 /* 2123 * Set a default elf platform, cpu probe may later 2124 * overwrite it with a more precise value 2125 */ 2126 set_elf_platform(cpu, "mips"); 2127 2128 c->processor_id = PRID_IMP_UNKNOWN; 2129 c->fpu_id = FPIR_IMP_NONE; 2130 c->cputype = CPU_UNKNOWN; 2131 c->writecombine = _CACHE_UNCACHED; 2132 2133 c->fpu_csr31 = FPU_CSR_RN; 2134 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 2135 2136 c->processor_id = read_c0_prid(); 2137 switch (c->processor_id & PRID_COMP_MASK) { 2138 case PRID_COMP_LEGACY: 2139 cpu_probe_legacy(c, cpu); 2140 break; 2141 case PRID_COMP_MIPS: 2142 cpu_probe_mips(c, cpu); 2143 break; 2144 case PRID_COMP_ALCHEMY: 2145 cpu_probe_alchemy(c, cpu); 2146 break; 2147 case PRID_COMP_SIBYTE: 2148 cpu_probe_sibyte(c, cpu); 2149 break; 2150 case PRID_COMP_BROADCOM: 2151 cpu_probe_broadcom(c, cpu); 2152 break; 2153 case PRID_COMP_SANDCRAFT: 2154 cpu_probe_sandcraft(c, cpu); 2155 break; 2156 case PRID_COMP_NXP: 2157 cpu_probe_nxp(c, cpu); 2158 break; 2159 case PRID_COMP_CAVIUM: 2160 cpu_probe_cavium(c, cpu); 2161 break; 2162 case PRID_COMP_LOONGSON: 2163 cpu_probe_loongson(c, cpu); 2164 break; 2165 case PRID_COMP_INGENIC_D0: 2166 case PRID_COMP_INGENIC_D1: 2167 case PRID_COMP_INGENIC_E1: 2168 cpu_probe_ingenic(c, cpu); 2169 break; 2170 case PRID_COMP_NETLOGIC: 2171 cpu_probe_netlogic(c, cpu); 2172 break; 2173 } 2174 2175 BUG_ON(!__cpu_name[cpu]); 2176 BUG_ON(c->cputype == CPU_UNKNOWN); 2177 2178 /* 2179 * Platform code can force the cpu type to optimize code 2180 * generation. In that case be sure the cpu type is correctly 2181 * manually setup otherwise it could trigger some nasty bugs. 2182 */ 2183 BUG_ON(current_cpu_type() != c->cputype); 2184 2185 if (cpu_has_rixi) { 2186 /* Enable the RIXI exceptions */ 2187 set_c0_pagegrain(PG_IEC); 2188 back_to_back_c0_hazard(); 2189 /* Verify the IEC bit is set */ 2190 if (read_c0_pagegrain() & PG_IEC) 2191 c->options |= MIPS_CPU_RIXIEX; 2192 } 2193 2194 if (mips_fpu_disabled) 2195 c->options &= ~MIPS_CPU_FPU; 2196 2197 if (mips_dsp_disabled) 2198 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2199 2200 if (mips_htw_disabled) { 2201 c->options &= ~MIPS_CPU_HTW; 2202 write_c0_pwctl(read_c0_pwctl() & 2203 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2204 } 2205 2206 if (c->options & MIPS_CPU_FPU) 2207 cpu_set_fpu_opts(c); 2208 else 2209 cpu_set_nofpu_opts(c); 2210 2211 if (cpu_has_bp_ghist) 2212 write_c0_r10k_diag(read_c0_r10k_diag() | 2213 R10K_DIAG_E_GHIST); 2214 2215 if (cpu_has_mips_r2_r6) { 2216 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2217 /* R2 has Performance Counter Interrupt indicator */ 2218 c->options |= MIPS_CPU_PCI; 2219 } 2220 else 2221 c->srsets = 1; 2222 2223 if (cpu_has_mips_r6) 2224 elf_hwcap |= HWCAP_MIPS_R6; 2225 2226 if (cpu_has_msa) { 2227 c->msa_id = cpu_get_msa_id(); 2228 WARN(c->msa_id & MSA_IR_WRPF, 2229 "Vector register partitioning unimplemented!"); 2230 elf_hwcap |= HWCAP_MIPS_MSA; 2231 } 2232 2233 if (cpu_has_mips16) 2234 elf_hwcap |= HWCAP_MIPS_MIPS16; 2235 2236 if (cpu_has_mdmx) 2237 elf_hwcap |= HWCAP_MIPS_MDMX; 2238 2239 if (cpu_has_mips3d) 2240 elf_hwcap |= HWCAP_MIPS_MIPS3D; 2241 2242 if (cpu_has_smartmips) 2243 elf_hwcap |= HWCAP_MIPS_SMARTMIPS; 2244 2245 if (cpu_has_dsp) 2246 elf_hwcap |= HWCAP_MIPS_DSP; 2247 2248 if (cpu_has_dsp2) 2249 elf_hwcap |= HWCAP_MIPS_DSP2; 2250 2251 if (cpu_has_dsp3) 2252 elf_hwcap |= HWCAP_MIPS_DSP3; 2253 2254 if (cpu_has_mips16e2) 2255 elf_hwcap |= HWCAP_MIPS_MIPS16E2; 2256 2257 if (cpu_has_loongson_mmi) 2258 elf_hwcap |= HWCAP_LOONGSON_MMI; 2259 2260 if (cpu_has_loongson_ext) 2261 elf_hwcap |= HWCAP_LOONGSON_EXT; 2262 2263 if (cpu_has_loongson_ext2) 2264 elf_hwcap |= HWCAP_LOONGSON_EXT2; 2265 2266 if (cpu_has_vz) 2267 cpu_probe_vz(c); 2268 2269 cpu_probe_vmbits(c); 2270 2271 #ifdef CONFIG_64BIT 2272 if (cpu == 0) 2273 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2274 #endif 2275 } 2276 2277 void cpu_report(void) 2278 { 2279 struct cpuinfo_mips *c = ¤t_cpu_data; 2280 2281 pr_info("CPU%d revision is: %08x (%s)\n", 2282 smp_processor_id(), c->processor_id, cpu_name_string()); 2283 if (c->options & MIPS_CPU_FPU) 2284 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2285 if (cpu_has_msa) 2286 pr_info("MSA revision is: %08x\n", c->msa_id); 2287 } 2288 2289 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) 2290 { 2291 /* Ensure the core number fits in the field */ 2292 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> 2293 MIPS_GLOBALNUMBER_CLUSTER_SHF)); 2294 2295 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; 2296 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; 2297 } 2298 2299 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) 2300 { 2301 /* Ensure the core number fits in the field */ 2302 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); 2303 2304 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; 2305 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; 2306 } 2307 2308 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) 2309 { 2310 /* Ensure the VP(E) ID fits in the field */ 2311 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); 2312 2313 /* Ensure we're not using VP(E)s without support */ 2314 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && 2315 !IS_ENABLED(CONFIG_CPU_MIPSR6)); 2316 2317 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; 2318 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; 2319 } 2320