1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void) = NULL; 33 34 static void r3081_wait(void) 35 { 36 unsigned long cfg = read_c0_conf(); 37 write_c0_conf(cfg | R30XX_CONF_HALT); 38 } 39 40 static void r39xx_wait(void) 41 { 42 local_irq_disable(); 43 if (!need_resched()) 44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 45 local_irq_enable(); 46 } 47 48 /* 49 * There is a race when WAIT instruction executed with interrupt 50 * enabled. 51 * But it is implementation-dependent wheter the pipelie restarts when 52 * a non-enabled interrupt is requested. 53 */ 54 static void r4k_wait(void) 55 { 56 __asm__(" .set mips3 \n" 57 " wait \n" 58 " .set mips0 \n"); 59 } 60 61 /* 62 * This variant is preferable as it allows testing need_resched and going to 63 * sleep depending on the outcome atomically. Unfortunately the "It is 64 * implementation-dependent whether the pipeline restarts when a non-enabled 65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 66 * using this version a gamble. 67 */ 68 static void r4k_wait_irqoff(void) 69 { 70 local_irq_disable(); 71 if (!need_resched()) 72 __asm__(" .set mips3 \n" 73 " wait \n" 74 " .set mips0 \n"); 75 local_irq_enable(); 76 } 77 78 /* The Au1xxx wait is available only if using 32khz counter or 79 * external timer source, but specifically not CP0 Counter. */ 80 int allow_au1k_wait; 81 82 static void au1k_wait(void) 83 { 84 /* using the wait instruction makes CP0 counter unusable */ 85 __asm__(" .set mips3 \n" 86 " cache 0x14, 0(%0) \n" 87 " cache 0x14, 32(%0) \n" 88 " sync \n" 89 " nop \n" 90 " wait \n" 91 " nop \n" 92 " nop \n" 93 " nop \n" 94 " nop \n" 95 " .set mips0 \n" 96 : : "r" (au1k_wait)); 97 } 98 99 static int __initdata nowait = 0; 100 101 static int __init wait_disable(char *s) 102 { 103 nowait = 1; 104 105 return 1; 106 } 107 108 __setup("nowait", wait_disable); 109 110 static inline void check_wait(void) 111 { 112 struct cpuinfo_mips *c = ¤t_cpu_data; 113 114 if (nowait) { 115 printk("Wait instruction disabled.\n"); 116 return; 117 } 118 119 switch (c->cputype) { 120 case CPU_R3081: 121 case CPU_R3081E: 122 cpu_wait = r3081_wait; 123 break; 124 case CPU_TX3927: 125 cpu_wait = r39xx_wait; 126 break; 127 case CPU_R4200: 128 /* case CPU_R4300: */ 129 case CPU_R4600: 130 case CPU_R4640: 131 case CPU_R4650: 132 case CPU_R4700: 133 case CPU_R5000: 134 case CPU_NEVADA: 135 case CPU_RM7000: 136 case CPU_4KC: 137 case CPU_4KEC: 138 case CPU_4KSC: 139 case CPU_5KC: 140 case CPU_25KF: 141 case CPU_PR4450: 142 cpu_wait = r4k_wait; 143 break; 144 145 case CPU_24K: 146 case CPU_34K: 147 cpu_wait = r4k_wait; 148 if (read_c0_config7() & MIPS_CONF7_WII) 149 cpu_wait = r4k_wait_irqoff; 150 break; 151 152 case CPU_74K: 153 cpu_wait = r4k_wait; 154 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 155 cpu_wait = r4k_wait_irqoff; 156 break; 157 158 case CPU_TX49XX: 159 cpu_wait = r4k_wait_irqoff; 160 break; 161 case CPU_AU1000: 162 case CPU_AU1100: 163 case CPU_AU1500: 164 case CPU_AU1550: 165 case CPU_AU1200: 166 if (allow_au1k_wait) 167 cpu_wait = au1k_wait; 168 break; 169 case CPU_20KC: 170 /* 171 * WAIT on Rev1.0 has E1, E2, E3 and E16. 172 * WAIT on Rev2.0 and Rev3.0 has E16. 173 * Rev3.1 WAIT is nop, why bother 174 */ 175 if ((c->processor_id & 0xff) <= 0x64) 176 break; 177 178 cpu_wait = r4k_wait; 179 break; 180 case CPU_RM9000: 181 if ((c->processor_id & 0x00ff) >= 0x40) 182 cpu_wait = r4k_wait; 183 break; 184 default: 185 break; 186 } 187 } 188 189 static inline void check_errata(void) 190 { 191 struct cpuinfo_mips *c = ¤t_cpu_data; 192 193 switch (c->cputype) { 194 case CPU_34K: 195 /* 196 * Erratum "RPS May Cause Incorrect Instruction Execution" 197 * This code only handles VPE0, any SMP/SMTC/RTOS code 198 * making use of VPE1 will be responsable for that VPE. 199 */ 200 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 201 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 202 break; 203 default: 204 break; 205 } 206 } 207 208 void __init check_bugs32(void) 209 { 210 check_wait(); 211 check_errata(); 212 } 213 214 /* 215 * Probe whether cpu has config register by trying to play with 216 * alternate cache bit and see whether it matters. 217 * It's used by cpu_probe to distinguish between R3000A and R3081. 218 */ 219 static inline int cpu_has_confreg(void) 220 { 221 #ifdef CONFIG_CPU_R3000 222 extern unsigned long r3k_cache_size(unsigned long); 223 unsigned long size1, size2; 224 unsigned long cfg = read_c0_conf(); 225 226 size1 = r3k_cache_size(ST0_ISC); 227 write_c0_conf(cfg ^ R30XX_CONF_AC); 228 size2 = r3k_cache_size(ST0_ISC); 229 write_c0_conf(cfg); 230 return size1 != size2; 231 #else 232 return 0; 233 #endif 234 } 235 236 /* 237 * Get the FPU Implementation/Revision. 238 */ 239 static inline unsigned long cpu_get_fpu_id(void) 240 { 241 unsigned long tmp, fpu_id; 242 243 tmp = read_c0_status(); 244 __enable_fpu(); 245 fpu_id = read_32bit_cp1_register(CP1_REVISION); 246 write_c0_status(tmp); 247 return fpu_id; 248 } 249 250 /* 251 * Check the CPU has an FPU the official way. 252 */ 253 static inline int __cpu_has_fpu(void) 254 { 255 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 256 } 257 258 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 259 | MIPS_CPU_COUNTER) 260 261 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 262 { 263 switch (c->processor_id & 0xff00) { 264 case PRID_IMP_R2000: 265 c->cputype = CPU_R2000; 266 c->isa_level = MIPS_CPU_ISA_I; 267 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 268 MIPS_CPU_NOFPUEX; 269 if (__cpu_has_fpu()) 270 c->options |= MIPS_CPU_FPU; 271 c->tlbsize = 64; 272 break; 273 case PRID_IMP_R3000: 274 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 275 if (cpu_has_confreg()) 276 c->cputype = CPU_R3081E; 277 else 278 c->cputype = CPU_R3000A; 279 else 280 c->cputype = CPU_R3000; 281 c->isa_level = MIPS_CPU_ISA_I; 282 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 283 MIPS_CPU_NOFPUEX; 284 if (__cpu_has_fpu()) 285 c->options |= MIPS_CPU_FPU; 286 c->tlbsize = 64; 287 break; 288 case PRID_IMP_R4000: 289 if (read_c0_config() & CONF_SC) { 290 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 291 c->cputype = CPU_R4400PC; 292 else 293 c->cputype = CPU_R4000PC; 294 } else { 295 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 296 c->cputype = CPU_R4400SC; 297 else 298 c->cputype = CPU_R4000SC; 299 } 300 301 c->isa_level = MIPS_CPU_ISA_III; 302 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 303 MIPS_CPU_WATCH | MIPS_CPU_VCE | 304 MIPS_CPU_LLSC; 305 c->tlbsize = 48; 306 break; 307 case PRID_IMP_VR41XX: 308 switch (c->processor_id & 0xf0) { 309 case PRID_REV_VR4111: 310 c->cputype = CPU_VR4111; 311 break; 312 case PRID_REV_VR4121: 313 c->cputype = CPU_VR4121; 314 break; 315 case PRID_REV_VR4122: 316 if ((c->processor_id & 0xf) < 0x3) 317 c->cputype = CPU_VR4122; 318 else 319 c->cputype = CPU_VR4181A; 320 break; 321 case PRID_REV_VR4130: 322 if ((c->processor_id & 0xf) < 0x4) 323 c->cputype = CPU_VR4131; 324 else 325 c->cputype = CPU_VR4133; 326 break; 327 default: 328 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 329 c->cputype = CPU_VR41XX; 330 break; 331 } 332 c->isa_level = MIPS_CPU_ISA_III; 333 c->options = R4K_OPTS; 334 c->tlbsize = 32; 335 break; 336 case PRID_IMP_R4300: 337 c->cputype = CPU_R4300; 338 c->isa_level = MIPS_CPU_ISA_III; 339 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 340 MIPS_CPU_LLSC; 341 c->tlbsize = 32; 342 break; 343 case PRID_IMP_R4600: 344 c->cputype = CPU_R4600; 345 c->isa_level = MIPS_CPU_ISA_III; 346 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 347 MIPS_CPU_LLSC; 348 c->tlbsize = 48; 349 break; 350 #if 0 351 case PRID_IMP_R4650: 352 /* 353 * This processor doesn't have an MMU, so it's not 354 * "real easy" to run Linux on it. It is left purely 355 * for documentation. Commented out because it shares 356 * it's c0_prid id number with the TX3900. 357 */ 358 c->cputype = CPU_R4650; 359 c->isa_level = MIPS_CPU_ISA_III; 360 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 361 c->tlbsize = 48; 362 break; 363 #endif 364 case PRID_IMP_TX39: 365 c->isa_level = MIPS_CPU_ISA_I; 366 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 367 368 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 369 c->cputype = CPU_TX3927; 370 c->tlbsize = 64; 371 } else { 372 switch (c->processor_id & 0xff) { 373 case PRID_REV_TX3912: 374 c->cputype = CPU_TX3912; 375 c->tlbsize = 32; 376 break; 377 case PRID_REV_TX3922: 378 c->cputype = CPU_TX3922; 379 c->tlbsize = 64; 380 break; 381 default: 382 c->cputype = CPU_UNKNOWN; 383 break; 384 } 385 } 386 break; 387 case PRID_IMP_R4700: 388 c->cputype = CPU_R4700; 389 c->isa_level = MIPS_CPU_ISA_III; 390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 391 MIPS_CPU_LLSC; 392 c->tlbsize = 48; 393 break; 394 case PRID_IMP_TX49: 395 c->cputype = CPU_TX49XX; 396 c->isa_level = MIPS_CPU_ISA_III; 397 c->options = R4K_OPTS | MIPS_CPU_LLSC; 398 if (!(c->processor_id & 0x08)) 399 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 400 c->tlbsize = 48; 401 break; 402 case PRID_IMP_R5000: 403 c->cputype = CPU_R5000; 404 c->isa_level = MIPS_CPU_ISA_IV; 405 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 406 MIPS_CPU_LLSC; 407 c->tlbsize = 48; 408 break; 409 case PRID_IMP_R5432: 410 c->cputype = CPU_R5432; 411 c->isa_level = MIPS_CPU_ISA_IV; 412 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 413 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 414 c->tlbsize = 48; 415 break; 416 case PRID_IMP_R5500: 417 c->cputype = CPU_R5500; 418 c->isa_level = MIPS_CPU_ISA_IV; 419 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 420 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 421 c->tlbsize = 48; 422 break; 423 case PRID_IMP_NEVADA: 424 c->cputype = CPU_NEVADA; 425 c->isa_level = MIPS_CPU_ISA_IV; 426 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 427 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 428 c->tlbsize = 48; 429 break; 430 case PRID_IMP_R6000: 431 c->cputype = CPU_R6000; 432 c->isa_level = MIPS_CPU_ISA_II; 433 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 434 MIPS_CPU_LLSC; 435 c->tlbsize = 32; 436 break; 437 case PRID_IMP_R6000A: 438 c->cputype = CPU_R6000A; 439 c->isa_level = MIPS_CPU_ISA_II; 440 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 441 MIPS_CPU_LLSC; 442 c->tlbsize = 32; 443 break; 444 case PRID_IMP_RM7000: 445 c->cputype = CPU_RM7000; 446 c->isa_level = MIPS_CPU_ISA_IV; 447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 448 MIPS_CPU_LLSC; 449 /* 450 * Undocumented RM7000: Bit 29 in the info register of 451 * the RM7000 v2.0 indicates if the TLB has 48 or 64 452 * entries. 453 * 454 * 29 1 => 64 entry JTLB 455 * 0 => 48 entry JTLB 456 */ 457 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 458 break; 459 case PRID_IMP_RM9000: 460 c->cputype = CPU_RM9000; 461 c->isa_level = MIPS_CPU_ISA_IV; 462 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 463 MIPS_CPU_LLSC; 464 /* 465 * Bit 29 in the info register of the RM9000 466 * indicates if the TLB has 48 or 64 entries. 467 * 468 * 29 1 => 64 entry JTLB 469 * 0 => 48 entry JTLB 470 */ 471 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 472 break; 473 case PRID_IMP_R8000: 474 c->cputype = CPU_R8000; 475 c->isa_level = MIPS_CPU_ISA_IV; 476 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 477 MIPS_CPU_FPU | MIPS_CPU_32FPR | 478 MIPS_CPU_LLSC; 479 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 480 break; 481 case PRID_IMP_R10000: 482 c->cputype = CPU_R10000; 483 c->isa_level = MIPS_CPU_ISA_IV; 484 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 485 MIPS_CPU_FPU | MIPS_CPU_32FPR | 486 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 487 MIPS_CPU_LLSC; 488 c->tlbsize = 64; 489 break; 490 case PRID_IMP_R12000: 491 c->cputype = CPU_R12000; 492 c->isa_level = MIPS_CPU_ISA_IV; 493 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 494 MIPS_CPU_FPU | MIPS_CPU_32FPR | 495 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 496 MIPS_CPU_LLSC; 497 c->tlbsize = 64; 498 break; 499 case PRID_IMP_R14000: 500 c->cputype = CPU_R14000; 501 c->isa_level = MIPS_CPU_ISA_IV; 502 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 503 MIPS_CPU_FPU | MIPS_CPU_32FPR | 504 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 505 MIPS_CPU_LLSC; 506 c->tlbsize = 64; 507 break; 508 case PRID_IMP_LOONGSON2: 509 c->cputype = CPU_LOONGSON2; 510 c->isa_level = MIPS_CPU_ISA_III; 511 c->options = R4K_OPTS | 512 MIPS_CPU_FPU | MIPS_CPU_LLSC | 513 MIPS_CPU_32FPR; 514 c->tlbsize = 64; 515 break; 516 } 517 } 518 519 static char unknown_isa[] __initdata = KERN_ERR \ 520 "Unsupported ISA type, c0.config0: %d."; 521 522 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 523 { 524 unsigned int config0; 525 int isa; 526 527 config0 = read_c0_config(); 528 529 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 530 c->options |= MIPS_CPU_TLB; 531 isa = (config0 & MIPS_CONF_AT) >> 13; 532 switch (isa) { 533 case 0: 534 switch ((config0 & MIPS_CONF_AR) >> 10) { 535 case 0: 536 c->isa_level = MIPS_CPU_ISA_M32R1; 537 break; 538 case 1: 539 c->isa_level = MIPS_CPU_ISA_M32R2; 540 break; 541 default: 542 goto unknown; 543 } 544 break; 545 case 2: 546 switch ((config0 & MIPS_CONF_AR) >> 10) { 547 case 0: 548 c->isa_level = MIPS_CPU_ISA_M64R1; 549 break; 550 case 1: 551 c->isa_level = MIPS_CPU_ISA_M64R2; 552 break; 553 default: 554 goto unknown; 555 } 556 break; 557 default: 558 goto unknown; 559 } 560 561 return config0 & MIPS_CONF_M; 562 563 unknown: 564 panic(unknown_isa, config0); 565 } 566 567 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 568 { 569 unsigned int config1; 570 571 config1 = read_c0_config1(); 572 573 if (config1 & MIPS_CONF1_MD) 574 c->ases |= MIPS_ASE_MDMX; 575 if (config1 & MIPS_CONF1_WR) 576 c->options |= MIPS_CPU_WATCH; 577 if (config1 & MIPS_CONF1_CA) 578 c->ases |= MIPS_ASE_MIPS16; 579 if (config1 & MIPS_CONF1_EP) 580 c->options |= MIPS_CPU_EJTAG; 581 if (config1 & MIPS_CONF1_FP) { 582 c->options |= MIPS_CPU_FPU; 583 c->options |= MIPS_CPU_32FPR; 584 } 585 if (cpu_has_tlb) 586 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 587 588 return config1 & MIPS_CONF_M; 589 } 590 591 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 592 { 593 unsigned int config2; 594 595 config2 = read_c0_config2(); 596 597 if (config2 & MIPS_CONF2_SL) 598 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 599 600 return config2 & MIPS_CONF_M; 601 } 602 603 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 604 { 605 unsigned int config3; 606 607 config3 = read_c0_config3(); 608 609 if (config3 & MIPS_CONF3_SM) 610 c->ases |= MIPS_ASE_SMARTMIPS; 611 if (config3 & MIPS_CONF3_DSP) 612 c->ases |= MIPS_ASE_DSP; 613 if (config3 & MIPS_CONF3_VINT) 614 c->options |= MIPS_CPU_VINT; 615 if (config3 & MIPS_CONF3_VEIC) 616 c->options |= MIPS_CPU_VEIC; 617 if (config3 & MIPS_CONF3_MT) 618 c->ases |= MIPS_ASE_MIPSMT; 619 if (config3 & MIPS_CONF3_ULRI) 620 c->options |= MIPS_CPU_ULRI; 621 622 return config3 & MIPS_CONF_M; 623 } 624 625 static void __init decode_configs(struct cpuinfo_mips *c) 626 { 627 /* MIPS32 or MIPS64 compliant CPU. */ 628 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 629 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 630 631 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 632 633 /* Read Config registers. */ 634 if (!decode_config0(c)) 635 return; /* actually worth a panic() */ 636 if (!decode_config1(c)) 637 return; 638 if (!decode_config2(c)) 639 return; 640 if (!decode_config3(c)) 641 return; 642 } 643 644 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 645 { 646 decode_configs(c); 647 switch (c->processor_id & 0xff00) { 648 case PRID_IMP_4KC: 649 c->cputype = CPU_4KC; 650 break; 651 case PRID_IMP_4KEC: 652 c->cputype = CPU_4KEC; 653 break; 654 case PRID_IMP_4KECR2: 655 c->cputype = CPU_4KEC; 656 break; 657 case PRID_IMP_4KSC: 658 case PRID_IMP_4KSD: 659 c->cputype = CPU_4KSC; 660 break; 661 case PRID_IMP_5KC: 662 c->cputype = CPU_5KC; 663 break; 664 case PRID_IMP_20KC: 665 c->cputype = CPU_20KC; 666 break; 667 case PRID_IMP_24K: 668 case PRID_IMP_24KE: 669 c->cputype = CPU_24K; 670 break; 671 case PRID_IMP_25KF: 672 c->cputype = CPU_25KF; 673 break; 674 case PRID_IMP_34K: 675 c->cputype = CPU_34K; 676 break; 677 case PRID_IMP_74K: 678 c->cputype = CPU_74K; 679 break; 680 } 681 } 682 683 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 684 { 685 decode_configs(c); 686 switch (c->processor_id & 0xff00) { 687 case PRID_IMP_AU1_REV1: 688 case PRID_IMP_AU1_REV2: 689 switch ((c->processor_id >> 24) & 0xff) { 690 case 0: 691 c->cputype = CPU_AU1000; 692 break; 693 case 1: 694 c->cputype = CPU_AU1500; 695 break; 696 case 2: 697 c->cputype = CPU_AU1100; 698 break; 699 case 3: 700 c->cputype = CPU_AU1550; 701 break; 702 case 4: 703 c->cputype = CPU_AU1200; 704 break; 705 default: 706 panic("Unknown Au Core!"); 707 break; 708 } 709 break; 710 } 711 } 712 713 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 714 { 715 decode_configs(c); 716 717 /* 718 * For historical reasons the SB1 comes with it's own variant of 719 * cache code which eventually will be folded into c-r4k.c. Until 720 * then we pretend it's got it's own cache architecture. 721 */ 722 c->options &= ~MIPS_CPU_4K_CACHE; 723 c->options |= MIPS_CPU_SB1_CACHE; 724 725 switch (c->processor_id & 0xff00) { 726 case PRID_IMP_SB1: 727 c->cputype = CPU_SB1; 728 /* FPU in pass1 is known to have issues. */ 729 if ((c->processor_id & 0xff) < 0x02) 730 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 731 break; 732 case PRID_IMP_SB1A: 733 c->cputype = CPU_SB1A; 734 break; 735 } 736 } 737 738 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 739 { 740 decode_configs(c); 741 switch (c->processor_id & 0xff00) { 742 case PRID_IMP_SR71000: 743 c->cputype = CPU_SR71000; 744 c->scache.ways = 8; 745 c->tlbsize = 64; 746 break; 747 } 748 } 749 750 static inline void cpu_probe_philips(struct cpuinfo_mips *c) 751 { 752 decode_configs(c); 753 switch (c->processor_id & 0xff00) { 754 case PRID_IMP_PR4450: 755 c->cputype = CPU_PR4450; 756 c->isa_level = MIPS_CPU_ISA_M32R1; 757 break; 758 default: 759 panic("Unknown Philips Core!"); /* REVISIT: die? */ 760 break; 761 } 762 } 763 764 765 __init void cpu_probe(void) 766 { 767 struct cpuinfo_mips *c = ¤t_cpu_data; 768 769 c->processor_id = PRID_IMP_UNKNOWN; 770 c->fpu_id = FPIR_IMP_NONE; 771 c->cputype = CPU_UNKNOWN; 772 773 c->processor_id = read_c0_prid(); 774 switch (c->processor_id & 0xff0000) { 775 case PRID_COMP_LEGACY: 776 cpu_probe_legacy(c); 777 break; 778 case PRID_COMP_MIPS: 779 cpu_probe_mips(c); 780 break; 781 case PRID_COMP_ALCHEMY: 782 cpu_probe_alchemy(c); 783 break; 784 case PRID_COMP_SIBYTE: 785 cpu_probe_sibyte(c); 786 break; 787 case PRID_COMP_SANDCRAFT: 788 cpu_probe_sandcraft(c); 789 break; 790 case PRID_COMP_PHILIPS: 791 cpu_probe_philips(c); 792 break; 793 default: 794 c->cputype = CPU_UNKNOWN; 795 } 796 if (c->options & MIPS_CPU_FPU) { 797 c->fpu_id = cpu_get_fpu_id(); 798 799 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 800 c->isa_level == MIPS_CPU_ISA_M32R2 || 801 c->isa_level == MIPS_CPU_ISA_M64R1 || 802 c->isa_level == MIPS_CPU_ISA_M64R2) { 803 if (c->fpu_id & MIPS_FPIR_3D) 804 c->ases |= MIPS_ASE_MIPS3D; 805 } 806 } 807 } 808 809 __init void cpu_report(void) 810 { 811 struct cpuinfo_mips *c = ¤t_cpu_data; 812 813 printk("CPU revision is: %08x\n", c->processor_id); 814 if (c->options & MIPS_CPU_FPU) 815 printk("FPU revision is: %08x\n", c->fpu_id); 816 } 817