1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/fpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/spram.h> 28 #include <asm/uaccess.h> 29 30 /* 31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 32 * the implementation of the "wait" feature differs between CPU families. This 33 * points to the function that implements CPU specific wait. 34 * The wait instruction stops the pipeline and reduces the power consumption of 35 * the CPU very much. 36 */ 37 void (*cpu_wait)(void); 38 EXPORT_SYMBOL(cpu_wait); 39 40 static void r3081_wait(void) 41 { 42 unsigned long cfg = read_c0_conf(); 43 write_c0_conf(cfg | R30XX_CONF_HALT); 44 } 45 46 static void r39xx_wait(void) 47 { 48 local_irq_disable(); 49 if (!need_resched()) 50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 51 local_irq_enable(); 52 } 53 54 extern void r4k_wait(void); 55 56 /* 57 * This variant is preferable as it allows testing need_resched and going to 58 * sleep depending on the outcome atomically. Unfortunately the "It is 59 * implementation-dependent whether the pipeline restarts when a non-enabled 60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 61 * using this version a gamble. 62 */ 63 void r4k_wait_irqoff(void) 64 { 65 local_irq_disable(); 66 if (!need_resched()) 67 __asm__(" .set push \n" 68 " .set mips3 \n" 69 " wait \n" 70 " .set pop \n"); 71 local_irq_enable(); 72 __asm__(" .globl __pastwait \n" 73 "__pastwait: \n"); 74 } 75 76 /* 77 * The RM7000 variant has to handle erratum 38. The workaround is to not 78 * have any pending stores when the WAIT instruction is executed. 79 */ 80 static void rm7k_wait_irqoff(void) 81 { 82 local_irq_disable(); 83 if (!need_resched()) 84 __asm__( 85 " .set push \n" 86 " .set mips3 \n" 87 " .set noat \n" 88 " mfc0 $1, $12 \n" 89 " sync \n" 90 " mtc0 $1, $12 # stalls until W stage \n" 91 " wait \n" 92 " mtc0 $1, $12 # stalls until W stage \n" 93 " .set pop \n"); 94 local_irq_enable(); 95 } 96 97 /* 98 * The Au1xxx wait is available only if using 32khz counter or 99 * external timer source, but specifically not CP0 Counter. 100 * alchemy/common/time.c may override cpu_wait! 101 */ 102 static void au1k_wait(void) 103 { 104 __asm__(" .set mips3 \n" 105 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 32(%0) \n" 107 " sync \n" 108 " nop \n" 109 " wait \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " nop \n" 114 " .set mips0 \n" 115 : : "r" (au1k_wait)); 116 } 117 118 static int __initdata nowait; 119 120 static int __init wait_disable(char *s) 121 { 122 nowait = 1; 123 124 return 1; 125 } 126 127 __setup("nowait", wait_disable); 128 129 static int __cpuinitdata mips_fpu_disabled; 130 131 static int __init fpu_disable(char *s) 132 { 133 cpu_data[0].options &= ~MIPS_CPU_FPU; 134 mips_fpu_disabled = 1; 135 136 return 1; 137 } 138 139 __setup("nofpu", fpu_disable); 140 141 int __cpuinitdata mips_dsp_disabled; 142 143 static int __init dsp_disable(char *s) 144 { 145 cpu_data[0].ases &= ~MIPS_ASE_DSP; 146 mips_dsp_disabled = 1; 147 148 return 1; 149 } 150 151 __setup("nodsp", dsp_disable); 152 153 void __init check_wait(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 if (nowait) { 158 printk("Wait instruction disabled.\n"); 159 return; 160 } 161 162 switch (c->cputype) { 163 case CPU_R3081: 164 case CPU_R3081E: 165 cpu_wait = r3081_wait; 166 break; 167 case CPU_TX3927: 168 cpu_wait = r39xx_wait; 169 break; 170 case CPU_R4200: 171 /* case CPU_R4300: */ 172 case CPU_R4600: 173 case CPU_R4640: 174 case CPU_R4650: 175 case CPU_R4700: 176 case CPU_R5000: 177 case CPU_R5500: 178 case CPU_NEVADA: 179 case CPU_4KC: 180 case CPU_4KEC: 181 case CPU_4KSC: 182 case CPU_5KC: 183 case CPU_25KF: 184 case CPU_PR4450: 185 case CPU_BMIPS3300: 186 case CPU_BMIPS4350: 187 case CPU_BMIPS4380: 188 case CPU_BMIPS5000: 189 case CPU_CAVIUM_OCTEON: 190 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON2: 192 case CPU_JZRISC: 193 case CPU_XLR: 194 case CPU_XLP: 195 cpu_wait = r4k_wait; 196 break; 197 198 case CPU_RM7000: 199 cpu_wait = rm7k_wait_irqoff; 200 break; 201 202 case CPU_24K: 203 case CPU_34K: 204 case CPU_1004K: 205 cpu_wait = r4k_wait; 206 if (read_c0_config7() & MIPS_CONF7_WII) 207 cpu_wait = r4k_wait_irqoff; 208 break; 209 210 case CPU_74K: 211 cpu_wait = r4k_wait; 212 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 213 cpu_wait = r4k_wait_irqoff; 214 break; 215 216 case CPU_TX49XX: 217 cpu_wait = r4k_wait_irqoff; 218 break; 219 case CPU_ALCHEMY: 220 cpu_wait = au1k_wait; 221 break; 222 case CPU_20KC: 223 /* 224 * WAIT on Rev1.0 has E1, E2, E3 and E16. 225 * WAIT on Rev2.0 and Rev3.0 has E16. 226 * Rev3.1 WAIT is nop, why bother 227 */ 228 if ((c->processor_id & 0xff) <= 0x64) 229 break; 230 231 /* 232 * Another rev is incremeting c0_count at a reduced clock 233 * rate while in WAIT mode. So we basically have the choice 234 * between using the cp0 timer as clocksource or avoiding 235 * the WAIT instruction. Until more details are known, 236 * disable the use of WAIT for 20Kc entirely. 237 cpu_wait = r4k_wait; 238 */ 239 break; 240 case CPU_RM9000: 241 if ((c->processor_id & 0x00ff) >= 0x40) 242 cpu_wait = r4k_wait; 243 break; 244 default: 245 break; 246 } 247 } 248 249 static inline void check_errata(void) 250 { 251 struct cpuinfo_mips *c = ¤t_cpu_data; 252 253 switch (c->cputype) { 254 case CPU_34K: 255 /* 256 * Erratum "RPS May Cause Incorrect Instruction Execution" 257 * This code only handles VPE0, any SMP/SMTC/RTOS code 258 * making use of VPE1 will be responsable for that VPE. 259 */ 260 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 261 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 262 break; 263 default: 264 break; 265 } 266 } 267 268 void __init check_bugs32(void) 269 { 270 check_errata(); 271 } 272 273 /* 274 * Probe whether cpu has config register by trying to play with 275 * alternate cache bit and see whether it matters. 276 * It's used by cpu_probe to distinguish between R3000A and R3081. 277 */ 278 static inline int cpu_has_confreg(void) 279 { 280 #ifdef CONFIG_CPU_R3000 281 extern unsigned long r3k_cache_size(unsigned long); 282 unsigned long size1, size2; 283 unsigned long cfg = read_c0_conf(); 284 285 size1 = r3k_cache_size(ST0_ISC); 286 write_c0_conf(cfg ^ R30XX_CONF_AC); 287 size2 = r3k_cache_size(ST0_ISC); 288 write_c0_conf(cfg); 289 return size1 != size2; 290 #else 291 return 0; 292 #endif 293 } 294 295 static inline void set_elf_platform(int cpu, const char *plat) 296 { 297 if (cpu == 0) 298 __elf_platform = plat; 299 } 300 301 /* 302 * Get the FPU Implementation/Revision. 303 */ 304 static inline unsigned long cpu_get_fpu_id(void) 305 { 306 unsigned long tmp, fpu_id; 307 308 tmp = read_c0_status(); 309 __enable_fpu(); 310 fpu_id = read_32bit_cp1_register(CP1_REVISION); 311 write_c0_status(tmp); 312 return fpu_id; 313 } 314 315 /* 316 * Check the CPU has an FPU the official way. 317 */ 318 static inline int __cpu_has_fpu(void) 319 { 320 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 321 } 322 323 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 324 { 325 #ifdef __NEED_VMBITS_PROBE 326 write_c0_entryhi(0x3fffffffffffe000ULL); 327 back_to_back_c0_hazard(); 328 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 329 #endif 330 } 331 332 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 333 | MIPS_CPU_COUNTER) 334 335 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 336 { 337 switch (c->processor_id & 0xff00) { 338 case PRID_IMP_R2000: 339 c->cputype = CPU_R2000; 340 __cpu_name[cpu] = "R2000"; 341 c->isa_level = MIPS_CPU_ISA_I; 342 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 343 MIPS_CPU_NOFPUEX; 344 if (__cpu_has_fpu()) 345 c->options |= MIPS_CPU_FPU; 346 c->tlbsize = 64; 347 break; 348 case PRID_IMP_R3000: 349 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 350 if (cpu_has_confreg()) { 351 c->cputype = CPU_R3081E; 352 __cpu_name[cpu] = "R3081"; 353 } else { 354 c->cputype = CPU_R3000A; 355 __cpu_name[cpu] = "R3000A"; 356 } 357 break; 358 } else { 359 c->cputype = CPU_R3000; 360 __cpu_name[cpu] = "R3000"; 361 } 362 c->isa_level = MIPS_CPU_ISA_I; 363 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 364 MIPS_CPU_NOFPUEX; 365 if (__cpu_has_fpu()) 366 c->options |= MIPS_CPU_FPU; 367 c->tlbsize = 64; 368 break; 369 case PRID_IMP_R4000: 370 if (read_c0_config() & CONF_SC) { 371 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 372 c->cputype = CPU_R4400PC; 373 __cpu_name[cpu] = "R4400PC"; 374 } else { 375 c->cputype = CPU_R4000PC; 376 __cpu_name[cpu] = "R4000PC"; 377 } 378 } else { 379 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 380 c->cputype = CPU_R4400SC; 381 __cpu_name[cpu] = "R4400SC"; 382 } else { 383 c->cputype = CPU_R4000SC; 384 __cpu_name[cpu] = "R4000SC"; 385 } 386 } 387 388 c->isa_level = MIPS_CPU_ISA_III; 389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 390 MIPS_CPU_WATCH | MIPS_CPU_VCE | 391 MIPS_CPU_LLSC; 392 c->tlbsize = 48; 393 break; 394 case PRID_IMP_VR41XX: 395 switch (c->processor_id & 0xf0) { 396 case PRID_REV_VR4111: 397 c->cputype = CPU_VR4111; 398 __cpu_name[cpu] = "NEC VR4111"; 399 break; 400 case PRID_REV_VR4121: 401 c->cputype = CPU_VR4121; 402 __cpu_name[cpu] = "NEC VR4121"; 403 break; 404 case PRID_REV_VR4122: 405 if ((c->processor_id & 0xf) < 0x3) { 406 c->cputype = CPU_VR4122; 407 __cpu_name[cpu] = "NEC VR4122"; 408 } else { 409 c->cputype = CPU_VR4181A; 410 __cpu_name[cpu] = "NEC VR4181A"; 411 } 412 break; 413 case PRID_REV_VR4130: 414 if ((c->processor_id & 0xf) < 0x4) { 415 c->cputype = CPU_VR4131; 416 __cpu_name[cpu] = "NEC VR4131"; 417 } else { 418 c->cputype = CPU_VR4133; 419 __cpu_name[cpu] = "NEC VR4133"; 420 } 421 break; 422 default: 423 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 424 c->cputype = CPU_VR41XX; 425 __cpu_name[cpu] = "NEC Vr41xx"; 426 break; 427 } 428 c->isa_level = MIPS_CPU_ISA_III; 429 c->options = R4K_OPTS; 430 c->tlbsize = 32; 431 break; 432 case PRID_IMP_R4300: 433 c->cputype = CPU_R4300; 434 __cpu_name[cpu] = "R4300"; 435 c->isa_level = MIPS_CPU_ISA_III; 436 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 437 MIPS_CPU_LLSC; 438 c->tlbsize = 32; 439 break; 440 case PRID_IMP_R4600: 441 c->cputype = CPU_R4600; 442 __cpu_name[cpu] = "R4600"; 443 c->isa_level = MIPS_CPU_ISA_III; 444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 445 MIPS_CPU_LLSC; 446 c->tlbsize = 48; 447 break; 448 #if 0 449 case PRID_IMP_R4650: 450 /* 451 * This processor doesn't have an MMU, so it's not 452 * "real easy" to run Linux on it. It is left purely 453 * for documentation. Commented out because it shares 454 * it's c0_prid id number with the TX3900. 455 */ 456 c->cputype = CPU_R4650; 457 __cpu_name[cpu] = "R4650"; 458 c->isa_level = MIPS_CPU_ISA_III; 459 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 460 c->tlbsize = 48; 461 break; 462 #endif 463 case PRID_IMP_TX39: 464 c->isa_level = MIPS_CPU_ISA_I; 465 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 466 467 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 468 c->cputype = CPU_TX3927; 469 __cpu_name[cpu] = "TX3927"; 470 c->tlbsize = 64; 471 } else { 472 switch (c->processor_id & 0xff) { 473 case PRID_REV_TX3912: 474 c->cputype = CPU_TX3912; 475 __cpu_name[cpu] = "TX3912"; 476 c->tlbsize = 32; 477 break; 478 case PRID_REV_TX3922: 479 c->cputype = CPU_TX3922; 480 __cpu_name[cpu] = "TX3922"; 481 c->tlbsize = 64; 482 break; 483 } 484 } 485 break; 486 case PRID_IMP_R4700: 487 c->cputype = CPU_R4700; 488 __cpu_name[cpu] = "R4700"; 489 c->isa_level = MIPS_CPU_ISA_III; 490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 491 MIPS_CPU_LLSC; 492 c->tlbsize = 48; 493 break; 494 case PRID_IMP_TX49: 495 c->cputype = CPU_TX49XX; 496 __cpu_name[cpu] = "R49XX"; 497 c->isa_level = MIPS_CPU_ISA_III; 498 c->options = R4K_OPTS | MIPS_CPU_LLSC; 499 if (!(c->processor_id & 0x08)) 500 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 501 c->tlbsize = 48; 502 break; 503 case PRID_IMP_R5000: 504 c->cputype = CPU_R5000; 505 __cpu_name[cpu] = "R5000"; 506 c->isa_level = MIPS_CPU_ISA_IV; 507 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 508 MIPS_CPU_LLSC; 509 c->tlbsize = 48; 510 break; 511 case PRID_IMP_R5432: 512 c->cputype = CPU_R5432; 513 __cpu_name[cpu] = "R5432"; 514 c->isa_level = MIPS_CPU_ISA_IV; 515 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 516 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 517 c->tlbsize = 48; 518 break; 519 case PRID_IMP_R5500: 520 c->cputype = CPU_R5500; 521 __cpu_name[cpu] = "R5500"; 522 c->isa_level = MIPS_CPU_ISA_IV; 523 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 524 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 525 c->tlbsize = 48; 526 break; 527 case PRID_IMP_NEVADA: 528 c->cputype = CPU_NEVADA; 529 __cpu_name[cpu] = "Nevada"; 530 c->isa_level = MIPS_CPU_ISA_IV; 531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 532 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 533 c->tlbsize = 48; 534 break; 535 case PRID_IMP_R6000: 536 c->cputype = CPU_R6000; 537 __cpu_name[cpu] = "R6000"; 538 c->isa_level = MIPS_CPU_ISA_II; 539 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 540 MIPS_CPU_LLSC; 541 c->tlbsize = 32; 542 break; 543 case PRID_IMP_R6000A: 544 c->cputype = CPU_R6000A; 545 __cpu_name[cpu] = "R6000A"; 546 c->isa_level = MIPS_CPU_ISA_II; 547 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 548 MIPS_CPU_LLSC; 549 c->tlbsize = 32; 550 break; 551 case PRID_IMP_RM7000: 552 c->cputype = CPU_RM7000; 553 __cpu_name[cpu] = "RM7000"; 554 c->isa_level = MIPS_CPU_ISA_IV; 555 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 556 MIPS_CPU_LLSC; 557 /* 558 * Undocumented RM7000: Bit 29 in the info register of 559 * the RM7000 v2.0 indicates if the TLB has 48 or 64 560 * entries. 561 * 562 * 29 1 => 64 entry JTLB 563 * 0 => 48 entry JTLB 564 */ 565 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 566 break; 567 case PRID_IMP_RM9000: 568 c->cputype = CPU_RM9000; 569 __cpu_name[cpu] = "RM9000"; 570 c->isa_level = MIPS_CPU_ISA_IV; 571 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 572 MIPS_CPU_LLSC; 573 /* 574 * Bit 29 in the info register of the RM9000 575 * indicates if the TLB has 48 or 64 entries. 576 * 577 * 29 1 => 64 entry JTLB 578 * 0 => 48 entry JTLB 579 */ 580 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 581 break; 582 case PRID_IMP_R8000: 583 c->cputype = CPU_R8000; 584 __cpu_name[cpu] = "RM8000"; 585 c->isa_level = MIPS_CPU_ISA_IV; 586 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 587 MIPS_CPU_FPU | MIPS_CPU_32FPR | 588 MIPS_CPU_LLSC; 589 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 590 break; 591 case PRID_IMP_R10000: 592 c->cputype = CPU_R10000; 593 __cpu_name[cpu] = "R10000"; 594 c->isa_level = MIPS_CPU_ISA_IV; 595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 596 MIPS_CPU_FPU | MIPS_CPU_32FPR | 597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 598 MIPS_CPU_LLSC; 599 c->tlbsize = 64; 600 break; 601 case PRID_IMP_R12000: 602 c->cputype = CPU_R12000; 603 __cpu_name[cpu] = "R12000"; 604 c->isa_level = MIPS_CPU_ISA_IV; 605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 606 MIPS_CPU_FPU | MIPS_CPU_32FPR | 607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 608 MIPS_CPU_LLSC; 609 c->tlbsize = 64; 610 break; 611 case PRID_IMP_R14000: 612 c->cputype = CPU_R14000; 613 __cpu_name[cpu] = "R14000"; 614 c->isa_level = MIPS_CPU_ISA_IV; 615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 616 MIPS_CPU_FPU | MIPS_CPU_32FPR | 617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 618 MIPS_CPU_LLSC; 619 c->tlbsize = 64; 620 break; 621 case PRID_IMP_LOONGSON2: 622 c->cputype = CPU_LOONGSON2; 623 __cpu_name[cpu] = "ICT Loongson-2"; 624 625 switch (c->processor_id & PRID_REV_MASK) { 626 case PRID_REV_LOONGSON2E: 627 set_elf_platform(cpu, "loongson2e"); 628 break; 629 case PRID_REV_LOONGSON2F: 630 set_elf_platform(cpu, "loongson2f"); 631 break; 632 } 633 634 c->isa_level = MIPS_CPU_ISA_III; 635 c->options = R4K_OPTS | 636 MIPS_CPU_FPU | MIPS_CPU_LLSC | 637 MIPS_CPU_32FPR; 638 c->tlbsize = 64; 639 break; 640 } 641 } 642 643 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 644 "Unsupported ISA type, c0.config0: %d."; 645 646 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 647 { 648 unsigned int config0; 649 int isa; 650 651 config0 = read_c0_config(); 652 653 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 654 c->options |= MIPS_CPU_TLB; 655 isa = (config0 & MIPS_CONF_AT) >> 13; 656 switch (isa) { 657 case 0: 658 switch ((config0 & MIPS_CONF_AR) >> 10) { 659 case 0: 660 c->isa_level = MIPS_CPU_ISA_M32R1; 661 break; 662 case 1: 663 c->isa_level = MIPS_CPU_ISA_M32R2; 664 break; 665 default: 666 goto unknown; 667 } 668 break; 669 case 2: 670 switch ((config0 & MIPS_CONF_AR) >> 10) { 671 case 0: 672 c->isa_level = MIPS_CPU_ISA_M64R1; 673 break; 674 case 1: 675 c->isa_level = MIPS_CPU_ISA_M64R2; 676 break; 677 default: 678 goto unknown; 679 } 680 break; 681 default: 682 goto unknown; 683 } 684 685 return config0 & MIPS_CONF_M; 686 687 unknown: 688 panic(unknown_isa, config0); 689 } 690 691 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 692 { 693 unsigned int config1; 694 695 config1 = read_c0_config1(); 696 697 if (config1 & MIPS_CONF1_MD) 698 c->ases |= MIPS_ASE_MDMX; 699 if (config1 & MIPS_CONF1_WR) 700 c->options |= MIPS_CPU_WATCH; 701 if (config1 & MIPS_CONF1_CA) 702 c->ases |= MIPS_ASE_MIPS16; 703 if (config1 & MIPS_CONF1_EP) 704 c->options |= MIPS_CPU_EJTAG; 705 if (config1 & MIPS_CONF1_FP) { 706 c->options |= MIPS_CPU_FPU; 707 c->options |= MIPS_CPU_32FPR; 708 } 709 if (cpu_has_tlb) 710 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 711 712 return config1 & MIPS_CONF_M; 713 } 714 715 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 716 { 717 unsigned int config2; 718 719 config2 = read_c0_config2(); 720 721 if (config2 & MIPS_CONF2_SL) 722 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 723 724 return config2 & MIPS_CONF_M; 725 } 726 727 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 728 { 729 unsigned int config3; 730 731 config3 = read_c0_config3(); 732 733 if (config3 & MIPS_CONF3_SM) 734 c->ases |= MIPS_ASE_SMARTMIPS; 735 if (config3 & MIPS_CONF3_DSP) 736 c->ases |= MIPS_ASE_DSP; 737 if (config3 & MIPS_CONF3_VINT) 738 c->options |= MIPS_CPU_VINT; 739 if (config3 & MIPS_CONF3_VEIC) 740 c->options |= MIPS_CPU_VEIC; 741 if (config3 & MIPS_CONF3_MT) 742 c->ases |= MIPS_ASE_MIPSMT; 743 if (config3 & MIPS_CONF3_ULRI) 744 c->options |= MIPS_CPU_ULRI; 745 746 return config3 & MIPS_CONF_M; 747 } 748 749 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 750 { 751 unsigned int config4; 752 753 config4 = read_c0_config4(); 754 755 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 756 && cpu_has_tlb) 757 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 758 759 c->kscratch_mask = (config4 >> 16) & 0xff; 760 761 return config4 & MIPS_CONF_M; 762 } 763 764 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 765 { 766 int ok; 767 768 /* MIPS32 or MIPS64 compliant CPU. */ 769 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 770 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 771 772 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 773 774 ok = decode_config0(c); /* Read Config registers. */ 775 BUG_ON(!ok); /* Arch spec violation! */ 776 if (ok) 777 ok = decode_config1(c); 778 if (ok) 779 ok = decode_config2(c); 780 if (ok) 781 ok = decode_config3(c); 782 if (ok) 783 ok = decode_config4(c); 784 785 mips_probe_watch_registers(c); 786 787 if (cpu_has_mips_r2) 788 c->core = read_c0_ebase() & 0x3ff; 789 } 790 791 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 792 { 793 decode_configs(c); 794 switch (c->processor_id & 0xff00) { 795 case PRID_IMP_4KC: 796 c->cputype = CPU_4KC; 797 __cpu_name[cpu] = "MIPS 4Kc"; 798 break; 799 case PRID_IMP_4KEC: 800 case PRID_IMP_4KECR2: 801 c->cputype = CPU_4KEC; 802 __cpu_name[cpu] = "MIPS 4KEc"; 803 break; 804 case PRID_IMP_4KSC: 805 case PRID_IMP_4KSD: 806 c->cputype = CPU_4KSC; 807 __cpu_name[cpu] = "MIPS 4KSc"; 808 break; 809 case PRID_IMP_5KC: 810 c->cputype = CPU_5KC; 811 __cpu_name[cpu] = "MIPS 5Kc"; 812 break; 813 case PRID_IMP_20KC: 814 c->cputype = CPU_20KC; 815 __cpu_name[cpu] = "MIPS 20Kc"; 816 break; 817 case PRID_IMP_24K: 818 case PRID_IMP_24KE: 819 c->cputype = CPU_24K; 820 __cpu_name[cpu] = "MIPS 24Kc"; 821 break; 822 case PRID_IMP_25KF: 823 c->cputype = CPU_25KF; 824 __cpu_name[cpu] = "MIPS 25Kc"; 825 break; 826 case PRID_IMP_34K: 827 c->cputype = CPU_34K; 828 __cpu_name[cpu] = "MIPS 34Kc"; 829 break; 830 case PRID_IMP_74K: 831 c->cputype = CPU_74K; 832 __cpu_name[cpu] = "MIPS 74Kc"; 833 break; 834 case PRID_IMP_1004K: 835 c->cputype = CPU_1004K; 836 __cpu_name[cpu] = "MIPS 1004Kc"; 837 break; 838 } 839 840 spram_config(); 841 } 842 843 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 844 { 845 decode_configs(c); 846 switch (c->processor_id & 0xff00) { 847 case PRID_IMP_AU1_REV1: 848 case PRID_IMP_AU1_REV2: 849 c->cputype = CPU_ALCHEMY; 850 switch ((c->processor_id >> 24) & 0xff) { 851 case 0: 852 __cpu_name[cpu] = "Au1000"; 853 break; 854 case 1: 855 __cpu_name[cpu] = "Au1500"; 856 break; 857 case 2: 858 __cpu_name[cpu] = "Au1100"; 859 break; 860 case 3: 861 __cpu_name[cpu] = "Au1550"; 862 break; 863 case 4: 864 __cpu_name[cpu] = "Au1200"; 865 if ((c->processor_id & 0xff) == 2) 866 __cpu_name[cpu] = "Au1250"; 867 break; 868 case 5: 869 __cpu_name[cpu] = "Au1210"; 870 break; 871 default: 872 __cpu_name[cpu] = "Au1xxx"; 873 break; 874 } 875 break; 876 } 877 } 878 879 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 880 { 881 decode_configs(c); 882 883 switch (c->processor_id & 0xff00) { 884 case PRID_IMP_SB1: 885 c->cputype = CPU_SB1; 886 __cpu_name[cpu] = "SiByte SB1"; 887 /* FPU in pass1 is known to have issues. */ 888 if ((c->processor_id & 0xff) < 0x02) 889 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 890 break; 891 case PRID_IMP_SB1A: 892 c->cputype = CPU_SB1A; 893 __cpu_name[cpu] = "SiByte SB1A"; 894 break; 895 } 896 } 897 898 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 899 { 900 decode_configs(c); 901 switch (c->processor_id & 0xff00) { 902 case PRID_IMP_SR71000: 903 c->cputype = CPU_SR71000; 904 __cpu_name[cpu] = "Sandcraft SR71000"; 905 c->scache.ways = 8; 906 c->tlbsize = 64; 907 break; 908 } 909 } 910 911 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 912 { 913 decode_configs(c); 914 switch (c->processor_id & 0xff00) { 915 case PRID_IMP_PR4450: 916 c->cputype = CPU_PR4450; 917 __cpu_name[cpu] = "Philips PR4450"; 918 c->isa_level = MIPS_CPU_ISA_M32R1; 919 break; 920 } 921 } 922 923 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 924 { 925 decode_configs(c); 926 switch (c->processor_id & 0xff00) { 927 case PRID_IMP_BMIPS32_REV4: 928 case PRID_IMP_BMIPS32_REV8: 929 c->cputype = CPU_BMIPS32; 930 __cpu_name[cpu] = "Broadcom BMIPS32"; 931 set_elf_platform(cpu, "bmips32"); 932 break; 933 case PRID_IMP_BMIPS3300: 934 case PRID_IMP_BMIPS3300_ALT: 935 case PRID_IMP_BMIPS3300_BUG: 936 c->cputype = CPU_BMIPS3300; 937 __cpu_name[cpu] = "Broadcom BMIPS3300"; 938 set_elf_platform(cpu, "bmips3300"); 939 break; 940 case PRID_IMP_BMIPS43XX: { 941 int rev = c->processor_id & 0xff; 942 943 if (rev >= PRID_REV_BMIPS4380_LO && 944 rev <= PRID_REV_BMIPS4380_HI) { 945 c->cputype = CPU_BMIPS4380; 946 __cpu_name[cpu] = "Broadcom BMIPS4380"; 947 set_elf_platform(cpu, "bmips4380"); 948 } else { 949 c->cputype = CPU_BMIPS4350; 950 __cpu_name[cpu] = "Broadcom BMIPS4350"; 951 set_elf_platform(cpu, "bmips4350"); 952 } 953 break; 954 } 955 case PRID_IMP_BMIPS5000: 956 c->cputype = CPU_BMIPS5000; 957 __cpu_name[cpu] = "Broadcom BMIPS5000"; 958 set_elf_platform(cpu, "bmips5000"); 959 c->options |= MIPS_CPU_ULRI; 960 break; 961 } 962 } 963 964 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 965 { 966 decode_configs(c); 967 switch (c->processor_id & 0xff00) { 968 case PRID_IMP_CAVIUM_CN38XX: 969 case PRID_IMP_CAVIUM_CN31XX: 970 case PRID_IMP_CAVIUM_CN30XX: 971 c->cputype = CPU_CAVIUM_OCTEON; 972 __cpu_name[cpu] = "Cavium Octeon"; 973 goto platform; 974 case PRID_IMP_CAVIUM_CN58XX: 975 case PRID_IMP_CAVIUM_CN56XX: 976 case PRID_IMP_CAVIUM_CN50XX: 977 case PRID_IMP_CAVIUM_CN52XX: 978 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 979 __cpu_name[cpu] = "Cavium Octeon+"; 980 platform: 981 set_elf_platform(cpu, "octeon"); 982 break; 983 case PRID_IMP_CAVIUM_CN61XX: 984 case PRID_IMP_CAVIUM_CN63XX: 985 case PRID_IMP_CAVIUM_CN66XX: 986 case PRID_IMP_CAVIUM_CN68XX: 987 c->cputype = CPU_CAVIUM_OCTEON2; 988 __cpu_name[cpu] = "Cavium Octeon II"; 989 set_elf_platform(cpu, "octeon2"); 990 break; 991 default: 992 printk(KERN_INFO "Unknown Octeon chip!\n"); 993 c->cputype = CPU_UNKNOWN; 994 break; 995 } 996 } 997 998 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 999 { 1000 decode_configs(c); 1001 /* JZRISC does not implement the CP0 counter. */ 1002 c->options &= ~MIPS_CPU_COUNTER; 1003 switch (c->processor_id & 0xff00) { 1004 case PRID_IMP_JZRISC: 1005 c->cputype = CPU_JZRISC; 1006 __cpu_name[cpu] = "Ingenic JZRISC"; 1007 break; 1008 default: 1009 panic("Unknown Ingenic Processor ID!"); 1010 break; 1011 } 1012 } 1013 1014 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1015 { 1016 decode_configs(c); 1017 1018 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { 1019 c->cputype = CPU_ALCHEMY; 1020 __cpu_name[cpu] = "Au1300"; 1021 /* following stuff is not for Alchemy */ 1022 return; 1023 } 1024 1025 c->options = (MIPS_CPU_TLB | 1026 MIPS_CPU_4KEX | 1027 MIPS_CPU_COUNTER | 1028 MIPS_CPU_DIVEC | 1029 MIPS_CPU_WATCH | 1030 MIPS_CPU_EJTAG | 1031 MIPS_CPU_LLSC); 1032 1033 switch (c->processor_id & 0xff00) { 1034 case PRID_IMP_NETLOGIC_XLP8XX: 1035 case PRID_IMP_NETLOGIC_XLP3XX: 1036 c->cputype = CPU_XLP; 1037 __cpu_name[cpu] = "Netlogic XLP"; 1038 break; 1039 1040 case PRID_IMP_NETLOGIC_XLR732: 1041 case PRID_IMP_NETLOGIC_XLR716: 1042 case PRID_IMP_NETLOGIC_XLR532: 1043 case PRID_IMP_NETLOGIC_XLR308: 1044 case PRID_IMP_NETLOGIC_XLR532C: 1045 case PRID_IMP_NETLOGIC_XLR516C: 1046 case PRID_IMP_NETLOGIC_XLR508C: 1047 case PRID_IMP_NETLOGIC_XLR308C: 1048 c->cputype = CPU_XLR; 1049 __cpu_name[cpu] = "Netlogic XLR"; 1050 break; 1051 1052 case PRID_IMP_NETLOGIC_XLS608: 1053 case PRID_IMP_NETLOGIC_XLS408: 1054 case PRID_IMP_NETLOGIC_XLS404: 1055 case PRID_IMP_NETLOGIC_XLS208: 1056 case PRID_IMP_NETLOGIC_XLS204: 1057 case PRID_IMP_NETLOGIC_XLS108: 1058 case PRID_IMP_NETLOGIC_XLS104: 1059 case PRID_IMP_NETLOGIC_XLS616B: 1060 case PRID_IMP_NETLOGIC_XLS608B: 1061 case PRID_IMP_NETLOGIC_XLS416B: 1062 case PRID_IMP_NETLOGIC_XLS412B: 1063 case PRID_IMP_NETLOGIC_XLS408B: 1064 case PRID_IMP_NETLOGIC_XLS404B: 1065 c->cputype = CPU_XLR; 1066 __cpu_name[cpu] = "Netlogic XLS"; 1067 break; 1068 1069 default: 1070 pr_info("Unknown Netlogic chip id [%02x]!\n", 1071 c->processor_id); 1072 c->cputype = CPU_XLR; 1073 break; 1074 } 1075 1076 if (c->cputype == CPU_XLP) { 1077 c->isa_level = MIPS_CPU_ISA_M64R2; 1078 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1079 /* This will be updated again after all threads are woken up */ 1080 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1081 } else { 1082 c->isa_level = MIPS_CPU_ISA_M64R1; 1083 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1084 } 1085 } 1086 1087 #ifdef CONFIG_64BIT 1088 /* For use by uaccess.h */ 1089 u64 __ua_limit; 1090 EXPORT_SYMBOL(__ua_limit); 1091 #endif 1092 1093 const char *__cpu_name[NR_CPUS]; 1094 const char *__elf_platform; 1095 1096 __cpuinit void cpu_probe(void) 1097 { 1098 struct cpuinfo_mips *c = ¤t_cpu_data; 1099 unsigned int cpu = smp_processor_id(); 1100 1101 c->processor_id = PRID_IMP_UNKNOWN; 1102 c->fpu_id = FPIR_IMP_NONE; 1103 c->cputype = CPU_UNKNOWN; 1104 1105 c->processor_id = read_c0_prid(); 1106 switch (c->processor_id & 0xff0000) { 1107 case PRID_COMP_LEGACY: 1108 cpu_probe_legacy(c, cpu); 1109 break; 1110 case PRID_COMP_MIPS: 1111 cpu_probe_mips(c, cpu); 1112 break; 1113 case PRID_COMP_ALCHEMY: 1114 cpu_probe_alchemy(c, cpu); 1115 break; 1116 case PRID_COMP_SIBYTE: 1117 cpu_probe_sibyte(c, cpu); 1118 break; 1119 case PRID_COMP_BROADCOM: 1120 cpu_probe_broadcom(c, cpu); 1121 break; 1122 case PRID_COMP_SANDCRAFT: 1123 cpu_probe_sandcraft(c, cpu); 1124 break; 1125 case PRID_COMP_NXP: 1126 cpu_probe_nxp(c, cpu); 1127 break; 1128 case PRID_COMP_CAVIUM: 1129 cpu_probe_cavium(c, cpu); 1130 break; 1131 case PRID_COMP_INGENIC: 1132 cpu_probe_ingenic(c, cpu); 1133 break; 1134 case PRID_COMP_NETLOGIC: 1135 cpu_probe_netlogic(c, cpu); 1136 break; 1137 } 1138 1139 BUG_ON(!__cpu_name[cpu]); 1140 BUG_ON(c->cputype == CPU_UNKNOWN); 1141 1142 /* 1143 * Platform code can force the cpu type to optimize code 1144 * generation. In that case be sure the cpu type is correctly 1145 * manually setup otherwise it could trigger some nasty bugs. 1146 */ 1147 BUG_ON(current_cpu_type() != c->cputype); 1148 1149 if (mips_fpu_disabled) 1150 c->options &= ~MIPS_CPU_FPU; 1151 1152 if (mips_dsp_disabled) 1153 c->ases &= ~MIPS_ASE_DSP; 1154 1155 if (c->options & MIPS_CPU_FPU) { 1156 c->fpu_id = cpu_get_fpu_id(); 1157 1158 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1159 c->isa_level == MIPS_CPU_ISA_M32R2 || 1160 c->isa_level == MIPS_CPU_ISA_M64R1 || 1161 c->isa_level == MIPS_CPU_ISA_M64R2) { 1162 if (c->fpu_id & MIPS_FPIR_3D) 1163 c->ases |= MIPS_ASE_MIPS3D; 1164 } 1165 } 1166 1167 if (cpu_has_mips_r2) 1168 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1169 else 1170 c->srsets = 1; 1171 1172 cpu_probe_vmbits(c); 1173 1174 #ifdef CONFIG_64BIT 1175 if (cpu == 0) 1176 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1177 #endif 1178 } 1179 1180 __cpuinit void cpu_report(void) 1181 { 1182 struct cpuinfo_mips *c = ¤t_cpu_data; 1183 1184 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1185 c->processor_id, cpu_name_string()); 1186 if (c->options & MIPS_CPU_FPU) 1187 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1188 } 1189