1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/mipsmtregs.h> 27 #include <asm/msa.h> 28 #include <asm/watch.h> 29 #include <asm/elf.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/spram.h> 32 #include <asm/uaccess.h> 33 34 static int mips_fpu_disabled; 35 36 static int __init fpu_disable(char *s) 37 { 38 cpu_data[0].options &= ~MIPS_CPU_FPU; 39 mips_fpu_disabled = 1; 40 41 return 1; 42 } 43 44 __setup("nofpu", fpu_disable); 45 46 int mips_dsp_disabled; 47 48 static int __init dsp_disable(char *s) 49 { 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 51 mips_dsp_disabled = 1; 52 53 return 1; 54 } 55 56 __setup("nodsp", dsp_disable); 57 58 static int mips_htw_disabled; 59 60 static int __init htw_disable(char *s) 61 { 62 mips_htw_disabled = 1; 63 cpu_data[0].options &= ~MIPS_CPU_HTW; 64 write_c0_pwctl(read_c0_pwctl() & 65 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 66 67 return 1; 68 } 69 70 __setup("nohtw", htw_disable); 71 72 static int mips_ftlb_disabled; 73 static int mips_has_ftlb_configured; 74 75 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); 76 77 static int __init ftlb_disable(char *s) 78 { 79 unsigned int config4, mmuextdef; 80 81 /* 82 * If the core hasn't done any FTLB configuration, there is nothing 83 * for us to do here. 84 */ 85 if (!mips_has_ftlb_configured) 86 return 1; 87 88 /* Disable it in the boot cpu */ 89 set_ftlb_enable(&cpu_data[0], 0); 90 91 back_to_back_c0_hazard(); 92 93 config4 = read_c0_config4(); 94 95 /* Check that FTLB has been disabled */ 96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 99 /* This should never happen */ 100 pr_warn("FTLB could not be disabled!\n"); 101 return 1; 102 } 103 104 mips_ftlb_disabled = 1; 105 mips_has_ftlb_configured = 0; 106 107 /* 108 * noftlb is mainly used for debug purposes so print 109 * an informative message instead of using pr_debug() 110 */ 111 pr_info("FTLB has been disabled\n"); 112 113 /* 114 * Some of these bits are duplicated in the decode_config4. 115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 116 * once FTLB has been disabled so undo what decode_config4 did. 117 */ 118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 119 cpu_data[0].tlbsizeftlbsets; 120 cpu_data[0].tlbsizeftlbsets = 0; 121 cpu_data[0].tlbsizeftlbways = 0; 122 123 return 1; 124 } 125 126 __setup("noftlb", ftlb_disable); 127 128 129 static inline void check_errata(void) 130 { 131 struct cpuinfo_mips *c = ¤t_cpu_data; 132 133 switch (current_cpu_type()) { 134 case CPU_34K: 135 /* 136 * Erratum "RPS May Cause Incorrect Instruction Execution" 137 * This code only handles VPE0, any SMP/RTOS code 138 * making use of VPE1 will be responsable for that VPE. 139 */ 140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 142 break; 143 default: 144 break; 145 } 146 } 147 148 void __init check_bugs32(void) 149 { 150 check_errata(); 151 } 152 153 /* 154 * Probe whether cpu has config register by trying to play with 155 * alternate cache bit and see whether it matters. 156 * It's used by cpu_probe to distinguish between R3000A and R3081. 157 */ 158 static inline int cpu_has_confreg(void) 159 { 160 #ifdef CONFIG_CPU_R3000 161 extern unsigned long r3k_cache_size(unsigned long); 162 unsigned long size1, size2; 163 unsigned long cfg = read_c0_conf(); 164 165 size1 = r3k_cache_size(ST0_ISC); 166 write_c0_conf(cfg ^ R30XX_CONF_AC); 167 size2 = r3k_cache_size(ST0_ISC); 168 write_c0_conf(cfg); 169 return size1 != size2; 170 #else 171 return 0; 172 #endif 173 } 174 175 static inline void set_elf_platform(int cpu, const char *plat) 176 { 177 if (cpu == 0) 178 __elf_platform = plat; 179 } 180 181 /* 182 * Get the FPU Implementation/Revision. 183 */ 184 static inline unsigned long cpu_get_fpu_id(void) 185 { 186 unsigned long tmp, fpu_id; 187 188 tmp = read_c0_status(); 189 __enable_fpu(FPU_AS_IS); 190 fpu_id = read_32bit_cp1_register(CP1_REVISION); 191 write_c0_status(tmp); 192 return fpu_id; 193 } 194 195 /* 196 * Check the CPU has an FPU the official way. 197 */ 198 static inline int __cpu_has_fpu(void) 199 { 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 201 } 202 203 static inline unsigned long cpu_get_msa_id(void) 204 { 205 unsigned long status, msa_id; 206 207 status = read_c0_status(); 208 __enable_fpu(FPU_64BIT); 209 enable_msa(); 210 msa_id = read_msa_ir(); 211 disable_msa(); 212 write_c0_status(status); 213 return msa_id; 214 } 215 216 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 217 { 218 #ifdef __NEED_VMBITS_PROBE 219 write_c0_entryhi(0x3fffffffffffe000ULL); 220 back_to_back_c0_hazard(); 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 222 #endif 223 } 224 225 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 226 { 227 switch (isa) { 228 case MIPS_CPU_ISA_M64R2: 229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 230 case MIPS_CPU_ISA_M64R1: 231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 232 case MIPS_CPU_ISA_V: 233 c->isa_level |= MIPS_CPU_ISA_V; 234 case MIPS_CPU_ISA_IV: 235 c->isa_level |= MIPS_CPU_ISA_IV; 236 case MIPS_CPU_ISA_III: 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 238 break; 239 240 /* R6 incompatible with everything else */ 241 case MIPS_CPU_ISA_M64R6: 242 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 243 case MIPS_CPU_ISA_M32R6: 244 c->isa_level |= MIPS_CPU_ISA_M32R6; 245 /* Break here so we don't add incompatible ISAs */ 246 break; 247 case MIPS_CPU_ISA_M32R2: 248 c->isa_level |= MIPS_CPU_ISA_M32R2; 249 case MIPS_CPU_ISA_M32R1: 250 c->isa_level |= MIPS_CPU_ISA_M32R1; 251 case MIPS_CPU_ISA_II: 252 c->isa_level |= MIPS_CPU_ISA_II; 253 break; 254 } 255 } 256 257 static char unknown_isa[] = KERN_ERR \ 258 "Unsupported ISA type, c0.config0: %d."; 259 260 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 261 { 262 263 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 264 265 /* 266 * 0 = All TLBWR instructions go to FTLB 267 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 268 * FTLB and 1 goes to the VTLB. 269 * 2 = 7:1: As above with 7:1 ratio. 270 * 3 = 3:1: As above with 3:1 ratio. 271 * 272 * Use the linear midpoint as the probability threshold. 273 */ 274 if (probability >= 12) 275 return 1; 276 else if (probability >= 6) 277 return 2; 278 else 279 /* 280 * So FTLB is less than 4 times bigger than VTLB. 281 * A 3:1 ratio can still be useful though. 282 */ 283 return 3; 284 } 285 286 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 287 { 288 unsigned int config6; 289 290 /* It's implementation dependent how the FTLB can be enabled */ 291 switch (c->cputype) { 292 case CPU_PROAPTIV: 293 case CPU_P5600: 294 /* proAptiv & related cores use Config6 to enable the FTLB */ 295 config6 = read_c0_config6(); 296 /* Clear the old probability value */ 297 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 298 if (enable) 299 /* Enable FTLB */ 300 write_c0_config6(config6 | 301 (calculate_ftlb_probability(c) 302 << MIPS_CONF6_FTLBP_SHIFT) 303 | MIPS_CONF6_FTLBEN); 304 else 305 /* Disable FTLB */ 306 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 307 back_to_back_c0_hazard(); 308 break; 309 } 310 } 311 312 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 313 { 314 unsigned int config0; 315 int isa; 316 317 config0 = read_c0_config(); 318 319 /* 320 * Look for Standard TLB or Dual VTLB and FTLB 321 */ 322 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 323 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 324 c->options |= MIPS_CPU_TLB; 325 326 isa = (config0 & MIPS_CONF_AT) >> 13; 327 switch (isa) { 328 case 0: 329 switch ((config0 & MIPS_CONF_AR) >> 10) { 330 case 0: 331 set_isa(c, MIPS_CPU_ISA_M32R1); 332 break; 333 case 1: 334 set_isa(c, MIPS_CPU_ISA_M32R2); 335 break; 336 case 2: 337 set_isa(c, MIPS_CPU_ISA_M32R6); 338 break; 339 default: 340 goto unknown; 341 } 342 break; 343 case 2: 344 switch ((config0 & MIPS_CONF_AR) >> 10) { 345 case 0: 346 set_isa(c, MIPS_CPU_ISA_M64R1); 347 break; 348 case 1: 349 set_isa(c, MIPS_CPU_ISA_M64R2); 350 break; 351 case 2: 352 set_isa(c, MIPS_CPU_ISA_M64R6); 353 break; 354 default: 355 goto unknown; 356 } 357 break; 358 default: 359 goto unknown; 360 } 361 362 return config0 & MIPS_CONF_M; 363 364 unknown: 365 panic(unknown_isa, config0); 366 } 367 368 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 369 { 370 unsigned int config1; 371 372 config1 = read_c0_config1(); 373 374 if (config1 & MIPS_CONF1_MD) 375 c->ases |= MIPS_ASE_MDMX; 376 if (config1 & MIPS_CONF1_WR) 377 c->options |= MIPS_CPU_WATCH; 378 if (config1 & MIPS_CONF1_CA) 379 c->ases |= MIPS_ASE_MIPS16; 380 if (config1 & MIPS_CONF1_EP) 381 c->options |= MIPS_CPU_EJTAG; 382 if (config1 & MIPS_CONF1_FP) { 383 c->options |= MIPS_CPU_FPU; 384 c->options |= MIPS_CPU_32FPR; 385 } 386 if (cpu_has_tlb) { 387 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 388 c->tlbsizevtlb = c->tlbsize; 389 c->tlbsizeftlbsets = 0; 390 } 391 392 return config1 & MIPS_CONF_M; 393 } 394 395 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 396 { 397 unsigned int config2; 398 399 config2 = read_c0_config2(); 400 401 if (config2 & MIPS_CONF2_SL) 402 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 403 404 return config2 & MIPS_CONF_M; 405 } 406 407 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 408 { 409 unsigned int config3; 410 411 config3 = read_c0_config3(); 412 413 if (config3 & MIPS_CONF3_SM) { 414 c->ases |= MIPS_ASE_SMARTMIPS; 415 c->options |= MIPS_CPU_RIXI; 416 } 417 if (config3 & MIPS_CONF3_RXI) 418 c->options |= MIPS_CPU_RIXI; 419 if (config3 & MIPS_CONF3_DSP) 420 c->ases |= MIPS_ASE_DSP; 421 if (config3 & MIPS_CONF3_DSP2P) 422 c->ases |= MIPS_ASE_DSP2P; 423 if (config3 & MIPS_CONF3_VINT) 424 c->options |= MIPS_CPU_VINT; 425 if (config3 & MIPS_CONF3_VEIC) 426 c->options |= MIPS_CPU_VEIC; 427 if (config3 & MIPS_CONF3_MT) 428 c->ases |= MIPS_ASE_MIPSMT; 429 if (config3 & MIPS_CONF3_ULRI) 430 c->options |= MIPS_CPU_ULRI; 431 if (config3 & MIPS_CONF3_ISA) 432 c->options |= MIPS_CPU_MICROMIPS; 433 if (config3 & MIPS_CONF3_VZ) 434 c->ases |= MIPS_ASE_VZ; 435 if (config3 & MIPS_CONF3_SC) 436 c->options |= MIPS_CPU_SEGMENTS; 437 if (config3 & MIPS_CONF3_MSA) 438 c->ases |= MIPS_ASE_MSA; 439 /* Only tested on 32-bit cores */ 440 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { 441 c->htw_seq = 0; 442 c->options |= MIPS_CPU_HTW; 443 } 444 445 return config3 & MIPS_CONF_M; 446 } 447 448 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 449 { 450 unsigned int config4; 451 unsigned int newcf4; 452 unsigned int mmuextdef; 453 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 454 455 config4 = read_c0_config4(); 456 457 if (cpu_has_tlb) { 458 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 459 c->options |= MIPS_CPU_TLBINV; 460 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 461 switch (mmuextdef) { 462 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 463 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 464 c->tlbsizevtlb = c->tlbsize; 465 break; 466 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 467 c->tlbsizevtlb += 468 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 469 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 470 c->tlbsize = c->tlbsizevtlb; 471 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 472 /* fall through */ 473 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 474 if (mips_ftlb_disabled) 475 break; 476 newcf4 = (config4 & ~ftlb_page) | 477 (page_size_ftlb(mmuextdef) << 478 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 479 write_c0_config4(newcf4); 480 back_to_back_c0_hazard(); 481 config4 = read_c0_config4(); 482 if (config4 != newcf4) { 483 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 484 PAGE_SIZE, config4); 485 /* Switch FTLB off */ 486 set_ftlb_enable(c, 0); 487 break; 488 } 489 c->tlbsizeftlbsets = 1 << 490 ((config4 & MIPS_CONF4_FTLBSETS) >> 491 MIPS_CONF4_FTLBSETS_SHIFT); 492 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 493 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 494 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 495 mips_has_ftlb_configured = 1; 496 break; 497 } 498 } 499 500 c->kscratch_mask = (config4 >> 16) & 0xff; 501 502 return config4 & MIPS_CONF_M; 503 } 504 505 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 506 { 507 unsigned int config5; 508 509 config5 = read_c0_config5(); 510 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 511 write_c0_config5(config5); 512 513 if (config5 & MIPS_CONF5_EVA) 514 c->options |= MIPS_CPU_EVA; 515 if (config5 & MIPS_CONF5_MRP) 516 c->options |= MIPS_CPU_MAAR; 517 if (config5 & MIPS_CONF5_LLB) 518 c->options |= MIPS_CPU_RW_LLB; 519 520 return config5 & MIPS_CONF_M; 521 } 522 523 static void decode_configs(struct cpuinfo_mips *c) 524 { 525 int ok; 526 527 /* MIPS32 or MIPS64 compliant CPU. */ 528 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 529 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 530 531 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 532 533 /* Enable FTLB if present and not disabled */ 534 set_ftlb_enable(c, !mips_ftlb_disabled); 535 536 ok = decode_config0(c); /* Read Config registers. */ 537 BUG_ON(!ok); /* Arch spec violation! */ 538 if (ok) 539 ok = decode_config1(c); 540 if (ok) 541 ok = decode_config2(c); 542 if (ok) 543 ok = decode_config3(c); 544 if (ok) 545 ok = decode_config4(c); 546 if (ok) 547 ok = decode_config5(c); 548 549 mips_probe_watch_registers(c); 550 551 if (cpu_has_rixi) { 552 /* Enable the RIXI exceptions */ 553 set_c0_pagegrain(PG_IEC); 554 back_to_back_c0_hazard(); 555 /* Verify the IEC bit is set */ 556 if (read_c0_pagegrain() & PG_IEC) 557 c->options |= MIPS_CPU_RIXIEX; 558 } 559 560 #ifndef CONFIG_MIPS_CPS 561 if (cpu_has_mips_r2_r6) { 562 c->core = get_ebase_cpunum(); 563 if (cpu_has_mipsmt) 564 c->core >>= fls(core_nvpes()) - 1; 565 } 566 #endif 567 } 568 569 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 570 | MIPS_CPU_COUNTER) 571 572 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 573 { 574 switch (c->processor_id & PRID_IMP_MASK) { 575 case PRID_IMP_R2000: 576 c->cputype = CPU_R2000; 577 __cpu_name[cpu] = "R2000"; 578 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 579 MIPS_CPU_NOFPUEX; 580 if (__cpu_has_fpu()) 581 c->options |= MIPS_CPU_FPU; 582 c->tlbsize = 64; 583 break; 584 case PRID_IMP_R3000: 585 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 586 if (cpu_has_confreg()) { 587 c->cputype = CPU_R3081E; 588 __cpu_name[cpu] = "R3081"; 589 } else { 590 c->cputype = CPU_R3000A; 591 __cpu_name[cpu] = "R3000A"; 592 } 593 } else { 594 c->cputype = CPU_R3000; 595 __cpu_name[cpu] = "R3000"; 596 } 597 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 598 MIPS_CPU_NOFPUEX; 599 if (__cpu_has_fpu()) 600 c->options |= MIPS_CPU_FPU; 601 c->tlbsize = 64; 602 break; 603 case PRID_IMP_R4000: 604 if (read_c0_config() & CONF_SC) { 605 if ((c->processor_id & PRID_REV_MASK) >= 606 PRID_REV_R4400) { 607 c->cputype = CPU_R4400PC; 608 __cpu_name[cpu] = "R4400PC"; 609 } else { 610 c->cputype = CPU_R4000PC; 611 __cpu_name[cpu] = "R4000PC"; 612 } 613 } else { 614 int cca = read_c0_config() & CONF_CM_CMASK; 615 int mc; 616 617 /* 618 * SC and MC versions can't be reliably told apart, 619 * but only the latter support coherent caching 620 * modes so assume the firmware has set the KSEG0 621 * coherency attribute reasonably (if uncached, we 622 * assume SC). 623 */ 624 switch (cca) { 625 case CONF_CM_CACHABLE_CE: 626 case CONF_CM_CACHABLE_COW: 627 case CONF_CM_CACHABLE_CUW: 628 mc = 1; 629 break; 630 default: 631 mc = 0; 632 break; 633 } 634 if ((c->processor_id & PRID_REV_MASK) >= 635 PRID_REV_R4400) { 636 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 637 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 638 } else { 639 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 640 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 641 } 642 } 643 644 set_isa(c, MIPS_CPU_ISA_III); 645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 646 MIPS_CPU_WATCH | MIPS_CPU_VCE | 647 MIPS_CPU_LLSC; 648 c->tlbsize = 48; 649 break; 650 case PRID_IMP_VR41XX: 651 set_isa(c, MIPS_CPU_ISA_III); 652 c->options = R4K_OPTS; 653 c->tlbsize = 32; 654 switch (c->processor_id & 0xf0) { 655 case PRID_REV_VR4111: 656 c->cputype = CPU_VR4111; 657 __cpu_name[cpu] = "NEC VR4111"; 658 break; 659 case PRID_REV_VR4121: 660 c->cputype = CPU_VR4121; 661 __cpu_name[cpu] = "NEC VR4121"; 662 break; 663 case PRID_REV_VR4122: 664 if ((c->processor_id & 0xf) < 0x3) { 665 c->cputype = CPU_VR4122; 666 __cpu_name[cpu] = "NEC VR4122"; 667 } else { 668 c->cputype = CPU_VR4181A; 669 __cpu_name[cpu] = "NEC VR4181A"; 670 } 671 break; 672 case PRID_REV_VR4130: 673 if ((c->processor_id & 0xf) < 0x4) { 674 c->cputype = CPU_VR4131; 675 __cpu_name[cpu] = "NEC VR4131"; 676 } else { 677 c->cputype = CPU_VR4133; 678 c->options |= MIPS_CPU_LLSC; 679 __cpu_name[cpu] = "NEC VR4133"; 680 } 681 break; 682 default: 683 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 684 c->cputype = CPU_VR41XX; 685 __cpu_name[cpu] = "NEC Vr41xx"; 686 break; 687 } 688 break; 689 case PRID_IMP_R4300: 690 c->cputype = CPU_R4300; 691 __cpu_name[cpu] = "R4300"; 692 set_isa(c, MIPS_CPU_ISA_III); 693 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 694 MIPS_CPU_LLSC; 695 c->tlbsize = 32; 696 break; 697 case PRID_IMP_R4600: 698 c->cputype = CPU_R4600; 699 __cpu_name[cpu] = "R4600"; 700 set_isa(c, MIPS_CPU_ISA_III); 701 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 702 MIPS_CPU_LLSC; 703 c->tlbsize = 48; 704 break; 705 #if 0 706 case PRID_IMP_R4650: 707 /* 708 * This processor doesn't have an MMU, so it's not 709 * "real easy" to run Linux on it. It is left purely 710 * for documentation. Commented out because it shares 711 * it's c0_prid id number with the TX3900. 712 */ 713 c->cputype = CPU_R4650; 714 __cpu_name[cpu] = "R4650"; 715 set_isa(c, MIPS_CPU_ISA_III); 716 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 717 c->tlbsize = 48; 718 break; 719 #endif 720 case PRID_IMP_TX39: 721 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 722 723 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 724 c->cputype = CPU_TX3927; 725 __cpu_name[cpu] = "TX3927"; 726 c->tlbsize = 64; 727 } else { 728 switch (c->processor_id & PRID_REV_MASK) { 729 case PRID_REV_TX3912: 730 c->cputype = CPU_TX3912; 731 __cpu_name[cpu] = "TX3912"; 732 c->tlbsize = 32; 733 break; 734 case PRID_REV_TX3922: 735 c->cputype = CPU_TX3922; 736 __cpu_name[cpu] = "TX3922"; 737 c->tlbsize = 64; 738 break; 739 } 740 } 741 break; 742 case PRID_IMP_R4700: 743 c->cputype = CPU_R4700; 744 __cpu_name[cpu] = "R4700"; 745 set_isa(c, MIPS_CPU_ISA_III); 746 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 747 MIPS_CPU_LLSC; 748 c->tlbsize = 48; 749 break; 750 case PRID_IMP_TX49: 751 c->cputype = CPU_TX49XX; 752 __cpu_name[cpu] = "R49XX"; 753 set_isa(c, MIPS_CPU_ISA_III); 754 c->options = R4K_OPTS | MIPS_CPU_LLSC; 755 if (!(c->processor_id & 0x08)) 756 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 757 c->tlbsize = 48; 758 break; 759 case PRID_IMP_R5000: 760 c->cputype = CPU_R5000; 761 __cpu_name[cpu] = "R5000"; 762 set_isa(c, MIPS_CPU_ISA_IV); 763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 764 MIPS_CPU_LLSC; 765 c->tlbsize = 48; 766 break; 767 case PRID_IMP_R5432: 768 c->cputype = CPU_R5432; 769 __cpu_name[cpu] = "R5432"; 770 set_isa(c, MIPS_CPU_ISA_IV); 771 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 772 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 773 c->tlbsize = 48; 774 break; 775 case PRID_IMP_R5500: 776 c->cputype = CPU_R5500; 777 __cpu_name[cpu] = "R5500"; 778 set_isa(c, MIPS_CPU_ISA_IV); 779 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 780 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 781 c->tlbsize = 48; 782 break; 783 case PRID_IMP_NEVADA: 784 c->cputype = CPU_NEVADA; 785 __cpu_name[cpu] = "Nevada"; 786 set_isa(c, MIPS_CPU_ISA_IV); 787 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 788 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 789 c->tlbsize = 48; 790 break; 791 case PRID_IMP_R6000: 792 c->cputype = CPU_R6000; 793 __cpu_name[cpu] = "R6000"; 794 set_isa(c, MIPS_CPU_ISA_II); 795 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 796 MIPS_CPU_LLSC; 797 c->tlbsize = 32; 798 break; 799 case PRID_IMP_R6000A: 800 c->cputype = CPU_R6000A; 801 __cpu_name[cpu] = "R6000A"; 802 set_isa(c, MIPS_CPU_ISA_II); 803 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 804 MIPS_CPU_LLSC; 805 c->tlbsize = 32; 806 break; 807 case PRID_IMP_RM7000: 808 c->cputype = CPU_RM7000; 809 __cpu_name[cpu] = "RM7000"; 810 set_isa(c, MIPS_CPU_ISA_IV); 811 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 812 MIPS_CPU_LLSC; 813 /* 814 * Undocumented RM7000: Bit 29 in the info register of 815 * the RM7000 v2.0 indicates if the TLB has 48 or 64 816 * entries. 817 * 818 * 29 1 => 64 entry JTLB 819 * 0 => 48 entry JTLB 820 */ 821 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 822 break; 823 case PRID_IMP_R8000: 824 c->cputype = CPU_R8000; 825 __cpu_name[cpu] = "RM8000"; 826 set_isa(c, MIPS_CPU_ISA_IV); 827 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 828 MIPS_CPU_FPU | MIPS_CPU_32FPR | 829 MIPS_CPU_LLSC; 830 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 831 break; 832 case PRID_IMP_R10000: 833 c->cputype = CPU_R10000; 834 __cpu_name[cpu] = "R10000"; 835 set_isa(c, MIPS_CPU_ISA_IV); 836 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 837 MIPS_CPU_FPU | MIPS_CPU_32FPR | 838 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 839 MIPS_CPU_LLSC; 840 c->tlbsize = 64; 841 break; 842 case PRID_IMP_R12000: 843 c->cputype = CPU_R12000; 844 __cpu_name[cpu] = "R12000"; 845 set_isa(c, MIPS_CPU_ISA_IV); 846 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 847 MIPS_CPU_FPU | MIPS_CPU_32FPR | 848 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 849 MIPS_CPU_LLSC; 850 c->tlbsize = 64; 851 break; 852 case PRID_IMP_R14000: 853 c->cputype = CPU_R14000; 854 __cpu_name[cpu] = "R14000"; 855 set_isa(c, MIPS_CPU_ISA_IV); 856 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 857 MIPS_CPU_FPU | MIPS_CPU_32FPR | 858 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 859 MIPS_CPU_LLSC; 860 c->tlbsize = 64; 861 break; 862 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 863 switch (c->processor_id & PRID_REV_MASK) { 864 case PRID_REV_LOONGSON2E: 865 c->cputype = CPU_LOONGSON2; 866 __cpu_name[cpu] = "ICT Loongson-2"; 867 set_elf_platform(cpu, "loongson2e"); 868 set_isa(c, MIPS_CPU_ISA_III); 869 break; 870 case PRID_REV_LOONGSON2F: 871 c->cputype = CPU_LOONGSON2; 872 __cpu_name[cpu] = "ICT Loongson-2"; 873 set_elf_platform(cpu, "loongson2f"); 874 set_isa(c, MIPS_CPU_ISA_III); 875 break; 876 case PRID_REV_LOONGSON3A: 877 c->cputype = CPU_LOONGSON3; 878 __cpu_name[cpu] = "ICT Loongson-3"; 879 set_elf_platform(cpu, "loongson3a"); 880 set_isa(c, MIPS_CPU_ISA_M64R1); 881 break; 882 case PRID_REV_LOONGSON3B_R1: 883 case PRID_REV_LOONGSON3B_R2: 884 c->cputype = CPU_LOONGSON3; 885 __cpu_name[cpu] = "ICT Loongson-3"; 886 set_elf_platform(cpu, "loongson3b"); 887 set_isa(c, MIPS_CPU_ISA_M64R1); 888 break; 889 } 890 891 c->options = R4K_OPTS | 892 MIPS_CPU_FPU | MIPS_CPU_LLSC | 893 MIPS_CPU_32FPR; 894 c->tlbsize = 64; 895 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 896 break; 897 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 898 decode_configs(c); 899 900 c->cputype = CPU_LOONGSON1; 901 902 switch (c->processor_id & PRID_REV_MASK) { 903 case PRID_REV_LOONGSON1B: 904 __cpu_name[cpu] = "Loongson 1B"; 905 break; 906 } 907 908 break; 909 } 910 } 911 912 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 913 { 914 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 915 switch (c->processor_id & PRID_IMP_MASK) { 916 case PRID_IMP_QEMU_GENERIC: 917 c->writecombine = _CACHE_UNCACHED; 918 c->cputype = CPU_QEMU_GENERIC; 919 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 920 break; 921 case PRID_IMP_4KC: 922 c->cputype = CPU_4KC; 923 c->writecombine = _CACHE_UNCACHED; 924 __cpu_name[cpu] = "MIPS 4Kc"; 925 break; 926 case PRID_IMP_4KEC: 927 case PRID_IMP_4KECR2: 928 c->cputype = CPU_4KEC; 929 c->writecombine = _CACHE_UNCACHED; 930 __cpu_name[cpu] = "MIPS 4KEc"; 931 break; 932 case PRID_IMP_4KSC: 933 case PRID_IMP_4KSD: 934 c->cputype = CPU_4KSC; 935 c->writecombine = _CACHE_UNCACHED; 936 __cpu_name[cpu] = "MIPS 4KSc"; 937 break; 938 case PRID_IMP_5KC: 939 c->cputype = CPU_5KC; 940 c->writecombine = _CACHE_UNCACHED; 941 __cpu_name[cpu] = "MIPS 5Kc"; 942 break; 943 case PRID_IMP_5KE: 944 c->cputype = CPU_5KE; 945 c->writecombine = _CACHE_UNCACHED; 946 __cpu_name[cpu] = "MIPS 5KE"; 947 break; 948 case PRID_IMP_20KC: 949 c->cputype = CPU_20KC; 950 c->writecombine = _CACHE_UNCACHED; 951 __cpu_name[cpu] = "MIPS 20Kc"; 952 break; 953 case PRID_IMP_24K: 954 c->cputype = CPU_24K; 955 c->writecombine = _CACHE_UNCACHED; 956 __cpu_name[cpu] = "MIPS 24Kc"; 957 break; 958 case PRID_IMP_24KE: 959 c->cputype = CPU_24K; 960 c->writecombine = _CACHE_UNCACHED; 961 __cpu_name[cpu] = "MIPS 24KEc"; 962 break; 963 case PRID_IMP_25KF: 964 c->cputype = CPU_25KF; 965 c->writecombine = _CACHE_UNCACHED; 966 __cpu_name[cpu] = "MIPS 25Kc"; 967 break; 968 case PRID_IMP_34K: 969 c->cputype = CPU_34K; 970 c->writecombine = _CACHE_UNCACHED; 971 __cpu_name[cpu] = "MIPS 34Kc"; 972 break; 973 case PRID_IMP_74K: 974 c->cputype = CPU_74K; 975 c->writecombine = _CACHE_UNCACHED; 976 __cpu_name[cpu] = "MIPS 74Kc"; 977 break; 978 case PRID_IMP_M14KC: 979 c->cputype = CPU_M14KC; 980 c->writecombine = _CACHE_UNCACHED; 981 __cpu_name[cpu] = "MIPS M14Kc"; 982 break; 983 case PRID_IMP_M14KEC: 984 c->cputype = CPU_M14KEC; 985 c->writecombine = _CACHE_UNCACHED; 986 __cpu_name[cpu] = "MIPS M14KEc"; 987 break; 988 case PRID_IMP_1004K: 989 c->cputype = CPU_1004K; 990 c->writecombine = _CACHE_UNCACHED; 991 __cpu_name[cpu] = "MIPS 1004Kc"; 992 break; 993 case PRID_IMP_1074K: 994 c->cputype = CPU_1074K; 995 c->writecombine = _CACHE_UNCACHED; 996 __cpu_name[cpu] = "MIPS 1074Kc"; 997 break; 998 case PRID_IMP_INTERAPTIV_UP: 999 c->cputype = CPU_INTERAPTIV; 1000 __cpu_name[cpu] = "MIPS interAptiv"; 1001 break; 1002 case PRID_IMP_INTERAPTIV_MP: 1003 c->cputype = CPU_INTERAPTIV; 1004 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1005 break; 1006 case PRID_IMP_PROAPTIV_UP: 1007 c->cputype = CPU_PROAPTIV; 1008 __cpu_name[cpu] = "MIPS proAptiv"; 1009 break; 1010 case PRID_IMP_PROAPTIV_MP: 1011 c->cputype = CPU_PROAPTIV; 1012 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1013 break; 1014 case PRID_IMP_P5600: 1015 c->cputype = CPU_P5600; 1016 __cpu_name[cpu] = "MIPS P5600"; 1017 break; 1018 case PRID_IMP_M5150: 1019 c->cputype = CPU_M5150; 1020 __cpu_name[cpu] = "MIPS M5150"; 1021 break; 1022 } 1023 1024 decode_configs(c); 1025 1026 spram_config(); 1027 } 1028 1029 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1030 { 1031 decode_configs(c); 1032 switch (c->processor_id & PRID_IMP_MASK) { 1033 case PRID_IMP_AU1_REV1: 1034 case PRID_IMP_AU1_REV2: 1035 c->cputype = CPU_ALCHEMY; 1036 switch ((c->processor_id >> 24) & 0xff) { 1037 case 0: 1038 __cpu_name[cpu] = "Au1000"; 1039 break; 1040 case 1: 1041 __cpu_name[cpu] = "Au1500"; 1042 break; 1043 case 2: 1044 __cpu_name[cpu] = "Au1100"; 1045 break; 1046 case 3: 1047 __cpu_name[cpu] = "Au1550"; 1048 break; 1049 case 4: 1050 __cpu_name[cpu] = "Au1200"; 1051 if ((c->processor_id & PRID_REV_MASK) == 2) 1052 __cpu_name[cpu] = "Au1250"; 1053 break; 1054 case 5: 1055 __cpu_name[cpu] = "Au1210"; 1056 break; 1057 default: 1058 __cpu_name[cpu] = "Au1xxx"; 1059 break; 1060 } 1061 break; 1062 } 1063 } 1064 1065 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1066 { 1067 decode_configs(c); 1068 1069 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1070 switch (c->processor_id & PRID_IMP_MASK) { 1071 case PRID_IMP_SB1: 1072 c->cputype = CPU_SB1; 1073 __cpu_name[cpu] = "SiByte SB1"; 1074 /* FPU in pass1 is known to have issues. */ 1075 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1076 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1077 break; 1078 case PRID_IMP_SB1A: 1079 c->cputype = CPU_SB1A; 1080 __cpu_name[cpu] = "SiByte SB1A"; 1081 break; 1082 } 1083 } 1084 1085 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1086 { 1087 decode_configs(c); 1088 switch (c->processor_id & PRID_IMP_MASK) { 1089 case PRID_IMP_SR71000: 1090 c->cputype = CPU_SR71000; 1091 __cpu_name[cpu] = "Sandcraft SR71000"; 1092 c->scache.ways = 8; 1093 c->tlbsize = 64; 1094 break; 1095 } 1096 } 1097 1098 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1099 { 1100 decode_configs(c); 1101 switch (c->processor_id & PRID_IMP_MASK) { 1102 case PRID_IMP_PR4450: 1103 c->cputype = CPU_PR4450; 1104 __cpu_name[cpu] = "Philips PR4450"; 1105 set_isa(c, MIPS_CPU_ISA_M32R1); 1106 break; 1107 } 1108 } 1109 1110 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1111 { 1112 decode_configs(c); 1113 switch (c->processor_id & PRID_IMP_MASK) { 1114 case PRID_IMP_BMIPS32_REV4: 1115 case PRID_IMP_BMIPS32_REV8: 1116 c->cputype = CPU_BMIPS32; 1117 __cpu_name[cpu] = "Broadcom BMIPS32"; 1118 set_elf_platform(cpu, "bmips32"); 1119 break; 1120 case PRID_IMP_BMIPS3300: 1121 case PRID_IMP_BMIPS3300_ALT: 1122 case PRID_IMP_BMIPS3300_BUG: 1123 c->cputype = CPU_BMIPS3300; 1124 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1125 set_elf_platform(cpu, "bmips3300"); 1126 break; 1127 case PRID_IMP_BMIPS43XX: { 1128 int rev = c->processor_id & PRID_REV_MASK; 1129 1130 if (rev >= PRID_REV_BMIPS4380_LO && 1131 rev <= PRID_REV_BMIPS4380_HI) { 1132 c->cputype = CPU_BMIPS4380; 1133 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1134 set_elf_platform(cpu, "bmips4380"); 1135 } else { 1136 c->cputype = CPU_BMIPS4350; 1137 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1138 set_elf_platform(cpu, "bmips4350"); 1139 } 1140 break; 1141 } 1142 case PRID_IMP_BMIPS5000: 1143 case PRID_IMP_BMIPS5200: 1144 c->cputype = CPU_BMIPS5000; 1145 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1146 set_elf_platform(cpu, "bmips5000"); 1147 c->options |= MIPS_CPU_ULRI; 1148 break; 1149 } 1150 } 1151 1152 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1153 { 1154 decode_configs(c); 1155 switch (c->processor_id & PRID_IMP_MASK) { 1156 case PRID_IMP_CAVIUM_CN38XX: 1157 case PRID_IMP_CAVIUM_CN31XX: 1158 case PRID_IMP_CAVIUM_CN30XX: 1159 c->cputype = CPU_CAVIUM_OCTEON; 1160 __cpu_name[cpu] = "Cavium Octeon"; 1161 goto platform; 1162 case PRID_IMP_CAVIUM_CN58XX: 1163 case PRID_IMP_CAVIUM_CN56XX: 1164 case PRID_IMP_CAVIUM_CN50XX: 1165 case PRID_IMP_CAVIUM_CN52XX: 1166 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1167 __cpu_name[cpu] = "Cavium Octeon+"; 1168 platform: 1169 set_elf_platform(cpu, "octeon"); 1170 break; 1171 case PRID_IMP_CAVIUM_CN61XX: 1172 case PRID_IMP_CAVIUM_CN63XX: 1173 case PRID_IMP_CAVIUM_CN66XX: 1174 case PRID_IMP_CAVIUM_CN68XX: 1175 case PRID_IMP_CAVIUM_CNF71XX: 1176 c->cputype = CPU_CAVIUM_OCTEON2; 1177 __cpu_name[cpu] = "Cavium Octeon II"; 1178 set_elf_platform(cpu, "octeon2"); 1179 break; 1180 case PRID_IMP_CAVIUM_CN70XX: 1181 case PRID_IMP_CAVIUM_CN78XX: 1182 c->cputype = CPU_CAVIUM_OCTEON3; 1183 __cpu_name[cpu] = "Cavium Octeon III"; 1184 set_elf_platform(cpu, "octeon3"); 1185 break; 1186 default: 1187 printk(KERN_INFO "Unknown Octeon chip!\n"); 1188 c->cputype = CPU_UNKNOWN; 1189 break; 1190 } 1191 } 1192 1193 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1194 { 1195 decode_configs(c); 1196 /* JZRISC does not implement the CP0 counter. */ 1197 c->options &= ~MIPS_CPU_COUNTER; 1198 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1199 switch (c->processor_id & PRID_IMP_MASK) { 1200 case PRID_IMP_JZRISC: 1201 c->cputype = CPU_JZRISC; 1202 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1203 __cpu_name[cpu] = "Ingenic JZRISC"; 1204 break; 1205 default: 1206 panic("Unknown Ingenic Processor ID!"); 1207 break; 1208 } 1209 } 1210 1211 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1212 { 1213 decode_configs(c); 1214 1215 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1216 c->cputype = CPU_ALCHEMY; 1217 __cpu_name[cpu] = "Au1300"; 1218 /* following stuff is not for Alchemy */ 1219 return; 1220 } 1221 1222 c->options = (MIPS_CPU_TLB | 1223 MIPS_CPU_4KEX | 1224 MIPS_CPU_COUNTER | 1225 MIPS_CPU_DIVEC | 1226 MIPS_CPU_WATCH | 1227 MIPS_CPU_EJTAG | 1228 MIPS_CPU_LLSC); 1229 1230 switch (c->processor_id & PRID_IMP_MASK) { 1231 case PRID_IMP_NETLOGIC_XLP2XX: 1232 case PRID_IMP_NETLOGIC_XLP9XX: 1233 case PRID_IMP_NETLOGIC_XLP5XX: 1234 c->cputype = CPU_XLP; 1235 __cpu_name[cpu] = "Broadcom XLPII"; 1236 break; 1237 1238 case PRID_IMP_NETLOGIC_XLP8XX: 1239 case PRID_IMP_NETLOGIC_XLP3XX: 1240 c->cputype = CPU_XLP; 1241 __cpu_name[cpu] = "Netlogic XLP"; 1242 break; 1243 1244 case PRID_IMP_NETLOGIC_XLR732: 1245 case PRID_IMP_NETLOGIC_XLR716: 1246 case PRID_IMP_NETLOGIC_XLR532: 1247 case PRID_IMP_NETLOGIC_XLR308: 1248 case PRID_IMP_NETLOGIC_XLR532C: 1249 case PRID_IMP_NETLOGIC_XLR516C: 1250 case PRID_IMP_NETLOGIC_XLR508C: 1251 case PRID_IMP_NETLOGIC_XLR308C: 1252 c->cputype = CPU_XLR; 1253 __cpu_name[cpu] = "Netlogic XLR"; 1254 break; 1255 1256 case PRID_IMP_NETLOGIC_XLS608: 1257 case PRID_IMP_NETLOGIC_XLS408: 1258 case PRID_IMP_NETLOGIC_XLS404: 1259 case PRID_IMP_NETLOGIC_XLS208: 1260 case PRID_IMP_NETLOGIC_XLS204: 1261 case PRID_IMP_NETLOGIC_XLS108: 1262 case PRID_IMP_NETLOGIC_XLS104: 1263 case PRID_IMP_NETLOGIC_XLS616B: 1264 case PRID_IMP_NETLOGIC_XLS608B: 1265 case PRID_IMP_NETLOGIC_XLS416B: 1266 case PRID_IMP_NETLOGIC_XLS412B: 1267 case PRID_IMP_NETLOGIC_XLS408B: 1268 case PRID_IMP_NETLOGIC_XLS404B: 1269 c->cputype = CPU_XLR; 1270 __cpu_name[cpu] = "Netlogic XLS"; 1271 break; 1272 1273 default: 1274 pr_info("Unknown Netlogic chip id [%02x]!\n", 1275 c->processor_id); 1276 c->cputype = CPU_XLR; 1277 break; 1278 } 1279 1280 if (c->cputype == CPU_XLP) { 1281 set_isa(c, MIPS_CPU_ISA_M64R2); 1282 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1283 /* This will be updated again after all threads are woken up */ 1284 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1285 } else { 1286 set_isa(c, MIPS_CPU_ISA_M64R1); 1287 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1288 } 1289 c->kscratch_mask = 0xf; 1290 } 1291 1292 #ifdef CONFIG_64BIT 1293 /* For use by uaccess.h */ 1294 u64 __ua_limit; 1295 EXPORT_SYMBOL(__ua_limit); 1296 #endif 1297 1298 const char *__cpu_name[NR_CPUS]; 1299 const char *__elf_platform; 1300 1301 void cpu_probe(void) 1302 { 1303 struct cpuinfo_mips *c = ¤t_cpu_data; 1304 unsigned int cpu = smp_processor_id(); 1305 1306 c->processor_id = PRID_IMP_UNKNOWN; 1307 c->fpu_id = FPIR_IMP_NONE; 1308 c->cputype = CPU_UNKNOWN; 1309 c->writecombine = _CACHE_UNCACHED; 1310 1311 c->processor_id = read_c0_prid(); 1312 switch (c->processor_id & PRID_COMP_MASK) { 1313 case PRID_COMP_LEGACY: 1314 cpu_probe_legacy(c, cpu); 1315 break; 1316 case PRID_COMP_MIPS: 1317 cpu_probe_mips(c, cpu); 1318 break; 1319 case PRID_COMP_ALCHEMY: 1320 cpu_probe_alchemy(c, cpu); 1321 break; 1322 case PRID_COMP_SIBYTE: 1323 cpu_probe_sibyte(c, cpu); 1324 break; 1325 case PRID_COMP_BROADCOM: 1326 cpu_probe_broadcom(c, cpu); 1327 break; 1328 case PRID_COMP_SANDCRAFT: 1329 cpu_probe_sandcraft(c, cpu); 1330 break; 1331 case PRID_COMP_NXP: 1332 cpu_probe_nxp(c, cpu); 1333 break; 1334 case PRID_COMP_CAVIUM: 1335 cpu_probe_cavium(c, cpu); 1336 break; 1337 case PRID_COMP_INGENIC: 1338 cpu_probe_ingenic(c, cpu); 1339 break; 1340 case PRID_COMP_NETLOGIC: 1341 cpu_probe_netlogic(c, cpu); 1342 break; 1343 } 1344 1345 BUG_ON(!__cpu_name[cpu]); 1346 BUG_ON(c->cputype == CPU_UNKNOWN); 1347 1348 /* 1349 * Platform code can force the cpu type to optimize code 1350 * generation. In that case be sure the cpu type is correctly 1351 * manually setup otherwise it could trigger some nasty bugs. 1352 */ 1353 BUG_ON(current_cpu_type() != c->cputype); 1354 1355 if (mips_fpu_disabled) 1356 c->options &= ~MIPS_CPU_FPU; 1357 1358 if (mips_dsp_disabled) 1359 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1360 1361 if (mips_htw_disabled) { 1362 c->options &= ~MIPS_CPU_HTW; 1363 write_c0_pwctl(read_c0_pwctl() & 1364 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1365 } 1366 1367 if (c->options & MIPS_CPU_FPU) { 1368 c->fpu_id = cpu_get_fpu_id(); 1369 1370 if (c->isa_level & cpu_has_mips_r) { 1371 if (c->fpu_id & MIPS_FPIR_3D) 1372 c->ases |= MIPS_ASE_MIPS3D; 1373 if (c->fpu_id & MIPS_FPIR_FREP) 1374 c->options |= MIPS_CPU_FRE; 1375 } 1376 } 1377 1378 if (cpu_has_mips_r2_r6) { 1379 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1380 /* R2 has Performance Counter Interrupt indicator */ 1381 c->options |= MIPS_CPU_PCI; 1382 } 1383 else 1384 c->srsets = 1; 1385 1386 if (cpu_has_msa) { 1387 c->msa_id = cpu_get_msa_id(); 1388 WARN(c->msa_id & MSA_IR_WRPF, 1389 "Vector register partitioning unimplemented!"); 1390 } 1391 1392 cpu_probe_vmbits(c); 1393 1394 #ifdef CONFIG_64BIT 1395 if (cpu == 0) 1396 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1397 #endif 1398 } 1399 1400 void cpu_report(void) 1401 { 1402 struct cpuinfo_mips *c = ¤t_cpu_data; 1403 1404 pr_info("CPU%d revision is: %08x (%s)\n", 1405 smp_processor_id(), c->processor_id, cpu_name_string()); 1406 if (c->options & MIPS_CPU_FPU) 1407 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1408 if (cpu_has_msa) 1409 pr_info("MSA revision is: %08x\n", c->msa_id); 1410 } 1411