1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/mipsmtregs.h> 27 #include <asm/msa.h> 28 #include <asm/watch.h> 29 #include <asm/elf.h> 30 #include <asm/spram.h> 31 #include <asm/uaccess.h> 32 33 static int mips_fpu_disabled; 34 35 static int __init fpu_disable(char *s) 36 { 37 cpu_data[0].options &= ~MIPS_CPU_FPU; 38 mips_fpu_disabled = 1; 39 40 return 1; 41 } 42 43 __setup("nofpu", fpu_disable); 44 45 int mips_dsp_disabled; 46 47 static int __init dsp_disable(char *s) 48 { 49 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 50 mips_dsp_disabled = 1; 51 52 return 1; 53 } 54 55 __setup("nodsp", dsp_disable); 56 57 static int mips_htw_disabled; 58 59 static int __init htw_disable(char *s) 60 { 61 mips_htw_disabled = 1; 62 cpu_data[0].options &= ~MIPS_CPU_HTW; 63 write_c0_pwctl(read_c0_pwctl() & 64 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 65 66 return 1; 67 } 68 69 __setup("nohtw", htw_disable); 70 71 static inline void check_errata(void) 72 { 73 struct cpuinfo_mips *c = ¤t_cpu_data; 74 75 switch (current_cpu_type()) { 76 case CPU_34K: 77 /* 78 * Erratum "RPS May Cause Incorrect Instruction Execution" 79 * This code only handles VPE0, any SMP/RTOS code 80 * making use of VPE1 will be responsable for that VPE. 81 */ 82 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 83 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 84 break; 85 default: 86 break; 87 } 88 } 89 90 void __init check_bugs32(void) 91 { 92 check_errata(); 93 } 94 95 /* 96 * Probe whether cpu has config register by trying to play with 97 * alternate cache bit and see whether it matters. 98 * It's used by cpu_probe to distinguish between R3000A and R3081. 99 */ 100 static inline int cpu_has_confreg(void) 101 { 102 #ifdef CONFIG_CPU_R3000 103 extern unsigned long r3k_cache_size(unsigned long); 104 unsigned long size1, size2; 105 unsigned long cfg = read_c0_conf(); 106 107 size1 = r3k_cache_size(ST0_ISC); 108 write_c0_conf(cfg ^ R30XX_CONF_AC); 109 size2 = r3k_cache_size(ST0_ISC); 110 write_c0_conf(cfg); 111 return size1 != size2; 112 #else 113 return 0; 114 #endif 115 } 116 117 static inline void set_elf_platform(int cpu, const char *plat) 118 { 119 if (cpu == 0) 120 __elf_platform = plat; 121 } 122 123 /* 124 * Get the FPU Implementation/Revision. 125 */ 126 static inline unsigned long cpu_get_fpu_id(void) 127 { 128 unsigned long tmp, fpu_id; 129 130 tmp = read_c0_status(); 131 __enable_fpu(FPU_AS_IS); 132 fpu_id = read_32bit_cp1_register(CP1_REVISION); 133 write_c0_status(tmp); 134 return fpu_id; 135 } 136 137 /* 138 * Check the CPU has an FPU the official way. 139 */ 140 static inline int __cpu_has_fpu(void) 141 { 142 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); 143 } 144 145 static inline unsigned long cpu_get_msa_id(void) 146 { 147 unsigned long status, msa_id; 148 149 status = read_c0_status(); 150 __enable_fpu(FPU_64BIT); 151 enable_msa(); 152 msa_id = read_msa_ir(); 153 disable_msa(); 154 write_c0_status(status); 155 return msa_id; 156 } 157 158 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 159 { 160 #ifdef __NEED_VMBITS_PROBE 161 write_c0_entryhi(0x3fffffffffffe000ULL); 162 back_to_back_c0_hazard(); 163 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 164 #endif 165 } 166 167 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 168 { 169 switch (isa) { 170 case MIPS_CPU_ISA_M64R2: 171 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 172 case MIPS_CPU_ISA_M64R1: 173 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 174 case MIPS_CPU_ISA_V: 175 c->isa_level |= MIPS_CPU_ISA_V; 176 case MIPS_CPU_ISA_IV: 177 c->isa_level |= MIPS_CPU_ISA_IV; 178 case MIPS_CPU_ISA_III: 179 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 180 break; 181 182 case MIPS_CPU_ISA_M32R2: 183 c->isa_level |= MIPS_CPU_ISA_M32R2; 184 case MIPS_CPU_ISA_M32R1: 185 c->isa_level |= MIPS_CPU_ISA_M32R1; 186 case MIPS_CPU_ISA_II: 187 c->isa_level |= MIPS_CPU_ISA_II; 188 break; 189 } 190 } 191 192 static char unknown_isa[] = KERN_ERR \ 193 "Unsupported ISA type, c0.config0: %d."; 194 195 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 196 { 197 unsigned int config6; 198 199 /* It's implementation dependent how the FTLB can be enabled */ 200 switch (c->cputype) { 201 case CPU_PROAPTIV: 202 case CPU_P5600: 203 /* proAptiv & related cores use Config6 to enable the FTLB */ 204 config6 = read_c0_config6(); 205 if (enable) 206 /* Enable FTLB */ 207 write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 208 else 209 /* Disable FTLB */ 210 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 211 back_to_back_c0_hazard(); 212 break; 213 } 214 } 215 216 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 217 { 218 unsigned int config0; 219 int isa; 220 221 config0 = read_c0_config(); 222 223 /* 224 * Look for Standard TLB or Dual VTLB and FTLB 225 */ 226 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 227 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 228 c->options |= MIPS_CPU_TLB; 229 230 isa = (config0 & MIPS_CONF_AT) >> 13; 231 switch (isa) { 232 case 0: 233 switch ((config0 & MIPS_CONF_AR) >> 10) { 234 case 0: 235 set_isa(c, MIPS_CPU_ISA_M32R1); 236 break; 237 case 1: 238 set_isa(c, MIPS_CPU_ISA_M32R2); 239 break; 240 default: 241 goto unknown; 242 } 243 break; 244 case 2: 245 switch ((config0 & MIPS_CONF_AR) >> 10) { 246 case 0: 247 set_isa(c, MIPS_CPU_ISA_M64R1); 248 break; 249 case 1: 250 set_isa(c, MIPS_CPU_ISA_M64R2); 251 break; 252 default: 253 goto unknown; 254 } 255 break; 256 default: 257 goto unknown; 258 } 259 260 return config0 & MIPS_CONF_M; 261 262 unknown: 263 panic(unknown_isa, config0); 264 } 265 266 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 267 { 268 unsigned int config1; 269 270 config1 = read_c0_config1(); 271 272 if (config1 & MIPS_CONF1_MD) 273 c->ases |= MIPS_ASE_MDMX; 274 if (config1 & MIPS_CONF1_WR) 275 c->options |= MIPS_CPU_WATCH; 276 if (config1 & MIPS_CONF1_CA) 277 c->ases |= MIPS_ASE_MIPS16; 278 if (config1 & MIPS_CONF1_EP) 279 c->options |= MIPS_CPU_EJTAG; 280 if (config1 & MIPS_CONF1_FP) { 281 c->options |= MIPS_CPU_FPU; 282 c->options |= MIPS_CPU_32FPR; 283 } 284 if (cpu_has_tlb) { 285 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 286 c->tlbsizevtlb = c->tlbsize; 287 c->tlbsizeftlbsets = 0; 288 } 289 290 return config1 & MIPS_CONF_M; 291 } 292 293 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 294 { 295 unsigned int config2; 296 297 config2 = read_c0_config2(); 298 299 if (config2 & MIPS_CONF2_SL) 300 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 301 302 return config2 & MIPS_CONF_M; 303 } 304 305 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 306 { 307 unsigned int config3; 308 309 config3 = read_c0_config3(); 310 311 if (config3 & MIPS_CONF3_SM) { 312 c->ases |= MIPS_ASE_SMARTMIPS; 313 c->options |= MIPS_CPU_RIXI; 314 } 315 if (config3 & MIPS_CONF3_RXI) 316 c->options |= MIPS_CPU_RIXI; 317 if (config3 & MIPS_CONF3_DSP) 318 c->ases |= MIPS_ASE_DSP; 319 if (config3 & MIPS_CONF3_DSP2P) 320 c->ases |= MIPS_ASE_DSP2P; 321 if (config3 & MIPS_CONF3_VINT) 322 c->options |= MIPS_CPU_VINT; 323 if (config3 & MIPS_CONF3_VEIC) 324 c->options |= MIPS_CPU_VEIC; 325 if (config3 & MIPS_CONF3_MT) 326 c->ases |= MIPS_ASE_MIPSMT; 327 if (config3 & MIPS_CONF3_ULRI) 328 c->options |= MIPS_CPU_ULRI; 329 if (config3 & MIPS_CONF3_ISA) 330 c->options |= MIPS_CPU_MICROMIPS; 331 if (config3 & MIPS_CONF3_VZ) 332 c->ases |= MIPS_ASE_VZ; 333 if (config3 & MIPS_CONF3_SC) 334 c->options |= MIPS_CPU_SEGMENTS; 335 if (config3 & MIPS_CONF3_MSA) 336 c->ases |= MIPS_ASE_MSA; 337 /* Only tested on 32-bit cores */ 338 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) 339 c->options |= MIPS_CPU_HTW; 340 341 return config3 & MIPS_CONF_M; 342 } 343 344 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 345 { 346 unsigned int config4; 347 unsigned int newcf4; 348 unsigned int mmuextdef; 349 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 350 351 config4 = read_c0_config4(); 352 353 if (cpu_has_tlb) { 354 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 355 c->options |= MIPS_CPU_TLBINV; 356 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 357 switch (mmuextdef) { 358 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 359 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 360 c->tlbsizevtlb = c->tlbsize; 361 break; 362 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 363 c->tlbsizevtlb += 364 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 365 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 366 c->tlbsize = c->tlbsizevtlb; 367 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 368 /* fall through */ 369 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 370 newcf4 = (config4 & ~ftlb_page) | 371 (page_size_ftlb(mmuextdef) << 372 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 373 write_c0_config4(newcf4); 374 back_to_back_c0_hazard(); 375 config4 = read_c0_config4(); 376 if (config4 != newcf4) { 377 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 378 PAGE_SIZE, config4); 379 /* Switch FTLB off */ 380 set_ftlb_enable(c, 0); 381 break; 382 } 383 c->tlbsizeftlbsets = 1 << 384 ((config4 & MIPS_CONF4_FTLBSETS) >> 385 MIPS_CONF4_FTLBSETS_SHIFT); 386 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 387 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 388 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 389 break; 390 } 391 } 392 393 c->kscratch_mask = (config4 >> 16) & 0xff; 394 395 return config4 & MIPS_CONF_M; 396 } 397 398 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 399 { 400 unsigned int config5; 401 402 config5 = read_c0_config5(); 403 config5 &= ~MIPS_CONF5_UFR; 404 write_c0_config5(config5); 405 406 if (config5 & MIPS_CONF5_EVA) 407 c->options |= MIPS_CPU_EVA; 408 if (config5 & MIPS_CONF5_MRP) 409 c->options |= MIPS_CPU_MAAR; 410 411 return config5 & MIPS_CONF_M; 412 } 413 414 static void decode_configs(struct cpuinfo_mips *c) 415 { 416 int ok; 417 418 /* MIPS32 or MIPS64 compliant CPU. */ 419 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 420 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 421 422 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 423 424 /* Enable FTLB if present */ 425 set_ftlb_enable(c, 1); 426 427 ok = decode_config0(c); /* Read Config registers. */ 428 BUG_ON(!ok); /* Arch spec violation! */ 429 if (ok) 430 ok = decode_config1(c); 431 if (ok) 432 ok = decode_config2(c); 433 if (ok) 434 ok = decode_config3(c); 435 if (ok) 436 ok = decode_config4(c); 437 if (ok) 438 ok = decode_config5(c); 439 440 mips_probe_watch_registers(c); 441 442 if (cpu_has_rixi) { 443 /* Enable the RIXI exceptions */ 444 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); 445 back_to_back_c0_hazard(); 446 /* Verify the IEC bit is set */ 447 if (read_c0_pagegrain() & PG_IEC) 448 c->options |= MIPS_CPU_RIXIEX; 449 } 450 451 #ifndef CONFIG_MIPS_CPS 452 if (cpu_has_mips_r2) { 453 c->core = get_ebase_cpunum(); 454 if (cpu_has_mipsmt) 455 c->core >>= fls(core_nvpes()) - 1; 456 } 457 #endif 458 } 459 460 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 461 | MIPS_CPU_COUNTER) 462 463 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 464 { 465 switch (c->processor_id & PRID_IMP_MASK) { 466 case PRID_IMP_R2000: 467 c->cputype = CPU_R2000; 468 __cpu_name[cpu] = "R2000"; 469 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 470 MIPS_CPU_NOFPUEX; 471 if (__cpu_has_fpu()) 472 c->options |= MIPS_CPU_FPU; 473 c->tlbsize = 64; 474 break; 475 case PRID_IMP_R3000: 476 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 477 if (cpu_has_confreg()) { 478 c->cputype = CPU_R3081E; 479 __cpu_name[cpu] = "R3081"; 480 } else { 481 c->cputype = CPU_R3000A; 482 __cpu_name[cpu] = "R3000A"; 483 } 484 } else { 485 c->cputype = CPU_R3000; 486 __cpu_name[cpu] = "R3000"; 487 } 488 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 489 MIPS_CPU_NOFPUEX; 490 if (__cpu_has_fpu()) 491 c->options |= MIPS_CPU_FPU; 492 c->tlbsize = 64; 493 break; 494 case PRID_IMP_R4000: 495 if (read_c0_config() & CONF_SC) { 496 if ((c->processor_id & PRID_REV_MASK) >= 497 PRID_REV_R4400) { 498 c->cputype = CPU_R4400PC; 499 __cpu_name[cpu] = "R4400PC"; 500 } else { 501 c->cputype = CPU_R4000PC; 502 __cpu_name[cpu] = "R4000PC"; 503 } 504 } else { 505 int cca = read_c0_config() & CONF_CM_CMASK; 506 int mc; 507 508 /* 509 * SC and MC versions can't be reliably told apart, 510 * but only the latter support coherent caching 511 * modes so assume the firmware has set the KSEG0 512 * coherency attribute reasonably (if uncached, we 513 * assume SC). 514 */ 515 switch (cca) { 516 case CONF_CM_CACHABLE_CE: 517 case CONF_CM_CACHABLE_COW: 518 case CONF_CM_CACHABLE_CUW: 519 mc = 1; 520 break; 521 default: 522 mc = 0; 523 break; 524 } 525 if ((c->processor_id & PRID_REV_MASK) >= 526 PRID_REV_R4400) { 527 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 528 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 529 } else { 530 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 531 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 532 } 533 } 534 535 set_isa(c, MIPS_CPU_ISA_III); 536 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 537 MIPS_CPU_WATCH | MIPS_CPU_VCE | 538 MIPS_CPU_LLSC; 539 c->tlbsize = 48; 540 break; 541 case PRID_IMP_VR41XX: 542 set_isa(c, MIPS_CPU_ISA_III); 543 c->options = R4K_OPTS; 544 c->tlbsize = 32; 545 switch (c->processor_id & 0xf0) { 546 case PRID_REV_VR4111: 547 c->cputype = CPU_VR4111; 548 __cpu_name[cpu] = "NEC VR4111"; 549 break; 550 case PRID_REV_VR4121: 551 c->cputype = CPU_VR4121; 552 __cpu_name[cpu] = "NEC VR4121"; 553 break; 554 case PRID_REV_VR4122: 555 if ((c->processor_id & 0xf) < 0x3) { 556 c->cputype = CPU_VR4122; 557 __cpu_name[cpu] = "NEC VR4122"; 558 } else { 559 c->cputype = CPU_VR4181A; 560 __cpu_name[cpu] = "NEC VR4181A"; 561 } 562 break; 563 case PRID_REV_VR4130: 564 if ((c->processor_id & 0xf) < 0x4) { 565 c->cputype = CPU_VR4131; 566 __cpu_name[cpu] = "NEC VR4131"; 567 } else { 568 c->cputype = CPU_VR4133; 569 c->options |= MIPS_CPU_LLSC; 570 __cpu_name[cpu] = "NEC VR4133"; 571 } 572 break; 573 default: 574 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 575 c->cputype = CPU_VR41XX; 576 __cpu_name[cpu] = "NEC Vr41xx"; 577 break; 578 } 579 break; 580 case PRID_IMP_R4300: 581 c->cputype = CPU_R4300; 582 __cpu_name[cpu] = "R4300"; 583 set_isa(c, MIPS_CPU_ISA_III); 584 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 585 MIPS_CPU_LLSC; 586 c->tlbsize = 32; 587 break; 588 case PRID_IMP_R4600: 589 c->cputype = CPU_R4600; 590 __cpu_name[cpu] = "R4600"; 591 set_isa(c, MIPS_CPU_ISA_III); 592 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 593 MIPS_CPU_LLSC; 594 c->tlbsize = 48; 595 break; 596 #if 0 597 case PRID_IMP_R4650: 598 /* 599 * This processor doesn't have an MMU, so it's not 600 * "real easy" to run Linux on it. It is left purely 601 * for documentation. Commented out because it shares 602 * it's c0_prid id number with the TX3900. 603 */ 604 c->cputype = CPU_R4650; 605 __cpu_name[cpu] = "R4650"; 606 set_isa(c, MIPS_CPU_ISA_III); 607 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 608 c->tlbsize = 48; 609 break; 610 #endif 611 case PRID_IMP_TX39: 612 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 613 614 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 615 c->cputype = CPU_TX3927; 616 __cpu_name[cpu] = "TX3927"; 617 c->tlbsize = 64; 618 } else { 619 switch (c->processor_id & PRID_REV_MASK) { 620 case PRID_REV_TX3912: 621 c->cputype = CPU_TX3912; 622 __cpu_name[cpu] = "TX3912"; 623 c->tlbsize = 32; 624 break; 625 case PRID_REV_TX3922: 626 c->cputype = CPU_TX3922; 627 __cpu_name[cpu] = "TX3922"; 628 c->tlbsize = 64; 629 break; 630 } 631 } 632 break; 633 case PRID_IMP_R4700: 634 c->cputype = CPU_R4700; 635 __cpu_name[cpu] = "R4700"; 636 set_isa(c, MIPS_CPU_ISA_III); 637 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 638 MIPS_CPU_LLSC; 639 c->tlbsize = 48; 640 break; 641 case PRID_IMP_TX49: 642 c->cputype = CPU_TX49XX; 643 __cpu_name[cpu] = "R49XX"; 644 set_isa(c, MIPS_CPU_ISA_III); 645 c->options = R4K_OPTS | MIPS_CPU_LLSC; 646 if (!(c->processor_id & 0x08)) 647 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 648 c->tlbsize = 48; 649 break; 650 case PRID_IMP_R5000: 651 c->cputype = CPU_R5000; 652 __cpu_name[cpu] = "R5000"; 653 set_isa(c, MIPS_CPU_ISA_IV); 654 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 655 MIPS_CPU_LLSC; 656 c->tlbsize = 48; 657 break; 658 case PRID_IMP_R5432: 659 c->cputype = CPU_R5432; 660 __cpu_name[cpu] = "R5432"; 661 set_isa(c, MIPS_CPU_ISA_IV); 662 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 663 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 664 c->tlbsize = 48; 665 break; 666 case PRID_IMP_R5500: 667 c->cputype = CPU_R5500; 668 __cpu_name[cpu] = "R5500"; 669 set_isa(c, MIPS_CPU_ISA_IV); 670 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 671 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 672 c->tlbsize = 48; 673 break; 674 case PRID_IMP_NEVADA: 675 c->cputype = CPU_NEVADA; 676 __cpu_name[cpu] = "Nevada"; 677 set_isa(c, MIPS_CPU_ISA_IV); 678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 679 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 680 c->tlbsize = 48; 681 break; 682 case PRID_IMP_R6000: 683 c->cputype = CPU_R6000; 684 __cpu_name[cpu] = "R6000"; 685 set_isa(c, MIPS_CPU_ISA_II); 686 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 687 MIPS_CPU_LLSC; 688 c->tlbsize = 32; 689 break; 690 case PRID_IMP_R6000A: 691 c->cputype = CPU_R6000A; 692 __cpu_name[cpu] = "R6000A"; 693 set_isa(c, MIPS_CPU_ISA_II); 694 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 695 MIPS_CPU_LLSC; 696 c->tlbsize = 32; 697 break; 698 case PRID_IMP_RM7000: 699 c->cputype = CPU_RM7000; 700 __cpu_name[cpu] = "RM7000"; 701 set_isa(c, MIPS_CPU_ISA_IV); 702 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 703 MIPS_CPU_LLSC; 704 /* 705 * Undocumented RM7000: Bit 29 in the info register of 706 * the RM7000 v2.0 indicates if the TLB has 48 or 64 707 * entries. 708 * 709 * 29 1 => 64 entry JTLB 710 * 0 => 48 entry JTLB 711 */ 712 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 713 break; 714 case PRID_IMP_R8000: 715 c->cputype = CPU_R8000; 716 __cpu_name[cpu] = "RM8000"; 717 set_isa(c, MIPS_CPU_ISA_IV); 718 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 719 MIPS_CPU_FPU | MIPS_CPU_32FPR | 720 MIPS_CPU_LLSC; 721 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 722 break; 723 case PRID_IMP_R10000: 724 c->cputype = CPU_R10000; 725 __cpu_name[cpu] = "R10000"; 726 set_isa(c, MIPS_CPU_ISA_IV); 727 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 728 MIPS_CPU_FPU | MIPS_CPU_32FPR | 729 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 730 MIPS_CPU_LLSC; 731 c->tlbsize = 64; 732 break; 733 case PRID_IMP_R12000: 734 c->cputype = CPU_R12000; 735 __cpu_name[cpu] = "R12000"; 736 set_isa(c, MIPS_CPU_ISA_IV); 737 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 738 MIPS_CPU_FPU | MIPS_CPU_32FPR | 739 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 740 MIPS_CPU_LLSC; 741 c->tlbsize = 64; 742 break; 743 case PRID_IMP_R14000: 744 c->cputype = CPU_R14000; 745 __cpu_name[cpu] = "R14000"; 746 set_isa(c, MIPS_CPU_ISA_IV); 747 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 748 MIPS_CPU_FPU | MIPS_CPU_32FPR | 749 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 750 MIPS_CPU_LLSC; 751 c->tlbsize = 64; 752 break; 753 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 754 switch (c->processor_id & PRID_REV_MASK) { 755 case PRID_REV_LOONGSON2E: 756 c->cputype = CPU_LOONGSON2; 757 __cpu_name[cpu] = "ICT Loongson-2"; 758 set_elf_platform(cpu, "loongson2e"); 759 break; 760 case PRID_REV_LOONGSON2F: 761 c->cputype = CPU_LOONGSON2; 762 __cpu_name[cpu] = "ICT Loongson-2"; 763 set_elf_platform(cpu, "loongson2f"); 764 break; 765 case PRID_REV_LOONGSON3A: 766 c->cputype = CPU_LOONGSON3; 767 __cpu_name[cpu] = "ICT Loongson-3"; 768 set_elf_platform(cpu, "loongson3a"); 769 break; 770 case PRID_REV_LOONGSON3B_R1: 771 case PRID_REV_LOONGSON3B_R2: 772 c->cputype = CPU_LOONGSON3; 773 __cpu_name[cpu] = "ICT Loongson-3"; 774 set_elf_platform(cpu, "loongson3b"); 775 break; 776 } 777 778 set_isa(c, MIPS_CPU_ISA_III); 779 c->options = R4K_OPTS | 780 MIPS_CPU_FPU | MIPS_CPU_LLSC | 781 MIPS_CPU_32FPR; 782 c->tlbsize = 64; 783 break; 784 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 785 decode_configs(c); 786 787 c->cputype = CPU_LOONGSON1; 788 789 switch (c->processor_id & PRID_REV_MASK) { 790 case PRID_REV_LOONGSON1B: 791 __cpu_name[cpu] = "Loongson 1B"; 792 break; 793 } 794 795 break; 796 } 797 } 798 799 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 800 { 801 switch (c->processor_id & PRID_IMP_MASK) { 802 case PRID_IMP_4KC: 803 c->cputype = CPU_4KC; 804 __cpu_name[cpu] = "MIPS 4Kc"; 805 break; 806 case PRID_IMP_4KEC: 807 case PRID_IMP_4KECR2: 808 c->cputype = CPU_4KEC; 809 __cpu_name[cpu] = "MIPS 4KEc"; 810 break; 811 case PRID_IMP_4KSC: 812 case PRID_IMP_4KSD: 813 c->cputype = CPU_4KSC; 814 __cpu_name[cpu] = "MIPS 4KSc"; 815 break; 816 case PRID_IMP_5KC: 817 c->cputype = CPU_5KC; 818 __cpu_name[cpu] = "MIPS 5Kc"; 819 break; 820 case PRID_IMP_5KE: 821 c->cputype = CPU_5KE; 822 __cpu_name[cpu] = "MIPS 5KE"; 823 break; 824 case PRID_IMP_20KC: 825 c->cputype = CPU_20KC; 826 __cpu_name[cpu] = "MIPS 20Kc"; 827 break; 828 case PRID_IMP_24K: 829 c->cputype = CPU_24K; 830 __cpu_name[cpu] = "MIPS 24Kc"; 831 break; 832 case PRID_IMP_24KE: 833 c->cputype = CPU_24K; 834 __cpu_name[cpu] = "MIPS 24KEc"; 835 break; 836 case PRID_IMP_25KF: 837 c->cputype = CPU_25KF; 838 __cpu_name[cpu] = "MIPS 25Kc"; 839 break; 840 case PRID_IMP_34K: 841 c->cputype = CPU_34K; 842 __cpu_name[cpu] = "MIPS 34Kc"; 843 break; 844 case PRID_IMP_74K: 845 c->cputype = CPU_74K; 846 __cpu_name[cpu] = "MIPS 74Kc"; 847 break; 848 case PRID_IMP_M14KC: 849 c->cputype = CPU_M14KC; 850 __cpu_name[cpu] = "MIPS M14Kc"; 851 break; 852 case PRID_IMP_M14KEC: 853 c->cputype = CPU_M14KEC; 854 __cpu_name[cpu] = "MIPS M14KEc"; 855 break; 856 case PRID_IMP_1004K: 857 c->cputype = CPU_1004K; 858 __cpu_name[cpu] = "MIPS 1004Kc"; 859 break; 860 case PRID_IMP_1074K: 861 c->cputype = CPU_1074K; 862 __cpu_name[cpu] = "MIPS 1074Kc"; 863 break; 864 case PRID_IMP_INTERAPTIV_UP: 865 c->cputype = CPU_INTERAPTIV; 866 __cpu_name[cpu] = "MIPS interAptiv"; 867 break; 868 case PRID_IMP_INTERAPTIV_MP: 869 c->cputype = CPU_INTERAPTIV; 870 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 871 break; 872 case PRID_IMP_PROAPTIV_UP: 873 c->cputype = CPU_PROAPTIV; 874 __cpu_name[cpu] = "MIPS proAptiv"; 875 break; 876 case PRID_IMP_PROAPTIV_MP: 877 c->cputype = CPU_PROAPTIV; 878 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 879 break; 880 case PRID_IMP_P5600: 881 c->cputype = CPU_P5600; 882 __cpu_name[cpu] = "MIPS P5600"; 883 break; 884 case PRID_IMP_M5150: 885 c->cputype = CPU_M5150; 886 __cpu_name[cpu] = "MIPS M5150"; 887 break; 888 } 889 890 decode_configs(c); 891 892 spram_config(); 893 } 894 895 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 896 { 897 decode_configs(c); 898 switch (c->processor_id & PRID_IMP_MASK) { 899 case PRID_IMP_AU1_REV1: 900 case PRID_IMP_AU1_REV2: 901 c->cputype = CPU_ALCHEMY; 902 switch ((c->processor_id >> 24) & 0xff) { 903 case 0: 904 __cpu_name[cpu] = "Au1000"; 905 break; 906 case 1: 907 __cpu_name[cpu] = "Au1500"; 908 break; 909 case 2: 910 __cpu_name[cpu] = "Au1100"; 911 break; 912 case 3: 913 __cpu_name[cpu] = "Au1550"; 914 break; 915 case 4: 916 __cpu_name[cpu] = "Au1200"; 917 if ((c->processor_id & PRID_REV_MASK) == 2) 918 __cpu_name[cpu] = "Au1250"; 919 break; 920 case 5: 921 __cpu_name[cpu] = "Au1210"; 922 break; 923 default: 924 __cpu_name[cpu] = "Au1xxx"; 925 break; 926 } 927 break; 928 } 929 } 930 931 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 932 { 933 decode_configs(c); 934 935 switch (c->processor_id & PRID_IMP_MASK) { 936 case PRID_IMP_SB1: 937 c->cputype = CPU_SB1; 938 __cpu_name[cpu] = "SiByte SB1"; 939 /* FPU in pass1 is known to have issues. */ 940 if ((c->processor_id & PRID_REV_MASK) < 0x02) 941 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 942 break; 943 case PRID_IMP_SB1A: 944 c->cputype = CPU_SB1A; 945 __cpu_name[cpu] = "SiByte SB1A"; 946 break; 947 } 948 } 949 950 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 951 { 952 decode_configs(c); 953 switch (c->processor_id & PRID_IMP_MASK) { 954 case PRID_IMP_SR71000: 955 c->cputype = CPU_SR71000; 956 __cpu_name[cpu] = "Sandcraft SR71000"; 957 c->scache.ways = 8; 958 c->tlbsize = 64; 959 break; 960 } 961 } 962 963 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 964 { 965 decode_configs(c); 966 switch (c->processor_id & PRID_IMP_MASK) { 967 case PRID_IMP_PR4450: 968 c->cputype = CPU_PR4450; 969 __cpu_name[cpu] = "Philips PR4450"; 970 set_isa(c, MIPS_CPU_ISA_M32R1); 971 break; 972 } 973 } 974 975 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 976 { 977 decode_configs(c); 978 switch (c->processor_id & PRID_IMP_MASK) { 979 case PRID_IMP_BMIPS32_REV4: 980 case PRID_IMP_BMIPS32_REV8: 981 c->cputype = CPU_BMIPS32; 982 __cpu_name[cpu] = "Broadcom BMIPS32"; 983 set_elf_platform(cpu, "bmips32"); 984 break; 985 case PRID_IMP_BMIPS3300: 986 case PRID_IMP_BMIPS3300_ALT: 987 case PRID_IMP_BMIPS3300_BUG: 988 c->cputype = CPU_BMIPS3300; 989 __cpu_name[cpu] = "Broadcom BMIPS3300"; 990 set_elf_platform(cpu, "bmips3300"); 991 break; 992 case PRID_IMP_BMIPS43XX: { 993 int rev = c->processor_id & PRID_REV_MASK; 994 995 if (rev >= PRID_REV_BMIPS4380_LO && 996 rev <= PRID_REV_BMIPS4380_HI) { 997 c->cputype = CPU_BMIPS4380; 998 __cpu_name[cpu] = "Broadcom BMIPS4380"; 999 set_elf_platform(cpu, "bmips4380"); 1000 } else { 1001 c->cputype = CPU_BMIPS4350; 1002 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1003 set_elf_platform(cpu, "bmips4350"); 1004 } 1005 break; 1006 } 1007 case PRID_IMP_BMIPS5000: 1008 c->cputype = CPU_BMIPS5000; 1009 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1010 set_elf_platform(cpu, "bmips5000"); 1011 c->options |= MIPS_CPU_ULRI; 1012 break; 1013 } 1014 } 1015 1016 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1017 { 1018 decode_configs(c); 1019 switch (c->processor_id & PRID_IMP_MASK) { 1020 case PRID_IMP_CAVIUM_CN38XX: 1021 case PRID_IMP_CAVIUM_CN31XX: 1022 case PRID_IMP_CAVIUM_CN30XX: 1023 c->cputype = CPU_CAVIUM_OCTEON; 1024 __cpu_name[cpu] = "Cavium Octeon"; 1025 goto platform; 1026 case PRID_IMP_CAVIUM_CN58XX: 1027 case PRID_IMP_CAVIUM_CN56XX: 1028 case PRID_IMP_CAVIUM_CN50XX: 1029 case PRID_IMP_CAVIUM_CN52XX: 1030 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1031 __cpu_name[cpu] = "Cavium Octeon+"; 1032 platform: 1033 set_elf_platform(cpu, "octeon"); 1034 break; 1035 case PRID_IMP_CAVIUM_CN61XX: 1036 case PRID_IMP_CAVIUM_CN63XX: 1037 case PRID_IMP_CAVIUM_CN66XX: 1038 case PRID_IMP_CAVIUM_CN68XX: 1039 case PRID_IMP_CAVIUM_CNF71XX: 1040 c->cputype = CPU_CAVIUM_OCTEON2; 1041 __cpu_name[cpu] = "Cavium Octeon II"; 1042 set_elf_platform(cpu, "octeon2"); 1043 break; 1044 case PRID_IMP_CAVIUM_CN70XX: 1045 case PRID_IMP_CAVIUM_CN78XX: 1046 c->cputype = CPU_CAVIUM_OCTEON3; 1047 __cpu_name[cpu] = "Cavium Octeon III"; 1048 set_elf_platform(cpu, "octeon3"); 1049 break; 1050 default: 1051 printk(KERN_INFO "Unknown Octeon chip!\n"); 1052 c->cputype = CPU_UNKNOWN; 1053 break; 1054 } 1055 } 1056 1057 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1058 { 1059 decode_configs(c); 1060 /* JZRISC does not implement the CP0 counter. */ 1061 c->options &= ~MIPS_CPU_COUNTER; 1062 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1063 switch (c->processor_id & PRID_IMP_MASK) { 1064 case PRID_IMP_JZRISC: 1065 c->cputype = CPU_JZRISC; 1066 __cpu_name[cpu] = "Ingenic JZRISC"; 1067 break; 1068 default: 1069 panic("Unknown Ingenic Processor ID!"); 1070 break; 1071 } 1072 } 1073 1074 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1075 { 1076 decode_configs(c); 1077 1078 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1079 c->cputype = CPU_ALCHEMY; 1080 __cpu_name[cpu] = "Au1300"; 1081 /* following stuff is not for Alchemy */ 1082 return; 1083 } 1084 1085 c->options = (MIPS_CPU_TLB | 1086 MIPS_CPU_4KEX | 1087 MIPS_CPU_COUNTER | 1088 MIPS_CPU_DIVEC | 1089 MIPS_CPU_WATCH | 1090 MIPS_CPU_EJTAG | 1091 MIPS_CPU_LLSC); 1092 1093 switch (c->processor_id & PRID_IMP_MASK) { 1094 case PRID_IMP_NETLOGIC_XLP2XX: 1095 case PRID_IMP_NETLOGIC_XLP9XX: 1096 case PRID_IMP_NETLOGIC_XLP5XX: 1097 c->cputype = CPU_XLP; 1098 __cpu_name[cpu] = "Broadcom XLPII"; 1099 break; 1100 1101 case PRID_IMP_NETLOGIC_XLP8XX: 1102 case PRID_IMP_NETLOGIC_XLP3XX: 1103 c->cputype = CPU_XLP; 1104 __cpu_name[cpu] = "Netlogic XLP"; 1105 break; 1106 1107 case PRID_IMP_NETLOGIC_XLR732: 1108 case PRID_IMP_NETLOGIC_XLR716: 1109 case PRID_IMP_NETLOGIC_XLR532: 1110 case PRID_IMP_NETLOGIC_XLR308: 1111 case PRID_IMP_NETLOGIC_XLR532C: 1112 case PRID_IMP_NETLOGIC_XLR516C: 1113 case PRID_IMP_NETLOGIC_XLR508C: 1114 case PRID_IMP_NETLOGIC_XLR308C: 1115 c->cputype = CPU_XLR; 1116 __cpu_name[cpu] = "Netlogic XLR"; 1117 break; 1118 1119 case PRID_IMP_NETLOGIC_XLS608: 1120 case PRID_IMP_NETLOGIC_XLS408: 1121 case PRID_IMP_NETLOGIC_XLS404: 1122 case PRID_IMP_NETLOGIC_XLS208: 1123 case PRID_IMP_NETLOGIC_XLS204: 1124 case PRID_IMP_NETLOGIC_XLS108: 1125 case PRID_IMP_NETLOGIC_XLS104: 1126 case PRID_IMP_NETLOGIC_XLS616B: 1127 case PRID_IMP_NETLOGIC_XLS608B: 1128 case PRID_IMP_NETLOGIC_XLS416B: 1129 case PRID_IMP_NETLOGIC_XLS412B: 1130 case PRID_IMP_NETLOGIC_XLS408B: 1131 case PRID_IMP_NETLOGIC_XLS404B: 1132 c->cputype = CPU_XLR; 1133 __cpu_name[cpu] = "Netlogic XLS"; 1134 break; 1135 1136 default: 1137 pr_info("Unknown Netlogic chip id [%02x]!\n", 1138 c->processor_id); 1139 c->cputype = CPU_XLR; 1140 break; 1141 } 1142 1143 if (c->cputype == CPU_XLP) { 1144 set_isa(c, MIPS_CPU_ISA_M64R2); 1145 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1146 /* This will be updated again after all threads are woken up */ 1147 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1148 } else { 1149 set_isa(c, MIPS_CPU_ISA_M64R1); 1150 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1151 } 1152 c->kscratch_mask = 0xf; 1153 } 1154 1155 #ifdef CONFIG_64BIT 1156 /* For use by uaccess.h */ 1157 u64 __ua_limit; 1158 EXPORT_SYMBOL(__ua_limit); 1159 #endif 1160 1161 const char *__cpu_name[NR_CPUS]; 1162 const char *__elf_platform; 1163 1164 void cpu_probe(void) 1165 { 1166 struct cpuinfo_mips *c = ¤t_cpu_data; 1167 unsigned int cpu = smp_processor_id(); 1168 1169 c->processor_id = PRID_IMP_UNKNOWN; 1170 c->fpu_id = FPIR_IMP_NONE; 1171 c->cputype = CPU_UNKNOWN; 1172 1173 c->processor_id = read_c0_prid(); 1174 switch (c->processor_id & PRID_COMP_MASK) { 1175 case PRID_COMP_LEGACY: 1176 cpu_probe_legacy(c, cpu); 1177 break; 1178 case PRID_COMP_MIPS: 1179 cpu_probe_mips(c, cpu); 1180 break; 1181 case PRID_COMP_ALCHEMY: 1182 cpu_probe_alchemy(c, cpu); 1183 break; 1184 case PRID_COMP_SIBYTE: 1185 cpu_probe_sibyte(c, cpu); 1186 break; 1187 case PRID_COMP_BROADCOM: 1188 cpu_probe_broadcom(c, cpu); 1189 break; 1190 case PRID_COMP_SANDCRAFT: 1191 cpu_probe_sandcraft(c, cpu); 1192 break; 1193 case PRID_COMP_NXP: 1194 cpu_probe_nxp(c, cpu); 1195 break; 1196 case PRID_COMP_CAVIUM: 1197 cpu_probe_cavium(c, cpu); 1198 break; 1199 case PRID_COMP_INGENIC: 1200 cpu_probe_ingenic(c, cpu); 1201 break; 1202 case PRID_COMP_NETLOGIC: 1203 cpu_probe_netlogic(c, cpu); 1204 break; 1205 } 1206 1207 BUG_ON(!__cpu_name[cpu]); 1208 BUG_ON(c->cputype == CPU_UNKNOWN); 1209 1210 /* 1211 * Platform code can force the cpu type to optimize code 1212 * generation. In that case be sure the cpu type is correctly 1213 * manually setup otherwise it could trigger some nasty bugs. 1214 */ 1215 BUG_ON(current_cpu_type() != c->cputype); 1216 1217 if (mips_fpu_disabled) 1218 c->options &= ~MIPS_CPU_FPU; 1219 1220 if (mips_dsp_disabled) 1221 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1222 1223 if (mips_htw_disabled) { 1224 c->options &= ~MIPS_CPU_HTW; 1225 write_c0_pwctl(read_c0_pwctl() & 1226 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1227 } 1228 1229 if (c->options & MIPS_CPU_FPU) { 1230 c->fpu_id = cpu_get_fpu_id(); 1231 1232 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1233 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1234 if (c->fpu_id & MIPS_FPIR_3D) 1235 c->ases |= MIPS_ASE_MIPS3D; 1236 } 1237 } 1238 1239 if (cpu_has_mips_r2) { 1240 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1241 /* R2 has Performance Counter Interrupt indicator */ 1242 c->options |= MIPS_CPU_PCI; 1243 } 1244 else 1245 c->srsets = 1; 1246 1247 if (cpu_has_msa) { 1248 c->msa_id = cpu_get_msa_id(); 1249 WARN(c->msa_id & MSA_IR_WRPF, 1250 "Vector register partitioning unimplemented!"); 1251 } 1252 1253 cpu_probe_vmbits(c); 1254 1255 #ifdef CONFIG_64BIT 1256 if (cpu == 0) 1257 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1258 #endif 1259 } 1260 1261 void cpu_report(void) 1262 { 1263 struct cpuinfo_mips *c = ¤t_cpu_data; 1264 1265 pr_info("CPU%d revision is: %08x (%s)\n", 1266 smp_processor_id(), c->processor_id, cpu_name_string()); 1267 if (c->options & MIPS_CPU_FPU) 1268 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1269 if (cpu_has_msa) 1270 pr_info("MSA revision is: %08x\n", c->msa_id); 1271 } 1272