1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Based on linux/arch/mips/kernel/cevt-r4k.c, 7 * linux/arch/mips/jmr3927/rbhma3100/setup.c 8 * 9 * Copyright 2001 MontaVista Software Inc. 10 * Copyright (C) 2000-2001 Toshiba Corporation 11 * Copyright (C) 2007 MIPS Technologies, Inc. 12 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> 13 */ 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <asm/time.h> 18 #include <asm/txx9tmr.h> 19 20 #define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL) 21 #define TIMER_CCD 0 /* 1/2 */ 22 #define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD)) 23 24 struct txx9_clocksource { 25 struct clocksource cs; 26 struct txx9_tmr_reg __iomem *tmrptr; 27 }; 28 29 static cycle_t txx9_cs_read(struct clocksource *cs) 30 { 31 struct txx9_clocksource *txx9_cs = 32 container_of(cs, struct txx9_clocksource, cs); 33 return __raw_readl(&txx9_cs->tmrptr->trr); 34 } 35 36 /* Use 1 bit smaller width to use full bits in that width */ 37 #define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1) 38 39 static struct txx9_clocksource txx9_clocksource = { 40 .cs = { 41 .name = "TXx9", 42 .rating = 200, 43 .read = txx9_cs_read, 44 .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS), 45 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 46 }, 47 }; 48 49 void __init txx9_clocksource_init(unsigned long baseaddr, 50 unsigned int imbusclk) 51 { 52 struct txx9_tmr_reg __iomem *tmrptr; 53 54 clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); 55 56 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 57 __raw_writel(TCR_BASE, &tmrptr->tcr); 58 __raw_writel(0, &tmrptr->tisr); 59 __raw_writel(TIMER_CCD, &tmrptr->ccdr); 60 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); 61 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); 62 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); 63 txx9_clocksource.tmrptr = tmrptr; 64 } 65 66 struct txx9_clock_event_device { 67 struct clock_event_device cd; 68 struct txx9_tmr_reg __iomem *tmrptr; 69 }; 70 71 static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr) 72 { 73 /* stop and reset counter */ 74 __raw_writel(TCR_BASE, &tmrptr->tcr); 75 /* clear pending interrupt */ 76 __raw_writel(0, &tmrptr->tisr); 77 } 78 79 static void txx9tmr_set_mode(enum clock_event_mode mode, 80 struct clock_event_device *evt) 81 { 82 struct txx9_clock_event_device *txx9_cd = 83 container_of(evt, struct txx9_clock_event_device, cd); 84 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; 85 86 txx9tmr_stop_and_clear(tmrptr); 87 switch (mode) { 88 case CLOCK_EVT_MODE_PERIODIC: 89 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, 90 &tmrptr->itmr); 91 /* start timer */ 92 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> 93 evt->shift, 94 &tmrptr->cpra); 95 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); 96 break; 97 case CLOCK_EVT_MODE_SHUTDOWN: 98 case CLOCK_EVT_MODE_UNUSED: 99 __raw_writel(0, &tmrptr->itmr); 100 break; 101 case CLOCK_EVT_MODE_ONESHOT: 102 __raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr); 103 break; 104 case CLOCK_EVT_MODE_RESUME: 105 __raw_writel(TIMER_CCD, &tmrptr->ccdr); 106 __raw_writel(0, &tmrptr->itmr); 107 break; 108 } 109 } 110 111 static int txx9tmr_set_next_event(unsigned long delta, 112 struct clock_event_device *evt) 113 { 114 struct txx9_clock_event_device *txx9_cd = 115 container_of(evt, struct txx9_clock_event_device, cd); 116 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; 117 118 txx9tmr_stop_and_clear(tmrptr); 119 /* start timer */ 120 __raw_writel(delta, &tmrptr->cpra); 121 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); 122 return 0; 123 } 124 125 static struct txx9_clock_event_device txx9_clock_event_device = { 126 .cd = { 127 .name = "TXx9", 128 .features = CLOCK_EVT_FEAT_PERIODIC | 129 CLOCK_EVT_FEAT_ONESHOT, 130 .rating = 200, 131 .set_mode = txx9tmr_set_mode, 132 .set_next_event = txx9tmr_set_next_event, 133 }, 134 }; 135 136 static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) 137 { 138 struct txx9_clock_event_device *txx9_cd = dev_id; 139 struct clock_event_device *cd = &txx9_cd->cd; 140 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; 141 142 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */ 143 cd->event_handler(cd); 144 return IRQ_HANDLED; 145 } 146 147 static struct irqaction txx9tmr_irq = { 148 .handler = txx9tmr_interrupt, 149 .flags = IRQF_PERCPU | IRQF_TIMER, 150 .name = "txx9tmr", 151 .dev_id = &txx9_clock_event_device, 152 }; 153 154 void __init txx9_clockevent_init(unsigned long baseaddr, int irq, 155 unsigned int imbusclk) 156 { 157 struct clock_event_device *cd = &txx9_clock_event_device.cd; 158 struct txx9_tmr_reg __iomem *tmrptr; 159 160 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 161 txx9tmr_stop_and_clear(tmrptr); 162 __raw_writel(TIMER_CCD, &tmrptr->ccdr); 163 __raw_writel(0, &tmrptr->itmr); 164 txx9_clock_event_device.tmrptr = tmrptr; 165 166 clockevent_set_clock(cd, TIMER_CLK(imbusclk)); 167 cd->max_delta_ns = 168 clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd); 169 cd->min_delta_ns = clockevent_delta2ns(0xf, cd); 170 cd->irq = irq; 171 cd->cpumask = cpumask_of(0), 172 clockevents_register_device(cd); 173 setup_irq(irq, &txx9tmr_irq); 174 printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n", 175 baseaddr, irq); 176 } 177 178 void __init txx9_tmr_init(unsigned long baseaddr) 179 { 180 struct txx9_tmr_reg __iomem *tmrptr; 181 182 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 183 /* Start once to make CounterResetEnable effective */ 184 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); 185 /* Stop and reset the counter */ 186 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); 187 __raw_writel(0, &tmrptr->tisr); 188 __raw_writel(0xffffffff, &tmrptr->cpra); 189 __raw_writel(0, &tmrptr->itmr); 190 __raw_writel(0, &tmrptr->ccdr); 191 __raw_writel(0, &tmrptr->pgmr); 192 iounmap(tmrptr); 193 } 194