1 /* 2 * Copyright (C) 2000,2001,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/clockchips.h> 19 #include <linux/interrupt.h> 20 #include <linux/percpu.h> 21 #include <linux/smp.h> 22 #include <linux/irq.h> 23 24 #include <asm/addrspace.h> 25 #include <asm/io.h> 26 #include <asm/time.h> 27 28 #include <asm/sibyte/bcm1480_regs.h> 29 #include <asm/sibyte/sb1250_regs.h> 30 #include <asm/sibyte/bcm1480_int.h> 31 #include <asm/sibyte/bcm1480_scd.h> 32 33 #include <asm/sibyte/sb1250.h> 34 35 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 36 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 37 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 38 39 /* 40 * The general purpose timer ticks at 1MHz independent if 41 * the rest of the system 42 */ 43 static void sibyte_set_mode(enum clock_event_mode mode, 44 struct clock_event_device *evt) 45 { 46 unsigned int cpu = smp_processor_id(); 47 void __iomem *cfg, *init; 48 49 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 50 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 51 52 switch (mode) { 53 case CLOCK_EVT_MODE_PERIODIC: 54 __raw_writeq(0, cfg); 55 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); 56 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 57 cfg); 58 break; 59 60 case CLOCK_EVT_MODE_ONESHOT: 61 /* Stop the timer until we actually program a shot */ 62 case CLOCK_EVT_MODE_SHUTDOWN: 63 __raw_writeq(0, cfg); 64 break; 65 66 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 67 case CLOCK_EVT_MODE_RESUME: 68 ; 69 } 70 } 71 72 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) 73 { 74 unsigned int cpu = smp_processor_id(); 75 void __iomem *cfg, *init; 76 77 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 78 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 79 80 __raw_writeq(0, cfg); 81 __raw_writeq(delta - 1, init); 82 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); 83 84 return 0; 85 } 86 87 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 88 { 89 unsigned int cpu = smp_processor_id(); 90 struct clock_event_device *cd = dev_id; 91 void __iomem *cfg; 92 unsigned long tmode; 93 94 if (cd->mode == CLOCK_EVT_MODE_PERIODIC) 95 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; 96 else 97 tmode = 0; 98 99 /* ACK interrupt */ 100 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 101 ____raw_writeq(tmode, cfg); 102 103 cd->event_handler(cd); 104 105 return IRQ_HANDLED; 106 } 107 108 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); 109 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 110 static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 111 112 void sb1480_clockevent_init(void) 113 { 114 unsigned int cpu = smp_processor_id(); 115 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 116 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); 117 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 118 unsigned char *name = per_cpu(sibyte_hpt_name, cpu); 119 120 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 121 122 sprintf(name, "bcm1480-counter-%d", cpu); 123 cd->name = name; 124 cd->features = CLOCK_EVT_FEAT_PERIODIC | 125 CLOCK_EVT_FEAT_ONESHOT; 126 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 127 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 128 cd->min_delta_ns = clockevent_delta2ns(2, cd); 129 cd->rating = 200; 130 cd->irq = irq; 131 cd->cpumask = cpumask_of(cpu); 132 cd->set_next_event = sibyte_next_event; 133 cd->set_mode = sibyte_set_mode; 134 clockevents_register_device(cd); 135 136 bcm1480_mask_irq(cpu, irq); 137 138 /* 139 * Map the timer interrupt to IP[4] of this cpu 140 */ 141 __raw_writeq(IMR_IP4_VAL, 142 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 143 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 144 145 bcm1480_unmask_irq(cpu, irq); 146 147 action->handler = sibyte_counter_handler; 148 action->flags = IRQF_PERCPU | IRQF_TIMER; 149 action->name = name; 150 action->dev_id = cd; 151 152 irq_set_affinity(irq, cpumask_of(cpu)); 153 setup_irq(irq, action); 154 } 155