xref: /openbmc/linux/arch/mips/kernel/bmips_vec.S (revision 930beb5a) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Reset/NMI/re-entry vectors for BMIPS processors
9 */
10
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/cpu.h>
17#include <asm/regdef.h>
18#include <asm/mipsregs.h>
19#include <asm/stackframe.h>
20#include <asm/addrspace.h>
21#include <asm/hazards.h>
22#include <asm/bmips.h>
23
24	.macro	BARRIER
25	.set	mips32
26	_ssnop
27	_ssnop
28	_ssnop
29	.set	mips0
30	.endm
31
32/***********************************************************************
33 * Alternate CPU1 startup vector for BMIPS4350
34 *
35 * On some systems the bootloader has already started CPU1 and configured
36 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * triggered by the SW1 interrupt.  If that is the case we try to move
38 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
39 ***********************************************************************/
40
41LEAF(bmips_smp_movevec)
42	la	k0, 1f
43	li	k1, CKSEG1
44	or	k0, k1
45	jr	k0
46
471:
48	/* clear IV, pending IPIs */
49	mtc0	zero, CP0_CAUSE
50
51	/* re-enable IRQs to wait for SW1 */
52	li	k0, ST0_IE | ST0_BEV | STATUSF_IP1
53	mtc0	k0, CP0_STATUS
54
55	/* set up CPU1 CBR; move BASE to 0xa000_0000 */
56	li	k0, 0xff400000
57	mtc0	k0, $22, 6
58	/* set up relocation vector address based on thread ID */
59	mfc0	k1, $22, 3
60	srl	k1, 16
61	andi	k1, 0x8000
62	or	k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
63	or	k0, k1
64	li	k1, 0xa0080000
65	sw	k1, 0(k0)
66
67	/* wait here for SW1 interrupt from bmips_boot_secondary() */
68	wait
69
70	la	k0, bmips_reset_nmi_vec
71	li	k1, CKSEG1
72	or	k0, k1
73	jr	k0
74END(bmips_smp_movevec)
75
76/***********************************************************************
77 * Reset/NMI vector
78 * For BMIPS processors that can relocate their exception vectors, this
79 * entire function gets copied to 0x8000_0000.
80 ***********************************************************************/
81
82NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
83	.set	push
84	.set	noat
85	.align	4
86
87#ifdef CONFIG_SMP
88	/* if the NMI bit is clear, assume this is a CPU1 reset instead */
89	li	k1, (1 << 19)
90	mfc0	k0, CP0_STATUS
91	and	k0, k1
92	beqz	k0, bmips_smp_entry
93
94#if defined(CONFIG_CPU_BMIPS5000)
95	mfc0	k0, CP0_PRID
96	li	k1, PRID_IMP_BMIPS5000
97	andi	k0, 0xff00
98	bne	k0, k1, 1f
99
100	/* if we're not on core 0, this must be the SMP boot signal */
101	li	k1, (3 << 25)
102	mfc0	k0, $22
103	and	k0, k1
104	bnez	k0, bmips_smp_entry
1051:
106#endif /* CONFIG_CPU_BMIPS5000 */
107#endif /* CONFIG_SMP */
108
109	/* nope, it's just a regular NMI */
110	SAVE_ALL
111	move	a0, sp
112
113	/* clear EXL, ERL, BEV so that TLB refills still work */
114	mfc0	k0, CP0_STATUS
115	li	k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
116	or	k0, k1
117	xor	k0, k1
118	mtc0	k0, CP0_STATUS
119	BARRIER
120
121	/* jump to the NMI handler function */
122	la	k0, nmi_handler
123	jr	k0
124
125	RESTORE_ALL
126	.set	mips3
127	eret
128
129/***********************************************************************
130 * CPU1 reset vector (used for the initial boot only)
131 * This is still part of bmips_reset_nmi_vec().
132 ***********************************************************************/
133
134#ifdef CONFIG_SMP
135
136bmips_smp_entry:
137
138	/* set up CP0 STATUS; enable FPU */
139	li	k0, 0x30000000
140	mtc0	k0, CP0_STATUS
141	BARRIER
142
143	/* set local CP0 CONFIG to make kseg0 cacheable, write-back */
144	mfc0	k0, CP0_CONFIG
145	ori	k0, 0x07
146	xori	k0, 0x04
147	mtc0	k0, CP0_CONFIG
148
149	mfc0	k0, CP0_PRID
150	andi	k0, 0xff00
151#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
152	li	k1, PRID_IMP_BMIPS43XX
153	bne	k0, k1, 2f
154
155	/* initialize CPU1's local I-cache */
156	li	k0, 0x80000000
157	li	k1, 0x80010000
158	mtc0	zero, $28
159	mtc0	zero, $28, 1
160	BARRIER
161
1621:	cache	Index_Store_Tag_I, 0(k0)
163	addiu	k0, 16
164	bne	k0, k1, 1b
165
166	b	3f
1672:
168#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
169#if defined(CONFIG_CPU_BMIPS5000)
170	/* set exception vector base */
171	li	k1, PRID_IMP_BMIPS5000
172	bne	k0, k1, 3f
173
174	la	k0, ebase
175	lw	k0, 0(k0)
176	mtc0	k0, $15, 1
177	BARRIER
178#endif /* CONFIG_CPU_BMIPS5000 */
1793:
180	/* jump back to kseg0 in case we need to remap the kseg1 area */
181	la	k0, 1f
182	jr	k0
1831:
184	la	k0, bmips_enable_xks01
185	jalr	k0
186
187	/* use temporary stack to set up upper memory TLB */
188	li	sp, BMIPS_WARM_RESTART_VEC
189	la	k0, plat_wired_tlb_setup
190	jalr	k0
191
192	/* switch to permanent stack and continue booting */
193
194	.global bmips_secondary_reentry
195bmips_secondary_reentry:
196	la	k0, bmips_smp_boot_sp
197	lw	sp, 0(k0)
198	la	k0, bmips_smp_boot_gp
199	lw	gp, 0(k0)
200	la	k0, start_secondary
201	jr	k0
202
203#endif /* CONFIG_SMP */
204
205	.align	4
206	.global bmips_reset_nmi_vec_end
207bmips_reset_nmi_vec_end:
208
209END(bmips_reset_nmi_vec)
210
211	.set	pop
212	.previous
213
214/***********************************************************************
215 * CPU1 warm restart vector (used for second and subsequent boots).
216 * Also used for S2 standby recovery (PM).
217 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
218 ***********************************************************************/
219
220LEAF(bmips_smp_int_vec)
221
222	.align	4
223	mfc0	k0, CP0_STATUS
224	ori	k0, 0x01
225	xori	k0, 0x01
226	mtc0	k0, CP0_STATUS
227	eret
228
229	.align	4
230	.global bmips_smp_int_vec_end
231bmips_smp_int_vec_end:
232
233END(bmips_smp_int_vec)
234
235/***********************************************************************
236 * XKS01 support
237 * Certain CPUs support extending kseg0 to 1024MB.
238 ***********************************************************************/
239
240LEAF(bmips_enable_xks01)
241
242#if defined(CONFIG_XKS01)
243	mfc0	t0, CP0_PRID
244	andi	t2, t0, 0xff00
245#if defined(CONFIG_CPU_BMIPS4380)
246	li	t1, PRID_IMP_BMIPS43XX
247	bne	t2, t1, 1f
248
249	andi	t0, 0xff
250	addiu	t1, t0, -PRID_REV_BMIPS4380_HI
251	bgtz	t1, 2f
252	addiu	t0, -PRID_REV_BMIPS4380_LO
253	bltz	t0, 2f
254
255	mfc0	t0, $22, 3
256	li	t1, 0x1ff0
257	li	t2, (1 << 12) | (1 << 9)
258	or	t0, t1
259	xor	t0, t1
260	or	t0, t2
261	mtc0	t0, $22, 3
262	BARRIER
263	b	2f
2641:
265#endif /* CONFIG_CPU_BMIPS4380 */
266#if defined(CONFIG_CPU_BMIPS5000)
267	li	t1, PRID_IMP_BMIPS5000
268	bne	t2, t1, 2f
269
270	mfc0	t0, $22, 5
271	li	t1, 0x01ff
272	li	t2, (1 << 8) | (1 << 5)
273	or	t0, t1
274	xor	t0, t1
275	or	t0, t2
276	mtc0	t0, $22, 5
277	BARRIER
278#endif /* CONFIG_CPU_BMIPS5000 */
2792:
280#endif /* defined(CONFIG_XKS01) */
281
282	jr	ra
283
284END(bmips_enable_xks01)
285
286	.previous
287