xref: /openbmc/linux/arch/mips/kernel/bmips_vec.S (revision 80ecbd24) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Reset/NMI/re-entry vectors for BMIPS processors
9 */
10
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/regdef.h>
17#include <asm/mipsregs.h>
18#include <asm/stackframe.h>
19#include <asm/addrspace.h>
20#include <asm/hazards.h>
21#include <asm/bmips.h>
22
23	.macro	BARRIER
24	.set	mips32
25	_ssnop
26	_ssnop
27	_ssnop
28	.set	mips0
29	.endm
30
31/***********************************************************************
32 * Alternate CPU1 startup vector for BMIPS4350
33 *
34 * On some systems the bootloader has already started CPU1 and configured
35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
36 * triggered by the SW1 interrupt.  If that is the case we try to move
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
38 ***********************************************************************/
39
40LEAF(bmips_smp_movevec)
41	la	k0, 1f
42	li	k1, CKSEG1
43	or	k0, k1
44	jr	k0
45
461:
47	/* clear IV, pending IPIs */
48	mtc0	zero, CP0_CAUSE
49
50	/* re-enable IRQs to wait for SW1 */
51	li	k0, ST0_IE | ST0_BEV | STATUSF_IP1
52	mtc0	k0, CP0_STATUS
53
54	/* set up CPU1 CBR; move BASE to 0xa000_0000 */
55	li	k0, 0xff400000
56	mtc0	k0, $22, 6
57	/* set up relocation vector address based on thread ID */
58	mfc0	k1, $22, 3
59	srl	k1, 16
60	andi	k1, 0x8000
61	or	k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
62	or	k0, k1
63	li	k1, 0xa0080000
64	sw	k1, 0(k0)
65
66	/* wait here for SW1 interrupt from bmips_boot_secondary() */
67	wait
68
69	la	k0, bmips_reset_nmi_vec
70	li	k1, CKSEG1
71	or	k0, k1
72	jr	k0
73END(bmips_smp_movevec)
74
75/***********************************************************************
76 * Reset/NMI vector
77 * For BMIPS processors that can relocate their exception vectors, this
78 * entire function gets copied to 0x8000_0000.
79 ***********************************************************************/
80
81NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
82	.set	push
83	.set	noat
84	.align	4
85
86#ifdef CONFIG_SMP
87	/* if the NMI bit is clear, assume this is a CPU1 reset instead */
88	li	k1, (1 << 19)
89	mfc0	k0, CP0_STATUS
90	and	k0, k1
91	beqz	k0, bmips_smp_entry
92
93#if defined(CONFIG_CPU_BMIPS5000)
94	/* if we're not on core 0, this must be the SMP boot signal */
95	li	k1, (3 << 25)
96	mfc0	k0, $22
97	and	k0, k1
98	bnez	k0, bmips_smp_entry
99#endif
100#endif /* CONFIG_SMP */
101
102	/* nope, it's just a regular NMI */
103	SAVE_ALL
104	move	a0, sp
105
106	/* clear EXL, ERL, BEV so that TLB refills still work */
107	mfc0	k0, CP0_STATUS
108	li	k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
109	or	k0, k1
110	xor	k0, k1
111	mtc0	k0, CP0_STATUS
112	BARRIER
113
114	/* jump to the NMI handler function */
115	la	k0, nmi_handler
116	jr	k0
117
118	RESTORE_ALL
119	.set	mips3
120	eret
121
122/***********************************************************************
123 * CPU1 reset vector (used for the initial boot only)
124 * This is still part of bmips_reset_nmi_vec().
125 ***********************************************************************/
126
127#ifdef CONFIG_SMP
128
129bmips_smp_entry:
130
131	/* set up CP0 STATUS; enable FPU */
132	li	k0, 0x30000000
133	mtc0	k0, CP0_STATUS
134	BARRIER
135
136	/* set local CP0 CONFIG to make kseg0 cacheable, write-back */
137	mfc0	k0, CP0_CONFIG
138	ori	k0, 0x07
139	xori	k0, 0x04
140	mtc0	k0, CP0_CONFIG
141
142#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
143	/* initialize CPU1's local I-cache */
144	li	k0, 0x80000000
145	li	k1, 0x80010000
146	mtc0	zero, $28
147	mtc0	zero, $28, 1
148	BARRIER
149
1501:	cache	Index_Store_Tag_I, 0(k0)
151	addiu	k0, 16
152	bne	k0, k1, 1b
153#elif defined(CONFIG_CPU_BMIPS5000)
154	/* set exception vector base */
155	la	k0, ebase
156	lw	k0, 0(k0)
157	mtc0	k0, $15, 1
158	BARRIER
159#endif
160
161	/* jump back to kseg0 in case we need to remap the kseg1 area */
162	la	k0, 1f
163	jr	k0
1641:
165	la	k0, bmips_enable_xks01
166	jalr	k0
167
168	/* use temporary stack to set up upper memory TLB */
169	li	sp, BMIPS_WARM_RESTART_VEC
170	la	k0, plat_wired_tlb_setup
171	jalr	k0
172
173	/* switch to permanent stack and continue booting */
174
175	.global bmips_secondary_reentry
176bmips_secondary_reentry:
177	la	k0, bmips_smp_boot_sp
178	lw	sp, 0(k0)
179	la	k0, bmips_smp_boot_gp
180	lw	gp, 0(k0)
181	la	k0, start_secondary
182	jr	k0
183
184#endif /* CONFIG_SMP */
185
186	.align	4
187	.global bmips_reset_nmi_vec_end
188bmips_reset_nmi_vec_end:
189
190END(bmips_reset_nmi_vec)
191
192	.set	pop
193	.previous
194
195/***********************************************************************
196 * CPU1 warm restart vector (used for second and subsequent boots).
197 * Also used for S2 standby recovery (PM).
198 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
199 ***********************************************************************/
200
201LEAF(bmips_smp_int_vec)
202
203	.align	4
204	mfc0	k0, CP0_STATUS
205	ori	k0, 0x01
206	xori	k0, 0x01
207	mtc0	k0, CP0_STATUS
208	eret
209
210	.align	4
211	.global bmips_smp_int_vec_end
212bmips_smp_int_vec_end:
213
214END(bmips_smp_int_vec)
215
216/***********************************************************************
217 * XKS01 support
218 * Certain CPUs support extending kseg0 to 1024MB.
219 ***********************************************************************/
220
221LEAF(bmips_enable_xks01)
222
223#if defined(CONFIG_XKS01)
224
225#if defined(CONFIG_CPU_BMIPS4380)
226	mfc0	t0, $22, 3
227	li	t1, 0x1ff0
228	li	t2, (1 << 12) | (1 << 9)
229	or	t0, t1
230	xor	t0, t1
231	or	t0, t2
232	mtc0	t0, $22, 3
233	BARRIER
234#elif defined(CONFIG_CPU_BMIPS5000)
235	mfc0	t0, $22, 5
236	li	t1, 0x01ff
237	li	t2, (1 << 8) | (1 << 5)
238	or	t0, t1
239	xor	t0, t1
240	or	t0, t2
241	mtc0	t0, $22, 5
242	BARRIER
243#else
244
245#error Missing XKS01 setup
246
247#endif
248
249#endif /* defined(CONFIG_XKS01) */
250
251	jr	ra
252
253END(bmips_enable_xks01)
254
255	.previous
256