1 /* 2 * offset.c: Calculate pt_regs and task_struct offsets. 3 * 4 * Copyright (C) 1996 David S. Miller 5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle 6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * 8 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Copyright (C) 2000 MIPS Technologies, Inc. 10 */ 11 #include <linux/compat.h> 12 #include <linux/types.h> 13 #include <linux/sched.h> 14 #include <linux/mm.h> 15 #include <linux/kbuild.h> 16 #include <linux/suspend.h> 17 #include <asm/ptrace.h> 18 #include <asm/processor.h> 19 #include <asm/smp-cps.h> 20 21 #include <linux/kvm_host.h> 22 23 void output_ptreg_defines(void) 24 { 25 COMMENT("MIPS pt_regs offsets."); 26 OFFSET(PT_R0, pt_regs, regs[0]); 27 OFFSET(PT_R1, pt_regs, regs[1]); 28 OFFSET(PT_R2, pt_regs, regs[2]); 29 OFFSET(PT_R3, pt_regs, regs[3]); 30 OFFSET(PT_R4, pt_regs, regs[4]); 31 OFFSET(PT_R5, pt_regs, regs[5]); 32 OFFSET(PT_R6, pt_regs, regs[6]); 33 OFFSET(PT_R7, pt_regs, regs[7]); 34 OFFSET(PT_R8, pt_regs, regs[8]); 35 OFFSET(PT_R9, pt_regs, regs[9]); 36 OFFSET(PT_R10, pt_regs, regs[10]); 37 OFFSET(PT_R11, pt_regs, regs[11]); 38 OFFSET(PT_R12, pt_regs, regs[12]); 39 OFFSET(PT_R13, pt_regs, regs[13]); 40 OFFSET(PT_R14, pt_regs, regs[14]); 41 OFFSET(PT_R15, pt_regs, regs[15]); 42 OFFSET(PT_R16, pt_regs, regs[16]); 43 OFFSET(PT_R17, pt_regs, regs[17]); 44 OFFSET(PT_R18, pt_regs, regs[18]); 45 OFFSET(PT_R19, pt_regs, regs[19]); 46 OFFSET(PT_R20, pt_regs, regs[20]); 47 OFFSET(PT_R21, pt_regs, regs[21]); 48 OFFSET(PT_R22, pt_regs, regs[22]); 49 OFFSET(PT_R23, pt_regs, regs[23]); 50 OFFSET(PT_R24, pt_regs, regs[24]); 51 OFFSET(PT_R25, pt_regs, regs[25]); 52 OFFSET(PT_R26, pt_regs, regs[26]); 53 OFFSET(PT_R27, pt_regs, regs[27]); 54 OFFSET(PT_R28, pt_regs, regs[28]); 55 OFFSET(PT_R29, pt_regs, regs[29]); 56 OFFSET(PT_R30, pt_regs, regs[30]); 57 OFFSET(PT_R31, pt_regs, regs[31]); 58 OFFSET(PT_LO, pt_regs, lo); 59 OFFSET(PT_HI, pt_regs, hi); 60 #ifdef CONFIG_CPU_HAS_SMARTMIPS 61 OFFSET(PT_ACX, pt_regs, acx); 62 #endif 63 OFFSET(PT_EPC, pt_regs, cp0_epc); 64 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr); 65 OFFSET(PT_STATUS, pt_regs, cp0_status); 66 OFFSET(PT_CAUSE, pt_regs, cp0_cause); 67 #ifdef CONFIG_MIPS_MT_SMTC 68 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); 69 #endif /* CONFIG_MIPS_MT_SMTC */ 70 #ifdef CONFIG_CPU_CAVIUM_OCTEON 71 OFFSET(PT_MPL, pt_regs, mpl); 72 OFFSET(PT_MTP, pt_regs, mtp); 73 #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 74 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 75 BLANK(); 76 } 77 78 void output_task_defines(void) 79 { 80 COMMENT("MIPS task_struct offsets."); 81 OFFSET(TASK_STATE, task_struct, state); 82 OFFSET(TASK_THREAD_INFO, task_struct, stack); 83 OFFSET(TASK_FLAGS, task_struct, flags); 84 OFFSET(TASK_MM, task_struct, mm); 85 OFFSET(TASK_PID, task_struct, pid); 86 #if defined(CONFIG_CC_STACKPROTECTOR) 87 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); 88 #endif 89 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); 90 BLANK(); 91 } 92 93 void output_thread_info_defines(void) 94 { 95 COMMENT("MIPS thread_info offsets."); 96 OFFSET(TI_TASK, thread_info, task); 97 OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain); 98 OFFSET(TI_FLAGS, thread_info, flags); 99 OFFSET(TI_TP_VALUE, thread_info, tp_value); 100 OFFSET(TI_CPU, thread_info, cpu); 101 OFFSET(TI_PRE_COUNT, thread_info, preempt_count); 102 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); 103 OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); 104 OFFSET(TI_REGS, thread_info, regs); 105 DEFINE(_THREAD_SIZE, THREAD_SIZE); 106 DEFINE(_THREAD_MASK, THREAD_MASK); 107 BLANK(); 108 } 109 110 void output_thread_defines(void) 111 { 112 COMMENT("MIPS specific thread_struct offsets."); 113 OFFSET(THREAD_REG16, task_struct, thread.reg16); 114 OFFSET(THREAD_REG17, task_struct, thread.reg17); 115 OFFSET(THREAD_REG18, task_struct, thread.reg18); 116 OFFSET(THREAD_REG19, task_struct, thread.reg19); 117 OFFSET(THREAD_REG20, task_struct, thread.reg20); 118 OFFSET(THREAD_REG21, task_struct, thread.reg21); 119 OFFSET(THREAD_REG22, task_struct, thread.reg22); 120 OFFSET(THREAD_REG23, task_struct, thread.reg23); 121 OFFSET(THREAD_REG29, task_struct, thread.reg29); 122 OFFSET(THREAD_REG30, task_struct, thread.reg30); 123 OFFSET(THREAD_REG31, task_struct, thread.reg31); 124 OFFSET(THREAD_STATUS, task_struct, 125 thread.cp0_status); 126 OFFSET(THREAD_FPU, task_struct, thread.fpu); 127 128 OFFSET(THREAD_BVADDR, task_struct, \ 129 thread.cp0_badvaddr); 130 OFFSET(THREAD_BUADDR, task_struct, \ 131 thread.cp0_baduaddr); 132 OFFSET(THREAD_ECODE, task_struct, \ 133 thread.error_code); 134 BLANK(); 135 } 136 137 void output_thread_fpu_defines(void) 138 { 139 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]); 140 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]); 141 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]); 142 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]); 143 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]); 144 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]); 145 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]); 146 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]); 147 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]); 148 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]); 149 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]); 150 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]); 151 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]); 152 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]); 153 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]); 154 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]); 155 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]); 156 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]); 157 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]); 158 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]); 159 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]); 160 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]); 161 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]); 162 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]); 163 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]); 164 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]); 165 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]); 166 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]); 167 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]); 168 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]); 169 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); 170 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); 171 172 /* the least significant 64 bits of each FP register */ 173 OFFSET(THREAD_FPR0_LS64, task_struct, 174 thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]); 175 OFFSET(THREAD_FPR1_LS64, task_struct, 176 thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]); 177 OFFSET(THREAD_FPR2_LS64, task_struct, 178 thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]); 179 OFFSET(THREAD_FPR3_LS64, task_struct, 180 thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]); 181 OFFSET(THREAD_FPR4_LS64, task_struct, 182 thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]); 183 OFFSET(THREAD_FPR5_LS64, task_struct, 184 thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]); 185 OFFSET(THREAD_FPR6_LS64, task_struct, 186 thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]); 187 OFFSET(THREAD_FPR7_LS64, task_struct, 188 thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]); 189 OFFSET(THREAD_FPR8_LS64, task_struct, 190 thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]); 191 OFFSET(THREAD_FPR9_LS64, task_struct, 192 thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]); 193 OFFSET(THREAD_FPR10_LS64, task_struct, 194 thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]); 195 OFFSET(THREAD_FPR11_LS64, task_struct, 196 thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]); 197 OFFSET(THREAD_FPR12_LS64, task_struct, 198 thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]); 199 OFFSET(THREAD_FPR13_LS64, task_struct, 200 thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]); 201 OFFSET(THREAD_FPR14_LS64, task_struct, 202 thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]); 203 OFFSET(THREAD_FPR15_LS64, task_struct, 204 thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]); 205 OFFSET(THREAD_FPR16_LS64, task_struct, 206 thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]); 207 OFFSET(THREAD_FPR17_LS64, task_struct, 208 thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]); 209 OFFSET(THREAD_FPR18_LS64, task_struct, 210 thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]); 211 OFFSET(THREAD_FPR19_LS64, task_struct, 212 thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]); 213 OFFSET(THREAD_FPR20_LS64, task_struct, 214 thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]); 215 OFFSET(THREAD_FPR21_LS64, task_struct, 216 thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]); 217 OFFSET(THREAD_FPR22_LS64, task_struct, 218 thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]); 219 OFFSET(THREAD_FPR23_LS64, task_struct, 220 thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]); 221 OFFSET(THREAD_FPR24_LS64, task_struct, 222 thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]); 223 OFFSET(THREAD_FPR25_LS64, task_struct, 224 thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]); 225 OFFSET(THREAD_FPR26_LS64, task_struct, 226 thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]); 227 OFFSET(THREAD_FPR27_LS64, task_struct, 228 thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]); 229 OFFSET(THREAD_FPR28_LS64, task_struct, 230 thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]); 231 OFFSET(THREAD_FPR29_LS64, task_struct, 232 thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]); 233 OFFSET(THREAD_FPR30_LS64, task_struct, 234 thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]); 235 OFFSET(THREAD_FPR31_LS64, task_struct, 236 thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]); 237 238 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); 239 BLANK(); 240 } 241 242 void output_mm_defines(void) 243 { 244 COMMENT("Size of struct page"); 245 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page)); 246 BLANK(); 247 COMMENT("Linux mm_struct offsets."); 248 OFFSET(MM_USERS, mm_struct, mm_users); 249 OFFSET(MM_PGD, mm_struct, pgd); 250 OFFSET(MM_CONTEXT, mm_struct, context); 251 BLANK(); 252 DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); 253 DEFINE(_PMD_T_SIZE, sizeof(pmd_t)); 254 DEFINE(_PTE_T_SIZE, sizeof(pte_t)); 255 BLANK(); 256 DEFINE(_PGD_T_LOG2, PGD_T_LOG2); 257 #ifndef __PAGETABLE_PMD_FOLDED 258 DEFINE(_PMD_T_LOG2, PMD_T_LOG2); 259 #endif 260 DEFINE(_PTE_T_LOG2, PTE_T_LOG2); 261 BLANK(); 262 DEFINE(_PGD_ORDER, PGD_ORDER); 263 #ifndef __PAGETABLE_PMD_FOLDED 264 DEFINE(_PMD_ORDER, PMD_ORDER); 265 #endif 266 DEFINE(_PTE_ORDER, PTE_ORDER); 267 BLANK(); 268 DEFINE(_PMD_SHIFT, PMD_SHIFT); 269 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT); 270 BLANK(); 271 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD); 272 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD); 273 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE); 274 BLANK(); 275 DEFINE(_PAGE_SHIFT, PAGE_SHIFT); 276 DEFINE(_PAGE_SIZE, PAGE_SIZE); 277 BLANK(); 278 } 279 280 #ifdef CONFIG_32BIT 281 void output_sc_defines(void) 282 { 283 COMMENT("Linux sigcontext offsets."); 284 OFFSET(SC_REGS, sigcontext, sc_regs); 285 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 286 OFFSET(SC_ACX, sigcontext, sc_acx); 287 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 288 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 289 OFFSET(SC_PC, sigcontext, sc_pc); 290 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 291 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir); 292 OFFSET(SC_HI1, sigcontext, sc_hi1); 293 OFFSET(SC_LO1, sigcontext, sc_lo1); 294 OFFSET(SC_HI2, sigcontext, sc_hi2); 295 OFFSET(SC_LO2, sigcontext, sc_lo2); 296 OFFSET(SC_HI3, sigcontext, sc_hi3); 297 OFFSET(SC_LO3, sigcontext, sc_lo3); 298 OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); 299 BLANK(); 300 } 301 #endif 302 303 #ifdef CONFIG_64BIT 304 void output_sc_defines(void) 305 { 306 COMMENT("Linux sigcontext offsets."); 307 OFFSET(SC_REGS, sigcontext, sc_regs); 308 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 309 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 310 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 311 OFFSET(SC_PC, sigcontext, sc_pc); 312 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 313 OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); 314 BLANK(); 315 } 316 #endif 317 318 #ifdef CONFIG_MIPS32_COMPAT 319 void output_sc32_defines(void) 320 { 321 COMMENT("Linux 32-bit sigcontext offsets."); 322 OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs); 323 OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr); 324 OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir); 325 OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs); 326 BLANK(); 327 } 328 #endif 329 330 void output_signal_defined(void) 331 { 332 COMMENT("Linux signal numbers."); 333 DEFINE(_SIGHUP, SIGHUP); 334 DEFINE(_SIGINT, SIGINT); 335 DEFINE(_SIGQUIT, SIGQUIT); 336 DEFINE(_SIGILL, SIGILL); 337 DEFINE(_SIGTRAP, SIGTRAP); 338 DEFINE(_SIGIOT, SIGIOT); 339 DEFINE(_SIGABRT, SIGABRT); 340 DEFINE(_SIGEMT, SIGEMT); 341 DEFINE(_SIGFPE, SIGFPE); 342 DEFINE(_SIGKILL, SIGKILL); 343 DEFINE(_SIGBUS, SIGBUS); 344 DEFINE(_SIGSEGV, SIGSEGV); 345 DEFINE(_SIGSYS, SIGSYS); 346 DEFINE(_SIGPIPE, SIGPIPE); 347 DEFINE(_SIGALRM, SIGALRM); 348 DEFINE(_SIGTERM, SIGTERM); 349 DEFINE(_SIGUSR1, SIGUSR1); 350 DEFINE(_SIGUSR2, SIGUSR2); 351 DEFINE(_SIGCHLD, SIGCHLD); 352 DEFINE(_SIGPWR, SIGPWR); 353 DEFINE(_SIGWINCH, SIGWINCH); 354 DEFINE(_SIGURG, SIGURG); 355 DEFINE(_SIGIO, SIGIO); 356 DEFINE(_SIGSTOP, SIGSTOP); 357 DEFINE(_SIGTSTP, SIGTSTP); 358 DEFINE(_SIGCONT, SIGCONT); 359 DEFINE(_SIGTTIN, SIGTTIN); 360 DEFINE(_SIGTTOU, SIGTTOU); 361 DEFINE(_SIGVTALRM, SIGVTALRM); 362 DEFINE(_SIGPROF, SIGPROF); 363 DEFINE(_SIGXCPU, SIGXCPU); 364 DEFINE(_SIGXFSZ, SIGXFSZ); 365 BLANK(); 366 } 367 368 #ifdef CONFIG_CPU_CAVIUM_OCTEON 369 void output_octeon_cop2_state_defines(void) 370 { 371 COMMENT("Octeon specific octeon_cop2_state offsets."); 372 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); 373 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); 374 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); 375 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); 376 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); 377 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); 378 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); 379 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); 380 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); 381 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); 382 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); 383 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); 384 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); 385 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); 386 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); 387 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); 388 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); 389 OFFSET(THREAD_CP2, task_struct, thread.cp2); 390 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); 391 BLANK(); 392 } 393 #endif 394 395 #ifdef CONFIG_HIBERNATION 396 void output_pbe_defines(void) 397 { 398 COMMENT(" Linux struct pbe offsets. "); 399 OFFSET(PBE_ADDRESS, pbe, address); 400 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); 401 OFFSET(PBE_NEXT, pbe, next); 402 DEFINE(PBE_SIZE, sizeof(struct pbe)); 403 BLANK(); 404 } 405 #endif 406 407 void output_kvm_defines(void) 408 { 409 COMMENT(" KVM/MIPS Specfic offsets. "); 410 DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch)); 411 OFFSET(VCPU_RUN, kvm_vcpu, run); 412 OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch); 413 414 OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase); 415 OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase); 416 417 OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack); 418 OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp); 419 420 OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr); 421 OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause); 422 OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc); 423 OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi); 424 425 OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst); 426 427 OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]); 428 OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]); 429 OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]); 430 OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]); 431 OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]); 432 OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]); 433 OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]); 434 OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]); 435 OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]); 436 OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]); 437 OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]); 438 OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]); 439 OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]); 440 OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]); 441 OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]); 442 OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]); 443 OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]); 444 OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]); 445 OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]); 446 OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]); 447 OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]); 448 OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]); 449 OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]); 450 OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]); 451 OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]); 452 OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]); 453 OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]); 454 OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]); 455 OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]); 456 OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]); 457 OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]); 458 OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]); 459 OFFSET(VCPU_LO, kvm_vcpu_arch, lo); 460 OFFSET(VCPU_HI, kvm_vcpu_arch, hi); 461 OFFSET(VCPU_PC, kvm_vcpu_arch, pc); 462 OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0); 463 OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid); 464 OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid); 465 466 OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]); 467 OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]); 468 BLANK(); 469 } 470 471 #ifdef CONFIG_MIPS_CPS 472 void output_cps_defines(void) 473 { 474 COMMENT(" MIPS CPS offsets. "); 475 OFFSET(BOOTCFG_CORE, boot_config, core); 476 OFFSET(BOOTCFG_VPE, boot_config, vpe); 477 OFFSET(BOOTCFG_PC, boot_config, pc); 478 OFFSET(BOOTCFG_SP, boot_config, sp); 479 OFFSET(BOOTCFG_GP, boot_config, gp); 480 } 481 #endif 482