1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * asm-offsets.c: Calculate pt_regs and task_struct offsets. 4 * 5 * Copyright (C) 1996 David S. Miller 6 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * 9 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 */ 12 #include <linux/compat.h> 13 #include <linux/types.h> 14 #include <linux/sched.h> 15 #include <linux/mm.h> 16 #include <linux/kbuild.h> 17 #include <linux/suspend.h> 18 #include <asm/cpu-info.h> 19 #include <asm/pm.h> 20 #include <asm/ptrace.h> 21 #include <asm/processor.h> 22 #include <asm/smp-cps.h> 23 24 #include <linux/kvm_host.h> 25 26 void output_ptreg_defines(void); 27 void output_ptreg_defines(void) 28 { 29 COMMENT("MIPS pt_regs offsets."); 30 OFFSET(PT_R0, pt_regs, regs[0]); 31 OFFSET(PT_R1, pt_regs, regs[1]); 32 OFFSET(PT_R2, pt_regs, regs[2]); 33 OFFSET(PT_R3, pt_regs, regs[3]); 34 OFFSET(PT_R4, pt_regs, regs[4]); 35 OFFSET(PT_R5, pt_regs, regs[5]); 36 OFFSET(PT_R6, pt_regs, regs[6]); 37 OFFSET(PT_R7, pt_regs, regs[7]); 38 OFFSET(PT_R8, pt_regs, regs[8]); 39 OFFSET(PT_R9, pt_regs, regs[9]); 40 OFFSET(PT_R10, pt_regs, regs[10]); 41 OFFSET(PT_R11, pt_regs, regs[11]); 42 OFFSET(PT_R12, pt_regs, regs[12]); 43 OFFSET(PT_R13, pt_regs, regs[13]); 44 OFFSET(PT_R14, pt_regs, regs[14]); 45 OFFSET(PT_R15, pt_regs, regs[15]); 46 OFFSET(PT_R16, pt_regs, regs[16]); 47 OFFSET(PT_R17, pt_regs, regs[17]); 48 OFFSET(PT_R18, pt_regs, regs[18]); 49 OFFSET(PT_R19, pt_regs, regs[19]); 50 OFFSET(PT_R20, pt_regs, regs[20]); 51 OFFSET(PT_R21, pt_regs, regs[21]); 52 OFFSET(PT_R22, pt_regs, regs[22]); 53 OFFSET(PT_R23, pt_regs, regs[23]); 54 OFFSET(PT_R24, pt_regs, regs[24]); 55 OFFSET(PT_R25, pt_regs, regs[25]); 56 OFFSET(PT_R26, pt_regs, regs[26]); 57 OFFSET(PT_R27, pt_regs, regs[27]); 58 OFFSET(PT_R28, pt_regs, regs[28]); 59 OFFSET(PT_R29, pt_regs, regs[29]); 60 OFFSET(PT_R30, pt_regs, regs[30]); 61 OFFSET(PT_R31, pt_regs, regs[31]); 62 OFFSET(PT_LO, pt_regs, lo); 63 OFFSET(PT_HI, pt_regs, hi); 64 #ifdef CONFIG_CPU_HAS_SMARTMIPS 65 OFFSET(PT_ACX, pt_regs, acx); 66 #endif 67 OFFSET(PT_EPC, pt_regs, cp0_epc); 68 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr); 69 OFFSET(PT_STATUS, pt_regs, cp0_status); 70 OFFSET(PT_CAUSE, pt_regs, cp0_cause); 71 #ifdef CONFIG_CPU_CAVIUM_OCTEON 72 OFFSET(PT_MPL, pt_regs, mpl); 73 OFFSET(PT_MTP, pt_regs, mtp); 74 #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 75 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 76 BLANK(); 77 } 78 79 void output_task_defines(void); 80 void output_task_defines(void) 81 { 82 COMMENT("MIPS task_struct offsets."); 83 OFFSET(TASK_THREAD_INFO, task_struct, stack); 84 OFFSET(TASK_FLAGS, task_struct, flags); 85 OFFSET(TASK_MM, task_struct, mm); 86 OFFSET(TASK_PID, task_struct, pid); 87 #if defined(CONFIG_STACKPROTECTOR) 88 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); 89 #endif 90 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); 91 BLANK(); 92 } 93 94 void output_thread_info_defines(void); 95 void output_thread_info_defines(void) 96 { 97 COMMENT("MIPS thread_info offsets."); 98 OFFSET(TI_TASK, thread_info, task); 99 OFFSET(TI_FLAGS, thread_info, flags); 100 OFFSET(TI_TP_VALUE, thread_info, tp_value); 101 OFFSET(TI_CPU, thread_info, cpu); 102 OFFSET(TI_PRE_COUNT, thread_info, preempt_count); 103 OFFSET(TI_REGS, thread_info, regs); 104 DEFINE(_THREAD_SIZE, THREAD_SIZE); 105 DEFINE(_THREAD_MASK, THREAD_MASK); 106 DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); 107 DEFINE(_IRQ_STACK_START, IRQ_STACK_START); 108 BLANK(); 109 } 110 111 void output_thread_defines(void); 112 void output_thread_defines(void) 113 { 114 COMMENT("MIPS specific thread_struct offsets."); 115 OFFSET(THREAD_REG16, task_struct, thread.reg16); 116 OFFSET(THREAD_REG17, task_struct, thread.reg17); 117 OFFSET(THREAD_REG18, task_struct, thread.reg18); 118 OFFSET(THREAD_REG19, task_struct, thread.reg19); 119 OFFSET(THREAD_REG20, task_struct, thread.reg20); 120 OFFSET(THREAD_REG21, task_struct, thread.reg21); 121 OFFSET(THREAD_REG22, task_struct, thread.reg22); 122 OFFSET(THREAD_REG23, task_struct, thread.reg23); 123 OFFSET(THREAD_REG29, task_struct, thread.reg29); 124 OFFSET(THREAD_REG30, task_struct, thread.reg30); 125 OFFSET(THREAD_REG31, task_struct, thread.reg31); 126 OFFSET(THREAD_STATUS, task_struct, 127 thread.cp0_status); 128 129 OFFSET(THREAD_BVADDR, task_struct, \ 130 thread.cp0_badvaddr); 131 OFFSET(THREAD_BUADDR, task_struct, \ 132 thread.cp0_baduaddr); 133 OFFSET(THREAD_ECODE, task_struct, \ 134 thread.error_code); 135 OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr); 136 BLANK(); 137 } 138 139 #ifdef CONFIG_MIPS_FP_SUPPORT 140 void output_thread_fpu_defines(void); 141 void output_thread_fpu_defines(void) 142 { 143 OFFSET(THREAD_FPU, task_struct, thread.fpu); 144 145 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]); 146 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]); 147 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]); 148 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]); 149 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]); 150 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]); 151 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]); 152 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]); 153 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]); 154 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]); 155 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]); 156 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]); 157 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]); 158 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]); 159 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]); 160 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]); 161 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]); 162 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]); 163 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]); 164 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]); 165 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]); 166 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]); 167 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]); 168 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]); 169 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]); 170 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]); 171 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]); 172 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]); 173 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]); 174 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]); 175 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); 176 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); 177 178 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); 179 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr); 180 BLANK(); 181 } 182 #endif 183 184 void output_mm_defines(void); 185 void output_mm_defines(void) 186 { 187 COMMENT("Size of struct page"); 188 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page)); 189 BLANK(); 190 COMMENT("Linux mm_struct offsets."); 191 OFFSET(MM_USERS, mm_struct, mm_users); 192 OFFSET(MM_PGD, mm_struct, pgd); 193 OFFSET(MM_CONTEXT, mm_struct, context); 194 BLANK(); 195 DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); 196 DEFINE(_PMD_T_SIZE, sizeof(pmd_t)); 197 DEFINE(_PTE_T_SIZE, sizeof(pte_t)); 198 BLANK(); 199 DEFINE(_PGD_T_LOG2, PGD_T_LOG2); 200 #ifndef __PAGETABLE_PMD_FOLDED 201 DEFINE(_PMD_T_LOG2, PMD_T_LOG2); 202 #endif 203 DEFINE(_PTE_T_LOG2, PTE_T_LOG2); 204 BLANK(); 205 BLANK(); 206 DEFINE(_PMD_SHIFT, PMD_SHIFT); 207 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT); 208 BLANK(); 209 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD); 210 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD); 211 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE); 212 BLANK(); 213 DEFINE(_PAGE_SHIFT, PAGE_SHIFT); 214 DEFINE(_PAGE_SIZE, PAGE_SIZE); 215 BLANK(); 216 } 217 218 #ifdef CONFIG_32BIT 219 void output_sc_defines(void); 220 void output_sc_defines(void) 221 { 222 COMMENT("Linux sigcontext offsets."); 223 OFFSET(SC_REGS, sigcontext, sc_regs); 224 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 225 OFFSET(SC_ACX, sigcontext, sc_acx); 226 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 227 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 228 OFFSET(SC_PC, sigcontext, sc_pc); 229 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 230 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir); 231 OFFSET(SC_HI1, sigcontext, sc_hi1); 232 OFFSET(SC_LO1, sigcontext, sc_lo1); 233 OFFSET(SC_HI2, sigcontext, sc_hi2); 234 OFFSET(SC_LO2, sigcontext, sc_lo2); 235 OFFSET(SC_HI3, sigcontext, sc_hi3); 236 OFFSET(SC_LO3, sigcontext, sc_lo3); 237 BLANK(); 238 } 239 #endif 240 241 #ifdef CONFIG_64BIT 242 void output_sc_defines(void); 243 void output_sc_defines(void) 244 { 245 COMMENT("Linux sigcontext offsets."); 246 OFFSET(SC_REGS, sigcontext, sc_regs); 247 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 248 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 249 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 250 OFFSET(SC_PC, sigcontext, sc_pc); 251 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 252 BLANK(); 253 } 254 #endif 255 256 void output_signal_defined(void); 257 void output_signal_defined(void) 258 { 259 COMMENT("Linux signal numbers."); 260 DEFINE(_SIGHUP, SIGHUP); 261 DEFINE(_SIGINT, SIGINT); 262 DEFINE(_SIGQUIT, SIGQUIT); 263 DEFINE(_SIGILL, SIGILL); 264 DEFINE(_SIGTRAP, SIGTRAP); 265 DEFINE(_SIGIOT, SIGIOT); 266 DEFINE(_SIGABRT, SIGABRT); 267 DEFINE(_SIGEMT, SIGEMT); 268 DEFINE(_SIGFPE, SIGFPE); 269 DEFINE(_SIGKILL, SIGKILL); 270 DEFINE(_SIGBUS, SIGBUS); 271 DEFINE(_SIGSEGV, SIGSEGV); 272 DEFINE(_SIGSYS, SIGSYS); 273 DEFINE(_SIGPIPE, SIGPIPE); 274 DEFINE(_SIGALRM, SIGALRM); 275 DEFINE(_SIGTERM, SIGTERM); 276 DEFINE(_SIGUSR1, SIGUSR1); 277 DEFINE(_SIGUSR2, SIGUSR2); 278 DEFINE(_SIGCHLD, SIGCHLD); 279 DEFINE(_SIGPWR, SIGPWR); 280 DEFINE(_SIGWINCH, SIGWINCH); 281 DEFINE(_SIGURG, SIGURG); 282 DEFINE(_SIGIO, SIGIO); 283 DEFINE(_SIGSTOP, SIGSTOP); 284 DEFINE(_SIGTSTP, SIGTSTP); 285 DEFINE(_SIGCONT, SIGCONT); 286 DEFINE(_SIGTTIN, SIGTTIN); 287 DEFINE(_SIGTTOU, SIGTTOU); 288 DEFINE(_SIGVTALRM, SIGVTALRM); 289 DEFINE(_SIGPROF, SIGPROF); 290 DEFINE(_SIGXCPU, SIGXCPU); 291 DEFINE(_SIGXFSZ, SIGXFSZ); 292 BLANK(); 293 } 294 295 #ifdef CONFIG_CPU_CAVIUM_OCTEON 296 void output_octeon_cop2_state_defines(void); 297 void output_octeon_cop2_state_defines(void) 298 { 299 COMMENT("Octeon specific octeon_cop2_state offsets."); 300 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); 301 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); 302 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); 303 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); 304 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); 305 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); 306 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); 307 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); 308 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); 309 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); 310 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); 311 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); 312 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); 313 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); 314 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); 315 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); 316 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); 317 OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3); 318 OFFSET(THREAD_CP2, task_struct, thread.cp2); 319 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 320 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 321 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); 322 #endif 323 BLANK(); 324 } 325 #endif 326 327 #ifdef CONFIG_HIBERNATION 328 void output_pbe_defines(void); 329 void output_pbe_defines(void) 330 { 331 COMMENT(" Linux struct pbe offsets. "); 332 OFFSET(PBE_ADDRESS, pbe, address); 333 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); 334 OFFSET(PBE_NEXT, pbe, next); 335 DEFINE(PBE_SIZE, sizeof(struct pbe)); 336 BLANK(); 337 } 338 #endif 339 340 #ifdef CONFIG_CPU_PM 341 void output_pm_defines(void); 342 void output_pm_defines(void) 343 { 344 COMMENT(" PM offsets. "); 345 #ifdef CONFIG_EVA 346 OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]); 347 OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]); 348 OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]); 349 #endif 350 OFFSET(SSS_SP, mips_static_suspend_state, sp); 351 BLANK(); 352 } 353 #endif 354 355 #ifdef CONFIG_MIPS_FP_SUPPORT 356 void output_kvm_defines(void); 357 void output_kvm_defines(void) 358 { 359 COMMENT(" KVM/MIPS Specific offsets. "); 360 361 OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]); 362 OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]); 363 OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]); 364 OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]); 365 OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]); 366 OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]); 367 OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]); 368 OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]); 369 OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]); 370 OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]); 371 OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]); 372 OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]); 373 OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]); 374 OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]); 375 OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]); 376 OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]); 377 OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]); 378 OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]); 379 OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]); 380 OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]); 381 OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]); 382 OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]); 383 OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]); 384 OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]); 385 OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]); 386 OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]); 387 OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]); 388 OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]); 389 OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]); 390 OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]); 391 OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]); 392 OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]); 393 394 OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31); 395 OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr); 396 BLANK(); 397 } 398 #endif 399 400 #ifdef CONFIG_MIPS_CPS 401 void output_cps_defines(void); 402 void output_cps_defines(void) 403 { 404 COMMENT(" MIPS CPS offsets. "); 405 406 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); 407 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); 408 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config)); 409 410 OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc); 411 OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp); 412 OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp); 413 DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config)); 414 } 415 #endif 416