xref: /openbmc/linux/arch/mips/include/uapi/asm/inst.h (revision 981ab3f1)
1 /*
2  * Format of an instruction in memory.
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1996, 2000 by Ralf Baechle
9  * Copyright (C) 2006 by Thiemo Seufer
10  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
11  * Copyright (C) 2014 Imagination Technologies Ltd.
12  */
13 #ifndef _UAPI_ASM_INST_H
14 #define _UAPI_ASM_INST_H
15 
16 #include <asm/bitfield.h>
17 
18 /*
19  * Major opcodes; before MIPS IV cop1x was called cop3.
20  */
21 enum major_op {
22 	spec_op, bcond_op, j_op, jal_op,
23 	beq_op, bne_op, blez_op, bgtz_op,
24 	addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
25 	andi_op, ori_op, xori_op, lui_op,
26 	cop0_op, cop1_op, cop2_op, cop1x_op,
27 	beql_op, bnel_op, blezl_op, bgtzl_op,
28 	daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
29 	spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
30 	lb_op, lh_op, lwl_op, lw_op,
31 	lbu_op, lhu_op, lwr_op, lwu_op,
32 	sb_op, sh_op, swl_op, sw_op,
33 	sdl_op, sdr_op, swr_op, cache_op,
34 	ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
35 	lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
36 	sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
37 	scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
38 };
39 
40 /*
41  * func field of spec opcode.
42  */
43 enum spec_op {
44 	sll_op, movc_op, srl_op, sra_op,
45 	sllv_op, pmon_op, srlv_op, srav_op,
46 	jr_op, jalr_op, movz_op, movn_op,
47 	syscall_op, break_op, spim_op, sync_op,
48 	mfhi_op, mthi_op, mflo_op, mtlo_op,
49 	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
50 	mult_op, multu_op, div_op, divu_op,
51 	dmult_op, dmultu_op, ddiv_op, ddivu_op,
52 	add_op, addu_op, sub_op, subu_op,
53 	and_op, or_op, xor_op, nor_op,
54 	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
55 	dadd_op, daddu_op, dsub_op, dsubu_op,
56 	tge_op, tgeu_op, tlt_op, tltu_op,
57 	teq_op, spec5_unused_op, tne_op, spec6_unused_op,
58 	dsll_op, spec7_unused_op, dsrl_op, dsra_op,
59 	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
60 };
61 
62 /*
63  * func field of spec2 opcode.
64  */
65 enum spec2_op {
66 	madd_op, maddu_op, mul_op, spec2_3_unused_op,
67 	msub_op, msubu_op, /* more unused ops */
68 	clz_op = 0x20, clo_op,
69 	dclz_op = 0x24, dclo_op,
70 	sdbpp_op = 0x3f
71 };
72 
73 /*
74  * func field of spec3 opcode.
75  */
76 enum spec3_op {
77 	ext_op, dextm_op, dextu_op, dext_op,
78 	ins_op, dinsm_op, dinsu_op, dins_op,
79 	yield_op  = 0x09, lx_op     = 0x0a,
80 	lwle_op   = 0x19, lwre_op   = 0x1a,
81 	cachee_op = 0x1b, sbe_op    = 0x1c,
82 	she_op    = 0x1d, sce_op    = 0x1e,
83 	swe_op    = 0x1f, bshfl_op  = 0x20,
84 	swle_op   = 0x21, swre_op   = 0x22,
85 	prefe_op  = 0x23, dbshfl_op = 0x24,
86 	cache6_op = 0x25, sc6_op    = 0x26,
87 	scd6_op   = 0x27, lbue_op   = 0x28,
88 	lhue_op   = 0x29, lbe_op    = 0x2c,
89 	lhe_op    = 0x2d, lle_op    = 0x2e,
90 	lwe_op    = 0x2f, pref6_op  = 0x35,
91 	ll6_op    = 0x36, lld6_op   = 0x37,
92 	rdhwr_op  = 0x3b
93 };
94 
95 /*
96  * Bits 10-6 minor opcode for r6 spec mult/div encodings
97  */
98 enum mult_op {
99 	mult_mult_op = 0x0,
100 	mult_mul_op = 0x2,
101 	mult_muh_op = 0x3,
102 };
103 enum multu_op {
104 	multu_multu_op = 0x0,
105 	multu_mulu_op = 0x2,
106 	multu_muhu_op = 0x3,
107 };
108 enum div_op {
109 	div_div_op = 0x0,
110 	div_div6_op = 0x2,
111 	div_mod_op = 0x3,
112 };
113 enum divu_op {
114 	divu_divu_op = 0x0,
115 	divu_divu6_op = 0x2,
116 	divu_modu_op = 0x3,
117 };
118 enum dmult_op {
119 	dmult_dmult_op = 0x0,
120 	dmult_dmul_op = 0x2,
121 	dmult_dmuh_op = 0x3,
122 };
123 enum dmultu_op {
124 	dmultu_dmultu_op = 0x0,
125 	dmultu_dmulu_op = 0x2,
126 	dmultu_dmuhu_op = 0x3,
127 };
128 enum ddiv_op {
129 	ddiv_ddiv_op = 0x0,
130 	ddiv_ddiv6_op = 0x2,
131 	ddiv_dmod_op = 0x3,
132 };
133 enum ddivu_op {
134 	ddivu_ddivu_op = 0x0,
135 	ddivu_ddivu6_op = 0x2,
136 	ddivu_dmodu_op = 0x3,
137 };
138 
139 /*
140  * rt field of bcond opcodes.
141  */
142 enum rt_op {
143 	bltz_op, bgez_op, bltzl_op, bgezl_op,
144 	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
145 	tgei_op, tgeiu_op, tlti_op, tltiu_op,
146 	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
147 	bltzal_op, bgezal_op, bltzall_op, bgezall_op,
148 	rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
149 	rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
150 	bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
151 };
152 
153 /*
154  * rs field of cop opcodes.
155  */
156 enum cop_op {
157 	mfc_op	      = 0x00, dmfc_op	    = 0x01,
158 	cfc_op	      = 0x02, mfhc0_op	    = 0x02,
159 	mfhc_op       = 0x03, mtc_op	    = 0x04,
160 	dmtc_op	      = 0x05, ctc_op	    = 0x06,
161 	mthc0_op      = 0x06, mthc_op	    = 0x07,
162 	bc_op	      = 0x08, bc1eqz_op     = 0x09,
163 	mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
164 	wrpgpr_op     = 0x0e, cop_op	    = 0x10,
165 	copm_op	      = 0x18
166 };
167 
168 /*
169  * rt field of cop.bc_op opcodes
170  */
171 enum bcop_op {
172 	bcf_op, bct_op, bcfl_op, bctl_op
173 };
174 
175 /*
176  * func field of cop0 coi opcodes.
177  */
178 enum cop0_coi_func {
179 	tlbr_op	      = 0x01, tlbwi_op	    = 0x02,
180 	tlbwr_op      = 0x06, tlbp_op	    = 0x08,
181 	rfe_op	      = 0x10, eret_op	    = 0x18,
182 	wait_op       = 0x20, hypcall_op    = 0x28
183 };
184 
185 /*
186  * func field of cop0 com opcodes.
187  */
188 enum cop0_com_func {
189 	tlbr1_op      = 0x01, tlbw_op	    = 0x02,
190 	tlbp1_op      = 0x08, dctr_op	    = 0x09,
191 	dctw_op	      = 0x0a
192 };
193 
194 /*
195  * fmt field of cop1 opcodes.
196  */
197 enum cop1_fmt {
198 	s_fmt, d_fmt, e_fmt, q_fmt,
199 	w_fmt, l_fmt
200 };
201 
202 /*
203  * func field of cop1 instructions using d, s or w format.
204  */
205 enum cop1_sdw_func {
206 	fadd_op	     =	0x00, fsub_op	   =  0x01,
207 	fmul_op	     =	0x02, fdiv_op	   =  0x03,
208 	fsqrt_op     =	0x04, fabs_op	   =  0x05,
209 	fmov_op	     =	0x06, fneg_op	   =  0x07,
210 	froundl_op   =	0x08, ftruncl_op   =  0x09,
211 	fceill_op    =	0x0a, ffloorl_op   =  0x0b,
212 	fround_op    =	0x0c, ftrunc_op	   =  0x0d,
213 	fceil_op     =	0x0e, ffloor_op	   =  0x0f,
214 	fsel_op      =  0x10,
215 	fmovc_op     =	0x11, fmovz_op	   =  0x12,
216 	fmovn_op     =	0x13, fseleqz_op   =  0x14,
217 	frecip_op    =  0x15, frsqrt_op    =  0x16,
218 	fselnez_op   =  0x17, fmaddf_op    =  0x18,
219 	fmsubf_op    =  0x19, frint_op     =  0x1a,
220 	fclass_op    =  0x1b, fmin_op      =  0x1c,
221 	fmina_op     =  0x1d, fmax_op      =  0x1e,
222 	fmaxa_op     =  0x1f, fcvts_op     =  0x20,
223 	fcvtd_op     =	0x21, fcvte_op	   =  0x22,
224 	fcvtw_op     =	0x24, fcvtl_op	   =  0x25,
225 	fcmp_op	     =	0x30
226 };
227 
228 /*
229  * func field of cop1x opcodes (MIPS IV).
230  */
231 enum cop1x_func {
232 	lwxc1_op     =	0x00, ldxc1_op	   =  0x01,
233 	swxc1_op     =  0x08, sdxc1_op	   =  0x09,
234 	pfetch_op    =	0x0f, madd_s_op	   =  0x20,
235 	madd_d_op    =	0x21, madd_e_op	   =  0x22,
236 	msub_s_op    =	0x28, msub_d_op	   =  0x29,
237 	msub_e_op    =	0x2a, nmadd_s_op   =  0x30,
238 	nmadd_d_op   =	0x31, nmadd_e_op   =  0x32,
239 	nmsub_s_op   =	0x38, nmsub_d_op   =  0x39,
240 	nmsub_e_op   =	0x3a
241 };
242 
243 /*
244  * func field for mad opcodes (MIPS IV).
245  */
246 enum mad_func {
247 	madd_fp_op	= 0x08, msub_fp_op	= 0x0a,
248 	nmadd_fp_op	= 0x0c, nmsub_fp_op	= 0x0e
249 };
250 
251 /*
252  * func field for page table walker (Loongson-3).
253  */
254 enum ptw_func {
255 	lwdir_op = 0x00,
256 	lwpte_op = 0x01,
257 	lddir_op = 0x02,
258 	ldpte_op = 0x03,
259 };
260 
261 /*
262  * func field for special3 lx opcodes (Cavium Octeon).
263  */
264 enum lx_func {
265 	lwx_op	= 0x00,
266 	lhx_op	= 0x04,
267 	lbux_op = 0x06,
268 	ldx_op	= 0x08,
269 	lwux_op = 0x10,
270 	lhux_op = 0x14,
271 	lbx_op	= 0x16,
272 };
273 
274 /*
275  * BSHFL opcodes
276  */
277 enum bshfl_func {
278 	wsbh_op = 0x2,
279 	seb_op  = 0x10,
280 	seh_op  = 0x18,
281 };
282 
283 /*
284  * DBSHFL opcodes
285  */
286 enum dbshfl_func {
287 	dsbh_op = 0x2,
288 	dshd_op = 0x5,
289 };
290 
291 /*
292  * MSA minor opcodes.
293  */
294 enum msa_func {
295 	msa_elm_op = 0x19,
296 };
297 
298 /*
299  * MSA ELM opcodes.
300  */
301 enum msa_elm {
302 	msa_ctc_op = 0x3e,
303 	msa_cfc_op = 0x7e,
304 };
305 
306 /*
307  * func field for MSA MI10 format.
308  */
309 enum msa_mi10_func {
310 	msa_ld_op = 8,
311 	msa_st_op = 9,
312 };
313 
314 /*
315  * MSA 2 bit format fields.
316  */
317 enum msa_2b_fmt {
318 	msa_fmt_b = 0,
319 	msa_fmt_h = 1,
320 	msa_fmt_w = 2,
321 	msa_fmt_d = 3,
322 };
323 
324 /*
325  * (microMIPS) Major opcodes.
326  */
327 enum mm_major_op {
328 	mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
329 	mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
330 	mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
331 	mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
332 	mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
333 	mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
334 	mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
335 	mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
336 	mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
337 	mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
338 	mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
339 	mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
340 	mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
341 	mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
342 	mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
343 	mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
344 };
345 
346 /*
347  * (microMIPS) POOL32I minor opcodes.
348  */
349 enum mm_32i_minor_op {
350 	mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
351 	mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
352 	mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
353 	mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
354 	mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
355 	mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
356 	mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
357 	mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
358 	mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
359 };
360 
361 /*
362  * (microMIPS) POOL32A minor opcodes.
363  */
364 enum mm_32a_minor_op {
365 	mm_sll32_op = 0x000,
366 	mm_ins_op = 0x00c,
367 	mm_sllv32_op = 0x010,
368 	mm_ext_op = 0x02c,
369 	mm_pool32axf_op = 0x03c,
370 	mm_srl32_op = 0x040,
371 	mm_sra_op = 0x080,
372 	mm_srlv32_op = 0x090,
373 	mm_rotr_op = 0x0c0,
374 	mm_lwxs_op = 0x118,
375 	mm_addu32_op = 0x150,
376 	mm_subu32_op = 0x1d0,
377 	mm_wsbh_op = 0x1ec,
378 	mm_mul_op = 0x210,
379 	mm_and_op = 0x250,
380 	mm_or32_op = 0x290,
381 	mm_xor32_op = 0x310,
382 	mm_slt_op = 0x350,
383 	mm_sltu_op = 0x390,
384 };
385 
386 /*
387  * (microMIPS) POOL32B functions.
388  */
389 enum mm_32b_func {
390 	mm_lwc2_func = 0x0,
391 	mm_lwp_func = 0x1,
392 	mm_ldc2_func = 0x2,
393 	mm_ldp_func = 0x4,
394 	mm_lwm32_func = 0x5,
395 	mm_cache_func = 0x6,
396 	mm_ldm_func = 0x7,
397 	mm_swc2_func = 0x8,
398 	mm_swp_func = 0x9,
399 	mm_sdc2_func = 0xa,
400 	mm_sdp_func = 0xc,
401 	mm_swm32_func = 0xd,
402 	mm_sdm_func = 0xf,
403 };
404 
405 /*
406  * (microMIPS) POOL32C functions.
407  */
408 enum mm_32c_func {
409 	mm_pref_func = 0x2,
410 	mm_ll_func = 0x3,
411 	mm_swr_func = 0x9,
412 	mm_sc_func = 0xb,
413 	mm_lwu_func = 0xe,
414 };
415 
416 /*
417  * (microMIPS) POOL32AXF minor opcodes.
418  */
419 enum mm_32axf_minor_op {
420 	mm_mfc0_op = 0x003,
421 	mm_mtc0_op = 0x00b,
422 	mm_tlbp_op = 0x00d,
423 	mm_mfhi32_op = 0x035,
424 	mm_jalr_op = 0x03c,
425 	mm_tlbr_op = 0x04d,
426 	mm_mflo32_op = 0x075,
427 	mm_jalrhb_op = 0x07c,
428 	mm_tlbwi_op = 0x08d,
429 	mm_mthi32_op = 0x0b5,
430 	mm_tlbwr_op = 0x0cd,
431 	mm_mtlo32_op = 0x0f5,
432 	mm_di_op = 0x11d,
433 	mm_jalrs_op = 0x13c,
434 	mm_jalrshb_op = 0x17c,
435 	mm_sync_op = 0x1ad,
436 	mm_syscall_op = 0x22d,
437 	mm_wait_op = 0x24d,
438 	mm_eret_op = 0x3cd,
439 	mm_divu_op = 0x5dc,
440 };
441 
442 /*
443  * (microMIPS) POOL32F minor opcodes.
444  */
445 enum mm_32f_minor_op {
446 	mm_32f_00_op = 0x00,
447 	mm_32f_01_op = 0x01,
448 	mm_32f_02_op = 0x02,
449 	mm_32f_10_op = 0x08,
450 	mm_32f_11_op = 0x09,
451 	mm_32f_12_op = 0x0a,
452 	mm_32f_20_op = 0x10,
453 	mm_32f_30_op = 0x18,
454 	mm_32f_40_op = 0x20,
455 	mm_32f_41_op = 0x21,
456 	mm_32f_42_op = 0x22,
457 	mm_32f_50_op = 0x28,
458 	mm_32f_51_op = 0x29,
459 	mm_32f_52_op = 0x2a,
460 	mm_32f_60_op = 0x30,
461 	mm_32f_70_op = 0x38,
462 	mm_32f_73_op = 0x3b,
463 	mm_32f_74_op = 0x3c,
464 };
465 
466 /*
467  * (microMIPS) POOL32F secondary minor opcodes.
468  */
469 enum mm_32f_10_minor_op {
470 	mm_lwxc1_op = 0x1,
471 	mm_swxc1_op,
472 	mm_ldxc1_op,
473 	mm_sdxc1_op,
474 	mm_luxc1_op,
475 	mm_suxc1_op,
476 };
477 
478 enum mm_32f_func {
479 	mm_lwxc1_func = 0x048,
480 	mm_swxc1_func = 0x088,
481 	mm_ldxc1_func = 0x0c8,
482 	mm_sdxc1_func = 0x108,
483 };
484 
485 /*
486  * (microMIPS) POOL32F secondary minor opcodes.
487  */
488 enum mm_32f_40_minor_op {
489 	mm_fmovf_op,
490 	mm_fmovt_op,
491 };
492 
493 /*
494  * (microMIPS) POOL32F secondary minor opcodes.
495  */
496 enum mm_32f_60_minor_op {
497 	mm_fadd_op,
498 	mm_fsub_op,
499 	mm_fmul_op,
500 	mm_fdiv_op,
501 };
502 
503 /*
504  * (microMIPS) POOL32F secondary minor opcodes.
505  */
506 enum mm_32f_70_minor_op {
507 	mm_fmovn_op,
508 	mm_fmovz_op,
509 };
510 
511 /*
512  * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
513  */
514 enum mm_32f_73_minor_op {
515 	mm_fmov0_op = 0x01,
516 	mm_fcvtl_op = 0x04,
517 	mm_movf0_op = 0x05,
518 	mm_frsqrt_op = 0x08,
519 	mm_ffloorl_op = 0x0c,
520 	mm_fabs0_op = 0x0d,
521 	mm_fcvtw_op = 0x24,
522 	mm_movt0_op = 0x25,
523 	mm_fsqrt_op = 0x28,
524 	mm_ffloorw_op = 0x2c,
525 	mm_fneg0_op = 0x2d,
526 	mm_cfc1_op = 0x40,
527 	mm_frecip_op = 0x48,
528 	mm_fceill_op = 0x4c,
529 	mm_fcvtd0_op = 0x4d,
530 	mm_ctc1_op = 0x60,
531 	mm_fceilw_op = 0x6c,
532 	mm_fcvts0_op = 0x6d,
533 	mm_mfc1_op = 0x80,
534 	mm_fmov1_op = 0x81,
535 	mm_movf1_op = 0x85,
536 	mm_ftruncl_op = 0x8c,
537 	mm_fabs1_op = 0x8d,
538 	mm_mtc1_op = 0xa0,
539 	mm_movt1_op = 0xa5,
540 	mm_ftruncw_op = 0xac,
541 	mm_fneg1_op = 0xad,
542 	mm_mfhc1_op = 0xc0,
543 	mm_froundl_op = 0xcc,
544 	mm_fcvtd1_op = 0xcd,
545 	mm_mthc1_op = 0xe0,
546 	mm_froundw_op = 0xec,
547 	mm_fcvts1_op = 0xed,
548 };
549 
550 /*
551  * (microMIPS) POOL32S minor opcodes.
552  */
553 enum mm_32s_minor_op {
554 	mm_32s_elm_op = 0x16,
555 };
556 
557 /*
558  * (microMIPS) POOL16C minor opcodes.
559  */
560 enum mm_16c_minor_op {
561 	mm_lwm16_op = 0x04,
562 	mm_swm16_op = 0x05,
563 	mm_jr16_op = 0x0c,
564 	mm_jrc_op = 0x0d,
565 	mm_jalr16_op = 0x0e,
566 	mm_jalrs16_op = 0x0f,
567 	mm_jraddiusp_op = 0x18,
568 };
569 
570 /*
571  * (microMIPS) POOL16D minor opcodes.
572  */
573 enum mm_16d_minor_op {
574 	mm_addius5_func,
575 	mm_addiusp_func,
576 };
577 
578 /*
579  * (MIPS16e) opcodes.
580  */
581 enum MIPS16e_ops {
582 	MIPS16e_jal_op = 003,
583 	MIPS16e_ld_op = 007,
584 	MIPS16e_i8_op = 014,
585 	MIPS16e_sd_op = 017,
586 	MIPS16e_lb_op = 020,
587 	MIPS16e_lh_op = 021,
588 	MIPS16e_lwsp_op = 022,
589 	MIPS16e_lw_op = 023,
590 	MIPS16e_lbu_op = 024,
591 	MIPS16e_lhu_op = 025,
592 	MIPS16e_lwpc_op = 026,
593 	MIPS16e_lwu_op = 027,
594 	MIPS16e_sb_op = 030,
595 	MIPS16e_sh_op = 031,
596 	MIPS16e_swsp_op = 032,
597 	MIPS16e_sw_op = 033,
598 	MIPS16e_rr_op = 035,
599 	MIPS16e_extend_op = 036,
600 	MIPS16e_i64_op = 037,
601 };
602 
603 enum MIPS16e_i64_func {
604 	MIPS16e_ldsp_func,
605 	MIPS16e_sdsp_func,
606 	MIPS16e_sdrasp_func,
607 	MIPS16e_dadjsp_func,
608 	MIPS16e_ldpc_func,
609 };
610 
611 enum MIPS16e_rr_func {
612 	MIPS16e_jr_func,
613 };
614 
615 enum MIPS6e_i8_func {
616 	MIPS16e_swrasp_func = 02,
617 };
618 
619 /*
620  * (microMIPS) NOP instruction.
621  */
622 #define MM_NOP16	0x0c00
623 
624 struct j_format {
625 	__BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
626 	__BITFIELD_FIELD(unsigned int target : 26,
627 	;))
628 };
629 
630 struct i_format {			/* signed immediate format */
631 	__BITFIELD_FIELD(unsigned int opcode : 6,
632 	__BITFIELD_FIELD(unsigned int rs : 5,
633 	__BITFIELD_FIELD(unsigned int rt : 5,
634 	__BITFIELD_FIELD(signed int simmediate : 16,
635 	;))))
636 };
637 
638 struct u_format {			/* unsigned immediate format */
639 	__BITFIELD_FIELD(unsigned int opcode : 6,
640 	__BITFIELD_FIELD(unsigned int rs : 5,
641 	__BITFIELD_FIELD(unsigned int rt : 5,
642 	__BITFIELD_FIELD(unsigned int uimmediate : 16,
643 	;))))
644 };
645 
646 struct c_format {			/* Cache (>= R6000) format */
647 	__BITFIELD_FIELD(unsigned int opcode : 6,
648 	__BITFIELD_FIELD(unsigned int rs : 5,
649 	__BITFIELD_FIELD(unsigned int c_op : 3,
650 	__BITFIELD_FIELD(unsigned int cache : 2,
651 	__BITFIELD_FIELD(unsigned int simmediate : 16,
652 	;)))))
653 };
654 
655 struct r_format {			/* Register format */
656 	__BITFIELD_FIELD(unsigned int opcode : 6,
657 	__BITFIELD_FIELD(unsigned int rs : 5,
658 	__BITFIELD_FIELD(unsigned int rt : 5,
659 	__BITFIELD_FIELD(unsigned int rd : 5,
660 	__BITFIELD_FIELD(unsigned int re : 5,
661 	__BITFIELD_FIELD(unsigned int func : 6,
662 	;))))))
663 };
664 
665 struct c0r_format {			/* C0 register format */
666 	__BITFIELD_FIELD(unsigned int opcode : 6,
667 	__BITFIELD_FIELD(unsigned int rs : 5,
668 	__BITFIELD_FIELD(unsigned int rt : 5,
669 	__BITFIELD_FIELD(unsigned int rd : 5,
670 	__BITFIELD_FIELD(unsigned int z: 8,
671 	__BITFIELD_FIELD(unsigned int sel : 3,
672 	;))))))
673 };
674 
675 struct mfmc0_format {			/* MFMC0 register format */
676 	__BITFIELD_FIELD(unsigned int opcode : 6,
677 	__BITFIELD_FIELD(unsigned int rs : 5,
678 	__BITFIELD_FIELD(unsigned int rt : 5,
679 	__BITFIELD_FIELD(unsigned int rd : 5,
680 	__BITFIELD_FIELD(unsigned int re : 5,
681 	__BITFIELD_FIELD(unsigned int sc : 1,
682 	__BITFIELD_FIELD(unsigned int : 2,
683 	__BITFIELD_FIELD(unsigned int sel : 3,
684 	;))))))))
685 };
686 
687 struct co_format {			/* C0 CO format */
688 	__BITFIELD_FIELD(unsigned int opcode : 6,
689 	__BITFIELD_FIELD(unsigned int co : 1,
690 	__BITFIELD_FIELD(unsigned int code : 19,
691 	__BITFIELD_FIELD(unsigned int func : 6,
692 	;))))
693 };
694 
695 struct p_format {		/* Performance counter format (R10000) */
696 	__BITFIELD_FIELD(unsigned int opcode : 6,
697 	__BITFIELD_FIELD(unsigned int rs : 5,
698 	__BITFIELD_FIELD(unsigned int rt : 5,
699 	__BITFIELD_FIELD(unsigned int rd : 5,
700 	__BITFIELD_FIELD(unsigned int re : 5,
701 	__BITFIELD_FIELD(unsigned int func : 6,
702 	;))))))
703 };
704 
705 struct f_format {			/* FPU register format */
706 	__BITFIELD_FIELD(unsigned int opcode : 6,
707 	__BITFIELD_FIELD(unsigned int : 1,
708 	__BITFIELD_FIELD(unsigned int fmt : 4,
709 	__BITFIELD_FIELD(unsigned int rt : 5,
710 	__BITFIELD_FIELD(unsigned int rd : 5,
711 	__BITFIELD_FIELD(unsigned int re : 5,
712 	__BITFIELD_FIELD(unsigned int func : 6,
713 	;)))))))
714 };
715 
716 struct ma_format {		/* FPU multiply and add format (MIPS IV) */
717 	__BITFIELD_FIELD(unsigned int opcode : 6,
718 	__BITFIELD_FIELD(unsigned int fr : 5,
719 	__BITFIELD_FIELD(unsigned int ft : 5,
720 	__BITFIELD_FIELD(unsigned int fs : 5,
721 	__BITFIELD_FIELD(unsigned int fd : 5,
722 	__BITFIELD_FIELD(unsigned int func : 4,
723 	__BITFIELD_FIELD(unsigned int fmt : 2,
724 	;)))))))
725 };
726 
727 struct b_format {			/* BREAK and SYSCALL */
728 	__BITFIELD_FIELD(unsigned int opcode : 6,
729 	__BITFIELD_FIELD(unsigned int code : 20,
730 	__BITFIELD_FIELD(unsigned int func : 6,
731 	;)))
732 };
733 
734 struct ps_format {			/* MIPS-3D / paired single format */
735 	__BITFIELD_FIELD(unsigned int opcode : 6,
736 	__BITFIELD_FIELD(unsigned int rs : 5,
737 	__BITFIELD_FIELD(unsigned int ft : 5,
738 	__BITFIELD_FIELD(unsigned int fs : 5,
739 	__BITFIELD_FIELD(unsigned int fd : 5,
740 	__BITFIELD_FIELD(unsigned int func : 6,
741 	;))))))
742 };
743 
744 struct v_format {				/* MDMX vector format */
745 	__BITFIELD_FIELD(unsigned int opcode : 6,
746 	__BITFIELD_FIELD(unsigned int sel : 4,
747 	__BITFIELD_FIELD(unsigned int fmt : 1,
748 	__BITFIELD_FIELD(unsigned int vt : 5,
749 	__BITFIELD_FIELD(unsigned int vs : 5,
750 	__BITFIELD_FIELD(unsigned int vd : 5,
751 	__BITFIELD_FIELD(unsigned int func : 6,
752 	;)))))))
753 };
754 
755 struct msa_mi10_format {		/* MSA MI10 */
756 	__BITFIELD_FIELD(unsigned int opcode : 6,
757 	__BITFIELD_FIELD(signed int s10 : 10,
758 	__BITFIELD_FIELD(unsigned int rs : 5,
759 	__BITFIELD_FIELD(unsigned int wd : 5,
760 	__BITFIELD_FIELD(unsigned int func : 4,
761 	__BITFIELD_FIELD(unsigned int df : 2,
762 	;))))))
763 };
764 
765 struct dsp_format {		/* SPEC3 DSP format instructions */
766 	__BITFIELD_FIELD(unsigned int opcode : 6,
767 	__BITFIELD_FIELD(unsigned int base : 5,
768 	__BITFIELD_FIELD(unsigned int index : 5,
769 	__BITFIELD_FIELD(unsigned int rd : 5,
770 	__BITFIELD_FIELD(unsigned int op : 5,
771 	__BITFIELD_FIELD(unsigned int func : 6,
772 	;))))))
773 };
774 
775 struct spec3_format {   /* SPEC3 */
776 	__BITFIELD_FIELD(unsigned int opcode:6,
777 	__BITFIELD_FIELD(unsigned int rs:5,
778 	__BITFIELD_FIELD(unsigned int rt:5,
779 	__BITFIELD_FIELD(signed int simmediate:9,
780 	__BITFIELD_FIELD(unsigned int func:7,
781 	;)))))
782 };
783 
784 /*
785  * microMIPS instruction formats (32-bit length)
786  *
787  * NOTE:
788  *	Parenthesis denote whether the format is a microMIPS instruction or
789  *	if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
790  */
791 struct fb_format {		/* FPU branch format (MIPS32) */
792 	__BITFIELD_FIELD(unsigned int opcode : 6,
793 	__BITFIELD_FIELD(unsigned int bc : 5,
794 	__BITFIELD_FIELD(unsigned int cc : 3,
795 	__BITFIELD_FIELD(unsigned int flag : 2,
796 	__BITFIELD_FIELD(signed int simmediate : 16,
797 	;)))))
798 };
799 
800 struct fp0_format {		/* FPU multiply and add format (MIPS32) */
801 	__BITFIELD_FIELD(unsigned int opcode : 6,
802 	__BITFIELD_FIELD(unsigned int fmt : 5,
803 	__BITFIELD_FIELD(unsigned int ft : 5,
804 	__BITFIELD_FIELD(unsigned int fs : 5,
805 	__BITFIELD_FIELD(unsigned int fd : 5,
806 	__BITFIELD_FIELD(unsigned int func : 6,
807 	;))))))
808 };
809 
810 struct mm_fp0_format {		/* FPU multiply and add format (microMIPS) */
811 	__BITFIELD_FIELD(unsigned int opcode : 6,
812 	__BITFIELD_FIELD(unsigned int ft : 5,
813 	__BITFIELD_FIELD(unsigned int fs : 5,
814 	__BITFIELD_FIELD(unsigned int fd : 5,
815 	__BITFIELD_FIELD(unsigned int fmt : 3,
816 	__BITFIELD_FIELD(unsigned int op : 2,
817 	__BITFIELD_FIELD(unsigned int func : 6,
818 	;)))))))
819 };
820 
821 struct fp1_format {		/* FPU mfc1 and cfc1 format (MIPS32) */
822 	__BITFIELD_FIELD(unsigned int opcode : 6,
823 	__BITFIELD_FIELD(unsigned int op : 5,
824 	__BITFIELD_FIELD(unsigned int rt : 5,
825 	__BITFIELD_FIELD(unsigned int fs : 5,
826 	__BITFIELD_FIELD(unsigned int fd : 5,
827 	__BITFIELD_FIELD(unsigned int func : 6,
828 	;))))))
829 };
830 
831 struct mm_fp1_format {		/* FPU mfc1 and cfc1 format (microMIPS) */
832 	__BITFIELD_FIELD(unsigned int opcode : 6,
833 	__BITFIELD_FIELD(unsigned int rt : 5,
834 	__BITFIELD_FIELD(unsigned int fs : 5,
835 	__BITFIELD_FIELD(unsigned int fmt : 2,
836 	__BITFIELD_FIELD(unsigned int op : 8,
837 	__BITFIELD_FIELD(unsigned int func : 6,
838 	;))))))
839 };
840 
841 struct mm_fp2_format {		/* FPU movt and movf format (microMIPS) */
842 	__BITFIELD_FIELD(unsigned int opcode : 6,
843 	__BITFIELD_FIELD(unsigned int fd : 5,
844 	__BITFIELD_FIELD(unsigned int fs : 5,
845 	__BITFIELD_FIELD(unsigned int cc : 3,
846 	__BITFIELD_FIELD(unsigned int zero : 2,
847 	__BITFIELD_FIELD(unsigned int fmt : 2,
848 	__BITFIELD_FIELD(unsigned int op : 3,
849 	__BITFIELD_FIELD(unsigned int func : 6,
850 	;))))))))
851 };
852 
853 struct mm_fp3_format {		/* FPU abs and neg format (microMIPS) */
854 	__BITFIELD_FIELD(unsigned int opcode : 6,
855 	__BITFIELD_FIELD(unsigned int rt : 5,
856 	__BITFIELD_FIELD(unsigned int fs : 5,
857 	__BITFIELD_FIELD(unsigned int fmt : 3,
858 	__BITFIELD_FIELD(unsigned int op : 7,
859 	__BITFIELD_FIELD(unsigned int func : 6,
860 	;))))))
861 };
862 
863 struct mm_fp4_format {		/* FPU c.cond format (microMIPS) */
864 	__BITFIELD_FIELD(unsigned int opcode : 6,
865 	__BITFIELD_FIELD(unsigned int rt : 5,
866 	__BITFIELD_FIELD(unsigned int fs : 5,
867 	__BITFIELD_FIELD(unsigned int cc : 3,
868 	__BITFIELD_FIELD(unsigned int fmt : 3,
869 	__BITFIELD_FIELD(unsigned int cond : 4,
870 	__BITFIELD_FIELD(unsigned int func : 6,
871 	;)))))))
872 };
873 
874 struct mm_fp5_format {		/* FPU lwxc1 and swxc1 format (microMIPS) */
875 	__BITFIELD_FIELD(unsigned int opcode : 6,
876 	__BITFIELD_FIELD(unsigned int index : 5,
877 	__BITFIELD_FIELD(unsigned int base : 5,
878 	__BITFIELD_FIELD(unsigned int fd : 5,
879 	__BITFIELD_FIELD(unsigned int op : 5,
880 	__BITFIELD_FIELD(unsigned int func : 6,
881 	;))))))
882 };
883 
884 struct fp6_format {		/* FPU madd and msub format (MIPS IV) */
885 	__BITFIELD_FIELD(unsigned int opcode : 6,
886 	__BITFIELD_FIELD(unsigned int fr : 5,
887 	__BITFIELD_FIELD(unsigned int ft : 5,
888 	__BITFIELD_FIELD(unsigned int fs : 5,
889 	__BITFIELD_FIELD(unsigned int fd : 5,
890 	__BITFIELD_FIELD(unsigned int func : 6,
891 	;))))))
892 };
893 
894 struct mm_fp6_format {		/* FPU madd and msub format (microMIPS) */
895 	__BITFIELD_FIELD(unsigned int opcode : 6,
896 	__BITFIELD_FIELD(unsigned int ft : 5,
897 	__BITFIELD_FIELD(unsigned int fs : 5,
898 	__BITFIELD_FIELD(unsigned int fd : 5,
899 	__BITFIELD_FIELD(unsigned int fr : 5,
900 	__BITFIELD_FIELD(unsigned int func : 6,
901 	;))))))
902 };
903 
904 struct mm_i_format {		/* Immediate format (microMIPS) */
905 	__BITFIELD_FIELD(unsigned int opcode : 6,
906 	__BITFIELD_FIELD(unsigned int rt : 5,
907 	__BITFIELD_FIELD(unsigned int rs : 5,
908 	__BITFIELD_FIELD(signed int simmediate : 16,
909 	;))))
910 };
911 
912 struct mm_m_format {		/* Multi-word load/store format (microMIPS) */
913 	__BITFIELD_FIELD(unsigned int opcode : 6,
914 	__BITFIELD_FIELD(unsigned int rd : 5,
915 	__BITFIELD_FIELD(unsigned int base : 5,
916 	__BITFIELD_FIELD(unsigned int func : 4,
917 	__BITFIELD_FIELD(signed int simmediate : 12,
918 	;)))))
919 };
920 
921 struct mm_x_format {		/* Scaled indexed load format (microMIPS) */
922 	__BITFIELD_FIELD(unsigned int opcode : 6,
923 	__BITFIELD_FIELD(unsigned int index : 5,
924 	__BITFIELD_FIELD(unsigned int base : 5,
925 	__BITFIELD_FIELD(unsigned int rd : 5,
926 	__BITFIELD_FIELD(unsigned int func : 11,
927 	;)))))
928 };
929 
930 struct mm_a_format {		/* ADDIUPC format (microMIPS) */
931 	__BITFIELD_FIELD(unsigned int opcode : 6,
932 	__BITFIELD_FIELD(unsigned int rs : 3,
933 	__BITFIELD_FIELD(signed int simmediate : 23,
934 	;)))
935 };
936 
937 /*
938  * microMIPS instruction formats (16-bit length)
939  */
940 struct mm_b0_format {		/* Unconditional branch format (microMIPS) */
941 	__BITFIELD_FIELD(unsigned int opcode : 6,
942 	__BITFIELD_FIELD(signed int simmediate : 10,
943 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
944 	;)))
945 };
946 
947 struct mm_b1_format {		/* Conditional branch format (microMIPS) */
948 	__BITFIELD_FIELD(unsigned int opcode : 6,
949 	__BITFIELD_FIELD(unsigned int rs : 3,
950 	__BITFIELD_FIELD(signed int simmediate : 7,
951 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
952 	;))))
953 };
954 
955 struct mm16_m_format {		/* Multi-word load/store format */
956 	__BITFIELD_FIELD(unsigned int opcode : 6,
957 	__BITFIELD_FIELD(unsigned int func : 4,
958 	__BITFIELD_FIELD(unsigned int rlist : 2,
959 	__BITFIELD_FIELD(unsigned int imm : 4,
960 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
961 	;)))))
962 };
963 
964 struct mm16_rb_format {		/* Signed immediate format */
965 	__BITFIELD_FIELD(unsigned int opcode : 6,
966 	__BITFIELD_FIELD(unsigned int rt : 3,
967 	__BITFIELD_FIELD(unsigned int base : 3,
968 	__BITFIELD_FIELD(signed int simmediate : 4,
969 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
970 	;)))))
971 };
972 
973 struct mm16_r3_format {		/* Load from global pointer format */
974 	__BITFIELD_FIELD(unsigned int opcode : 6,
975 	__BITFIELD_FIELD(unsigned int rt : 3,
976 	__BITFIELD_FIELD(signed int simmediate : 7,
977 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
978 	;))))
979 };
980 
981 struct mm16_r5_format {		/* Load/store from stack pointer format */
982 	__BITFIELD_FIELD(unsigned int opcode : 6,
983 	__BITFIELD_FIELD(unsigned int rt : 5,
984 	__BITFIELD_FIELD(signed int simmediate : 5,
985 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
986 	;))))
987 };
988 
989 /*
990  * MIPS16e instruction formats (16-bit length)
991  */
992 struct m16e_rr {
993 	__BITFIELD_FIELD(unsigned int opcode : 5,
994 	__BITFIELD_FIELD(unsigned int rx : 3,
995 	__BITFIELD_FIELD(unsigned int nd : 1,
996 	__BITFIELD_FIELD(unsigned int l : 1,
997 	__BITFIELD_FIELD(unsigned int ra : 1,
998 	__BITFIELD_FIELD(unsigned int func : 5,
999 	;))))))
1000 };
1001 
1002 struct m16e_jal {
1003 	__BITFIELD_FIELD(unsigned int opcode : 5,
1004 	__BITFIELD_FIELD(unsigned int x : 1,
1005 	__BITFIELD_FIELD(unsigned int imm20_16 : 5,
1006 	__BITFIELD_FIELD(signed int imm25_21 : 5,
1007 	;))))
1008 };
1009 
1010 struct m16e_i64 {
1011 	__BITFIELD_FIELD(unsigned int opcode : 5,
1012 	__BITFIELD_FIELD(unsigned int func : 3,
1013 	__BITFIELD_FIELD(unsigned int imm : 8,
1014 	;)))
1015 };
1016 
1017 struct m16e_ri64 {
1018 	__BITFIELD_FIELD(unsigned int opcode : 5,
1019 	__BITFIELD_FIELD(unsigned int func : 3,
1020 	__BITFIELD_FIELD(unsigned int ry : 3,
1021 	__BITFIELD_FIELD(unsigned int imm : 5,
1022 	;))))
1023 };
1024 
1025 struct m16e_ri {
1026 	__BITFIELD_FIELD(unsigned int opcode : 5,
1027 	__BITFIELD_FIELD(unsigned int rx : 3,
1028 	__BITFIELD_FIELD(unsigned int imm : 8,
1029 	;)))
1030 };
1031 
1032 struct m16e_rri {
1033 	__BITFIELD_FIELD(unsigned int opcode : 5,
1034 	__BITFIELD_FIELD(unsigned int rx : 3,
1035 	__BITFIELD_FIELD(unsigned int ry : 3,
1036 	__BITFIELD_FIELD(unsigned int imm : 5,
1037 	;))))
1038 };
1039 
1040 struct m16e_i8 {
1041 	__BITFIELD_FIELD(unsigned int opcode : 5,
1042 	__BITFIELD_FIELD(unsigned int func : 3,
1043 	__BITFIELD_FIELD(unsigned int imm : 8,
1044 	;)))
1045 };
1046 
1047 union mips_instruction {
1048 	unsigned int word;
1049 	unsigned short halfword[2];
1050 	unsigned char byte[4];
1051 	struct j_format j_format;
1052 	struct i_format i_format;
1053 	struct u_format u_format;
1054 	struct c_format c_format;
1055 	struct r_format r_format;
1056 	struct c0r_format c0r_format;
1057 	struct mfmc0_format mfmc0_format;
1058 	struct co_format co_format;
1059 	struct p_format p_format;
1060 	struct f_format f_format;
1061 	struct ma_format ma_format;
1062 	struct msa_mi10_format msa_mi10_format;
1063 	struct b_format b_format;
1064 	struct ps_format ps_format;
1065 	struct v_format v_format;
1066 	struct dsp_format dsp_format;
1067 	struct spec3_format spec3_format;
1068 	struct fb_format fb_format;
1069 	struct fp0_format fp0_format;
1070 	struct mm_fp0_format mm_fp0_format;
1071 	struct fp1_format fp1_format;
1072 	struct mm_fp1_format mm_fp1_format;
1073 	struct mm_fp2_format mm_fp2_format;
1074 	struct mm_fp3_format mm_fp3_format;
1075 	struct mm_fp4_format mm_fp4_format;
1076 	struct mm_fp5_format mm_fp5_format;
1077 	struct fp6_format fp6_format;
1078 	struct mm_fp6_format mm_fp6_format;
1079 	struct mm_i_format mm_i_format;
1080 	struct mm_m_format mm_m_format;
1081 	struct mm_x_format mm_x_format;
1082 	struct mm_a_format mm_a_format;
1083 	struct mm_b0_format mm_b0_format;
1084 	struct mm_b1_format mm_b1_format;
1085 	struct mm16_m_format mm16_m_format ;
1086 	struct mm16_rb_format mm16_rb_format;
1087 	struct mm16_r3_format mm16_r3_format;
1088 	struct mm16_r5_format mm16_r5_format;
1089 };
1090 
1091 union mips16e_instruction {
1092 	unsigned int full : 16;
1093 	struct m16e_rr rr;
1094 	struct m16e_jal jal;
1095 	struct m16e_i64 i64;
1096 	struct m16e_ri64 ri64;
1097 	struct m16e_ri ri;
1098 	struct m16e_rri rri;
1099 	struct m16e_i8 i8;
1100 };
1101 
1102 #endif /* _UAPI_ASM_INST_H */
1103