1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13 #ifndef _UAPI_ASM_INST_H 14 #define _UAPI_ASM_INST_H 15 16 #include <asm/bitfield.h> 17 18 /* 19 * Major opcodes; before MIPS IV cop1x was called cop3. 20 */ 21 enum major_op { 22 spec_op, bcond_op, j_op, jal_op, 23 beq_op, bne_op, blez_op, bgtz_op, 24 addi_op, addiu_op, slti_op, sltiu_op, 25 andi_op, ori_op, xori_op, lui_op, 26 cop0_op, cop1_op, cop2_op, cop1x_op, 27 beql_op, bnel_op, blezl_op, bgtzl_op, 28 daddi_op, daddiu_op, ldl_op, ldr_op, 29 spec2_op, jalx_op, mdmx_op, spec3_op, 30 lb_op, lh_op, lwl_op, lw_op, 31 lbu_op, lhu_op, lwr_op, lwu_op, 32 sb_op, sh_op, swl_op, sw_op, 33 sdl_op, sdr_op, swr_op, cache_op, 34 ll_op, lwc1_op, lwc2_op, pref_op, 35 lld_op, ldc1_op, ldc2_op, ld_op, 36 sc_op, swc1_op, swc2_op, major_3b_op, 37 scd_op, sdc1_op, sdc2_op, sd_op 38 }; 39 40 /* 41 * func field of spec opcode. 42 */ 43 enum spec_op { 44 sll_op, movc_op, srl_op, sra_op, 45 sllv_op, pmon_op, srlv_op, srav_op, 46 jr_op, jalr_op, movz_op, movn_op, 47 syscall_op, break_op, spim_op, sync_op, 48 mfhi_op, mthi_op, mflo_op, mtlo_op, 49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 50 mult_op, multu_op, div_op, divu_op, 51 dmult_op, dmultu_op, ddiv_op, ddivu_op, 52 add_op, addu_op, sub_op, subu_op, 53 and_op, or_op, xor_op, nor_op, 54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 55 dadd_op, daddu_op, dsub_op, dsubu_op, 56 tge_op, tgeu_op, tlt_op, tltu_op, 57 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 58 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 60 }; 61 62 /* 63 * func field of spec2 opcode. 64 */ 65 enum spec2_op { 66 madd_op, maddu_op, mul_op, spec2_3_unused_op, 67 msub_op, msubu_op, /* more unused ops */ 68 clz_op = 0x20, clo_op, 69 dclz_op = 0x24, dclo_op, 70 sdbpp_op = 0x3f 71 }; 72 73 /* 74 * func field of spec3 opcode. 75 */ 76 enum spec3_op { 77 ext_op, dextm_op, dextu_op, dext_op, 78 ins_op, dinsm_op, dinsu_op, dins_op, 79 yield_op = 0x09, lx_op = 0x0a, 80 lwle_op = 0x19, lwre_op = 0x1a, 81 cachee_op = 0x1b, sbe_op = 0x1c, 82 she_op = 0x1d, sce_op = 0x1e, 83 swe_op = 0x1f, bshfl_op = 0x20, 84 swle_op = 0x21, swre_op = 0x22, 85 prefe_op = 0x23, dbshfl_op = 0x24, 86 lbue_op = 0x28, lhue_op = 0x29, 87 lbe_op = 0x2c, lhe_op = 0x2d, 88 lle_op = 0x2e, lwe_op = 0x2f, 89 rdhwr_op = 0x3b 90 }; 91 92 /* 93 * rt field of bcond opcodes. 94 */ 95 enum rt_op { 96 bltz_op, bgez_op, bltzl_op, bgezl_op, 97 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 98 tgei_op, tgeiu_op, tlti_op, tltiu_op, 99 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 100 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 101 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 102 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 103 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f 104 }; 105 106 /* 107 * rs field of cop opcodes. 108 */ 109 enum cop_op { 110 mfc_op = 0x00, dmfc_op = 0x01, 111 cfc_op = 0x02, mfhc_op = 0x03, 112 mtc_op = 0x04, dmtc_op = 0x05, 113 ctc_op = 0x06, mthc_op = 0x07, 114 bc_op = 0x08, cop_op = 0x10, 115 copm_op = 0x18 116 }; 117 118 /* 119 * rt field of cop.bc_op opcodes 120 */ 121 enum bcop_op { 122 bcf_op, bct_op, bcfl_op, bctl_op 123 }; 124 125 /* 126 * func field of cop0 coi opcodes. 127 */ 128 enum cop0_coi_func { 129 tlbr_op = 0x01, tlbwi_op = 0x02, 130 tlbwr_op = 0x06, tlbp_op = 0x08, 131 rfe_op = 0x10, eret_op = 0x18, 132 wait_op = 0x20, 133 }; 134 135 /* 136 * func field of cop0 com opcodes. 137 */ 138 enum cop0_com_func { 139 tlbr1_op = 0x01, tlbw_op = 0x02, 140 tlbp1_op = 0x08, dctr_op = 0x09, 141 dctw_op = 0x0a 142 }; 143 144 /* 145 * fmt field of cop1 opcodes. 146 */ 147 enum cop1_fmt { 148 s_fmt, d_fmt, e_fmt, q_fmt, 149 w_fmt, l_fmt 150 }; 151 152 /* 153 * func field of cop1 instructions using d, s or w format. 154 */ 155 enum cop1_sdw_func { 156 fadd_op = 0x00, fsub_op = 0x01, 157 fmul_op = 0x02, fdiv_op = 0x03, 158 fsqrt_op = 0x04, fabs_op = 0x05, 159 fmov_op = 0x06, fneg_op = 0x07, 160 froundl_op = 0x08, ftruncl_op = 0x09, 161 fceill_op = 0x0a, ffloorl_op = 0x0b, 162 fround_op = 0x0c, ftrunc_op = 0x0d, 163 fceil_op = 0x0e, ffloor_op = 0x0f, 164 fmovc_op = 0x11, fmovz_op = 0x12, 165 fmovn_op = 0x13, frecip_op = 0x15, 166 frsqrt_op = 0x16, fcvts_op = 0x20, 167 fcvtd_op = 0x21, fcvte_op = 0x22, 168 fcvtw_op = 0x24, fcvtl_op = 0x25, 169 fcmp_op = 0x30 170 }; 171 172 /* 173 * func field of cop1x opcodes (MIPS IV). 174 */ 175 enum cop1x_func { 176 lwxc1_op = 0x00, ldxc1_op = 0x01, 177 swxc1_op = 0x08, sdxc1_op = 0x09, 178 pfetch_op = 0x0f, madd_s_op = 0x20, 179 madd_d_op = 0x21, madd_e_op = 0x22, 180 msub_s_op = 0x28, msub_d_op = 0x29, 181 msub_e_op = 0x2a, nmadd_s_op = 0x30, 182 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 183 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 184 nmsub_e_op = 0x3a 185 }; 186 187 /* 188 * func field for mad opcodes (MIPS IV). 189 */ 190 enum mad_func { 191 madd_fp_op = 0x08, msub_fp_op = 0x0a, 192 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 193 }; 194 195 /* 196 * func field for special3 lx opcodes (Cavium Octeon). 197 */ 198 enum lx_func { 199 lwx_op = 0x00, 200 lhx_op = 0x04, 201 lbux_op = 0x06, 202 ldx_op = 0x08, 203 lwux_op = 0x10, 204 lhux_op = 0x14, 205 lbx_op = 0x16, 206 }; 207 208 /* 209 * BSHFL opcodes 210 */ 211 enum bshfl_func { 212 wsbh_op = 0x2, 213 dshd_op = 0x5, 214 seb_op = 0x10, 215 seh_op = 0x18, 216 }; 217 218 /* 219 * (microMIPS) Major opcodes. 220 */ 221 enum mm_major_op { 222 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 223 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 224 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 225 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 226 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 227 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, 228 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 229 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 230 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 231 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 232 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 233 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 234 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 235 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 236 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 237 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 238 }; 239 240 /* 241 * (microMIPS) POOL32I minor opcodes. 242 */ 243 enum mm_32i_minor_op { 244 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 245 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 246 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 247 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 248 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 249 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 250 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 251 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 252 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 253 }; 254 255 /* 256 * (microMIPS) POOL32A minor opcodes. 257 */ 258 enum mm_32a_minor_op { 259 mm_sll32_op = 0x000, 260 mm_ins_op = 0x00c, 261 mm_sllv32_op = 0x010, 262 mm_ext_op = 0x02c, 263 mm_pool32axf_op = 0x03c, 264 mm_srl32_op = 0x040, 265 mm_sra_op = 0x080, 266 mm_srlv32_op = 0x090, 267 mm_rotr_op = 0x0c0, 268 mm_lwxs_op = 0x118, 269 mm_addu32_op = 0x150, 270 mm_subu32_op = 0x1d0, 271 mm_wsbh_op = 0x1ec, 272 mm_mul_op = 0x210, 273 mm_and_op = 0x250, 274 mm_or32_op = 0x290, 275 mm_xor32_op = 0x310, 276 mm_slt_op = 0x350, 277 mm_sltu_op = 0x390, 278 }; 279 280 /* 281 * (microMIPS) POOL32B functions. 282 */ 283 enum mm_32b_func { 284 mm_lwc2_func = 0x0, 285 mm_lwp_func = 0x1, 286 mm_ldc2_func = 0x2, 287 mm_ldp_func = 0x4, 288 mm_lwm32_func = 0x5, 289 mm_cache_func = 0x6, 290 mm_ldm_func = 0x7, 291 mm_swc2_func = 0x8, 292 mm_swp_func = 0x9, 293 mm_sdc2_func = 0xa, 294 mm_sdp_func = 0xc, 295 mm_swm32_func = 0xd, 296 mm_sdm_func = 0xf, 297 }; 298 299 /* 300 * (microMIPS) POOL32C functions. 301 */ 302 enum mm_32c_func { 303 mm_pref_func = 0x2, 304 mm_ll_func = 0x3, 305 mm_swr_func = 0x9, 306 mm_sc_func = 0xb, 307 mm_lwu_func = 0xe, 308 }; 309 310 /* 311 * (microMIPS) POOL32AXF minor opcodes. 312 */ 313 enum mm_32axf_minor_op { 314 mm_mfc0_op = 0x003, 315 mm_mtc0_op = 0x00b, 316 mm_tlbp_op = 0x00d, 317 mm_mfhi32_op = 0x035, 318 mm_jalr_op = 0x03c, 319 mm_tlbr_op = 0x04d, 320 mm_mflo32_op = 0x075, 321 mm_jalrhb_op = 0x07c, 322 mm_tlbwi_op = 0x08d, 323 mm_tlbwr_op = 0x0cd, 324 mm_jalrs_op = 0x13c, 325 mm_jalrshb_op = 0x17c, 326 mm_sync_op = 0x1ad, 327 mm_syscall_op = 0x22d, 328 mm_wait_op = 0x24d, 329 mm_eret_op = 0x3cd, 330 mm_divu_op = 0x5dc, 331 }; 332 333 /* 334 * (microMIPS) POOL32F minor opcodes. 335 */ 336 enum mm_32f_minor_op { 337 mm_32f_00_op = 0x00, 338 mm_32f_01_op = 0x01, 339 mm_32f_02_op = 0x02, 340 mm_32f_10_op = 0x08, 341 mm_32f_11_op = 0x09, 342 mm_32f_12_op = 0x0a, 343 mm_32f_20_op = 0x10, 344 mm_32f_30_op = 0x18, 345 mm_32f_40_op = 0x20, 346 mm_32f_41_op = 0x21, 347 mm_32f_42_op = 0x22, 348 mm_32f_50_op = 0x28, 349 mm_32f_51_op = 0x29, 350 mm_32f_52_op = 0x2a, 351 mm_32f_60_op = 0x30, 352 mm_32f_70_op = 0x38, 353 mm_32f_73_op = 0x3b, 354 mm_32f_74_op = 0x3c, 355 }; 356 357 /* 358 * (microMIPS) POOL32F secondary minor opcodes. 359 */ 360 enum mm_32f_10_minor_op { 361 mm_lwxc1_op = 0x1, 362 mm_swxc1_op, 363 mm_ldxc1_op, 364 mm_sdxc1_op, 365 mm_luxc1_op, 366 mm_suxc1_op, 367 }; 368 369 enum mm_32f_func { 370 mm_lwxc1_func = 0x048, 371 mm_swxc1_func = 0x088, 372 mm_ldxc1_func = 0x0c8, 373 mm_sdxc1_func = 0x108, 374 }; 375 376 /* 377 * (microMIPS) POOL32F secondary minor opcodes. 378 */ 379 enum mm_32f_40_minor_op { 380 mm_fmovf_op, 381 mm_fmovt_op, 382 }; 383 384 /* 385 * (microMIPS) POOL32F secondary minor opcodes. 386 */ 387 enum mm_32f_60_minor_op { 388 mm_fadd_op, 389 mm_fsub_op, 390 mm_fmul_op, 391 mm_fdiv_op, 392 }; 393 394 /* 395 * (microMIPS) POOL32F secondary minor opcodes. 396 */ 397 enum mm_32f_70_minor_op { 398 mm_fmovn_op, 399 mm_fmovz_op, 400 }; 401 402 /* 403 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 404 */ 405 enum mm_32f_73_minor_op { 406 mm_fmov0_op = 0x01, 407 mm_fcvtl_op = 0x04, 408 mm_movf0_op = 0x05, 409 mm_frsqrt_op = 0x08, 410 mm_ffloorl_op = 0x0c, 411 mm_fabs0_op = 0x0d, 412 mm_fcvtw_op = 0x24, 413 mm_movt0_op = 0x25, 414 mm_fsqrt_op = 0x28, 415 mm_ffloorw_op = 0x2c, 416 mm_fneg0_op = 0x2d, 417 mm_cfc1_op = 0x40, 418 mm_frecip_op = 0x48, 419 mm_fceill_op = 0x4c, 420 mm_fcvtd0_op = 0x4d, 421 mm_ctc1_op = 0x60, 422 mm_fceilw_op = 0x6c, 423 mm_fcvts0_op = 0x6d, 424 mm_mfc1_op = 0x80, 425 mm_fmov1_op = 0x81, 426 mm_movf1_op = 0x85, 427 mm_ftruncl_op = 0x8c, 428 mm_fabs1_op = 0x8d, 429 mm_mtc1_op = 0xa0, 430 mm_movt1_op = 0xa5, 431 mm_ftruncw_op = 0xac, 432 mm_fneg1_op = 0xad, 433 mm_mfhc1_op = 0xc0, 434 mm_froundl_op = 0xcc, 435 mm_fcvtd1_op = 0xcd, 436 mm_mthc1_op = 0xe0, 437 mm_froundw_op = 0xec, 438 mm_fcvts1_op = 0xed, 439 }; 440 441 /* 442 * (microMIPS) POOL16C minor opcodes. 443 */ 444 enum mm_16c_minor_op { 445 mm_lwm16_op = 0x04, 446 mm_swm16_op = 0x05, 447 mm_jr16_op = 0x0c, 448 mm_jrc_op = 0x0d, 449 mm_jalr16_op = 0x0e, 450 mm_jalrs16_op = 0x0f, 451 mm_jraddiusp_op = 0x18, 452 }; 453 454 /* 455 * (microMIPS) POOL16D minor opcodes. 456 */ 457 enum mm_16d_minor_op { 458 mm_addius5_func, 459 mm_addiusp_func, 460 }; 461 462 /* 463 * (MIPS16e) opcodes. 464 */ 465 enum MIPS16e_ops { 466 MIPS16e_jal_op = 003, 467 MIPS16e_ld_op = 007, 468 MIPS16e_i8_op = 014, 469 MIPS16e_sd_op = 017, 470 MIPS16e_lb_op = 020, 471 MIPS16e_lh_op = 021, 472 MIPS16e_lwsp_op = 022, 473 MIPS16e_lw_op = 023, 474 MIPS16e_lbu_op = 024, 475 MIPS16e_lhu_op = 025, 476 MIPS16e_lwpc_op = 026, 477 MIPS16e_lwu_op = 027, 478 MIPS16e_sb_op = 030, 479 MIPS16e_sh_op = 031, 480 MIPS16e_swsp_op = 032, 481 MIPS16e_sw_op = 033, 482 MIPS16e_rr_op = 035, 483 MIPS16e_extend_op = 036, 484 MIPS16e_i64_op = 037, 485 }; 486 487 enum MIPS16e_i64_func { 488 MIPS16e_ldsp_func, 489 MIPS16e_sdsp_func, 490 MIPS16e_sdrasp_func, 491 MIPS16e_dadjsp_func, 492 MIPS16e_ldpc_func, 493 }; 494 495 enum MIPS16e_rr_func { 496 MIPS16e_jr_func, 497 }; 498 499 enum MIPS6e_i8_func { 500 MIPS16e_swrasp_func = 02, 501 }; 502 503 /* 504 * (microMIPS & MIPS16e) NOP instruction. 505 */ 506 #define MM_NOP16 0x0c00 507 508 struct j_format { 509 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 510 __BITFIELD_FIELD(unsigned int target : 26, 511 ;)) 512 }; 513 514 struct i_format { /* signed immediate format */ 515 __BITFIELD_FIELD(unsigned int opcode : 6, 516 __BITFIELD_FIELD(unsigned int rs : 5, 517 __BITFIELD_FIELD(unsigned int rt : 5, 518 __BITFIELD_FIELD(signed int simmediate : 16, 519 ;)))) 520 }; 521 522 struct u_format { /* unsigned immediate format */ 523 __BITFIELD_FIELD(unsigned int opcode : 6, 524 __BITFIELD_FIELD(unsigned int rs : 5, 525 __BITFIELD_FIELD(unsigned int rt : 5, 526 __BITFIELD_FIELD(unsigned int uimmediate : 16, 527 ;)))) 528 }; 529 530 struct c_format { /* Cache (>= R6000) format */ 531 __BITFIELD_FIELD(unsigned int opcode : 6, 532 __BITFIELD_FIELD(unsigned int rs : 5, 533 __BITFIELD_FIELD(unsigned int c_op : 3, 534 __BITFIELD_FIELD(unsigned int cache : 2, 535 __BITFIELD_FIELD(unsigned int simmediate : 16, 536 ;))))) 537 }; 538 539 struct r_format { /* Register format */ 540 __BITFIELD_FIELD(unsigned int opcode : 6, 541 __BITFIELD_FIELD(unsigned int rs : 5, 542 __BITFIELD_FIELD(unsigned int rt : 5, 543 __BITFIELD_FIELD(unsigned int rd : 5, 544 __BITFIELD_FIELD(unsigned int re : 5, 545 __BITFIELD_FIELD(unsigned int func : 6, 546 ;)))))) 547 }; 548 549 struct p_format { /* Performance counter format (R10000) */ 550 __BITFIELD_FIELD(unsigned int opcode : 6, 551 __BITFIELD_FIELD(unsigned int rs : 5, 552 __BITFIELD_FIELD(unsigned int rt : 5, 553 __BITFIELD_FIELD(unsigned int rd : 5, 554 __BITFIELD_FIELD(unsigned int re : 5, 555 __BITFIELD_FIELD(unsigned int func : 6, 556 ;)))))) 557 }; 558 559 struct f_format { /* FPU register format */ 560 __BITFIELD_FIELD(unsigned int opcode : 6, 561 __BITFIELD_FIELD(unsigned int : 1, 562 __BITFIELD_FIELD(unsigned int fmt : 4, 563 __BITFIELD_FIELD(unsigned int rt : 5, 564 __BITFIELD_FIELD(unsigned int rd : 5, 565 __BITFIELD_FIELD(unsigned int re : 5, 566 __BITFIELD_FIELD(unsigned int func : 6, 567 ;))))))) 568 }; 569 570 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 571 __BITFIELD_FIELD(unsigned int opcode : 6, 572 __BITFIELD_FIELD(unsigned int fr : 5, 573 __BITFIELD_FIELD(unsigned int ft : 5, 574 __BITFIELD_FIELD(unsigned int fs : 5, 575 __BITFIELD_FIELD(unsigned int fd : 5, 576 __BITFIELD_FIELD(unsigned int func : 4, 577 __BITFIELD_FIELD(unsigned int fmt : 2, 578 ;))))))) 579 }; 580 581 struct b_format { /* BREAK and SYSCALL */ 582 __BITFIELD_FIELD(unsigned int opcode : 6, 583 __BITFIELD_FIELD(unsigned int code : 20, 584 __BITFIELD_FIELD(unsigned int func : 6, 585 ;))) 586 }; 587 588 struct ps_format { /* MIPS-3D / paired single format */ 589 __BITFIELD_FIELD(unsigned int opcode : 6, 590 __BITFIELD_FIELD(unsigned int rs : 5, 591 __BITFIELD_FIELD(unsigned int ft : 5, 592 __BITFIELD_FIELD(unsigned int fs : 5, 593 __BITFIELD_FIELD(unsigned int fd : 5, 594 __BITFIELD_FIELD(unsigned int func : 6, 595 ;)))))) 596 }; 597 598 struct v_format { /* MDMX vector format */ 599 __BITFIELD_FIELD(unsigned int opcode : 6, 600 __BITFIELD_FIELD(unsigned int sel : 4, 601 __BITFIELD_FIELD(unsigned int fmt : 1, 602 __BITFIELD_FIELD(unsigned int vt : 5, 603 __BITFIELD_FIELD(unsigned int vs : 5, 604 __BITFIELD_FIELD(unsigned int vd : 5, 605 __BITFIELD_FIELD(unsigned int func : 6, 606 ;))))))) 607 }; 608 609 struct spec3_format { /* SPEC3 */ 610 __BITFIELD_FIELD(unsigned int opcode:6, 611 __BITFIELD_FIELD(unsigned int rs:5, 612 __BITFIELD_FIELD(unsigned int rt:5, 613 __BITFIELD_FIELD(signed int simmediate:9, 614 __BITFIELD_FIELD(unsigned int func:7, 615 ;))))) 616 }; 617 618 /* 619 * microMIPS instruction formats (32-bit length) 620 * 621 * NOTE: 622 * Parenthesis denote whether the format is a microMIPS instruction or 623 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 624 */ 625 struct fb_format { /* FPU branch format (MIPS32) */ 626 __BITFIELD_FIELD(unsigned int opcode : 6, 627 __BITFIELD_FIELD(unsigned int bc : 5, 628 __BITFIELD_FIELD(unsigned int cc : 3, 629 __BITFIELD_FIELD(unsigned int flag : 2, 630 __BITFIELD_FIELD(signed int simmediate : 16, 631 ;))))) 632 }; 633 634 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 635 __BITFIELD_FIELD(unsigned int opcode : 6, 636 __BITFIELD_FIELD(unsigned int fmt : 5, 637 __BITFIELD_FIELD(unsigned int ft : 5, 638 __BITFIELD_FIELD(unsigned int fs : 5, 639 __BITFIELD_FIELD(unsigned int fd : 5, 640 __BITFIELD_FIELD(unsigned int func : 6, 641 ;)))))) 642 }; 643 644 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 645 __BITFIELD_FIELD(unsigned int opcode : 6, 646 __BITFIELD_FIELD(unsigned int ft : 5, 647 __BITFIELD_FIELD(unsigned int fs : 5, 648 __BITFIELD_FIELD(unsigned int fd : 5, 649 __BITFIELD_FIELD(unsigned int fmt : 3, 650 __BITFIELD_FIELD(unsigned int op : 2, 651 __BITFIELD_FIELD(unsigned int func : 6, 652 ;))))))) 653 }; 654 655 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 656 __BITFIELD_FIELD(unsigned int opcode : 6, 657 __BITFIELD_FIELD(unsigned int op : 5, 658 __BITFIELD_FIELD(unsigned int rt : 5, 659 __BITFIELD_FIELD(unsigned int fs : 5, 660 __BITFIELD_FIELD(unsigned int fd : 5, 661 __BITFIELD_FIELD(unsigned int func : 6, 662 ;)))))) 663 }; 664 665 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 666 __BITFIELD_FIELD(unsigned int opcode : 6, 667 __BITFIELD_FIELD(unsigned int rt : 5, 668 __BITFIELD_FIELD(unsigned int fs : 5, 669 __BITFIELD_FIELD(unsigned int fmt : 2, 670 __BITFIELD_FIELD(unsigned int op : 8, 671 __BITFIELD_FIELD(unsigned int func : 6, 672 ;)))))) 673 }; 674 675 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 676 __BITFIELD_FIELD(unsigned int opcode : 6, 677 __BITFIELD_FIELD(unsigned int fd : 5, 678 __BITFIELD_FIELD(unsigned int fs : 5, 679 __BITFIELD_FIELD(unsigned int cc : 3, 680 __BITFIELD_FIELD(unsigned int zero : 2, 681 __BITFIELD_FIELD(unsigned int fmt : 2, 682 __BITFIELD_FIELD(unsigned int op : 3, 683 __BITFIELD_FIELD(unsigned int func : 6, 684 ;)))))))) 685 }; 686 687 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 688 __BITFIELD_FIELD(unsigned int opcode : 6, 689 __BITFIELD_FIELD(unsigned int rt : 5, 690 __BITFIELD_FIELD(unsigned int fs : 5, 691 __BITFIELD_FIELD(unsigned int fmt : 3, 692 __BITFIELD_FIELD(unsigned int op : 7, 693 __BITFIELD_FIELD(unsigned int func : 6, 694 ;)))))) 695 }; 696 697 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 698 __BITFIELD_FIELD(unsigned int opcode : 6, 699 __BITFIELD_FIELD(unsigned int rt : 5, 700 __BITFIELD_FIELD(unsigned int fs : 5, 701 __BITFIELD_FIELD(unsigned int cc : 3, 702 __BITFIELD_FIELD(unsigned int fmt : 3, 703 __BITFIELD_FIELD(unsigned int cond : 4, 704 __BITFIELD_FIELD(unsigned int func : 6, 705 ;))))))) 706 }; 707 708 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 709 __BITFIELD_FIELD(unsigned int opcode : 6, 710 __BITFIELD_FIELD(unsigned int index : 5, 711 __BITFIELD_FIELD(unsigned int base : 5, 712 __BITFIELD_FIELD(unsigned int fd : 5, 713 __BITFIELD_FIELD(unsigned int op : 5, 714 __BITFIELD_FIELD(unsigned int func : 6, 715 ;)))))) 716 }; 717 718 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 719 __BITFIELD_FIELD(unsigned int opcode : 6, 720 __BITFIELD_FIELD(unsigned int fr : 5, 721 __BITFIELD_FIELD(unsigned int ft : 5, 722 __BITFIELD_FIELD(unsigned int fs : 5, 723 __BITFIELD_FIELD(unsigned int fd : 5, 724 __BITFIELD_FIELD(unsigned int func : 6, 725 ;)))))) 726 }; 727 728 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 729 __BITFIELD_FIELD(unsigned int opcode : 6, 730 __BITFIELD_FIELD(unsigned int ft : 5, 731 __BITFIELD_FIELD(unsigned int fs : 5, 732 __BITFIELD_FIELD(unsigned int fd : 5, 733 __BITFIELD_FIELD(unsigned int fr : 5, 734 __BITFIELD_FIELD(unsigned int func : 6, 735 ;)))))) 736 }; 737 738 struct mm_i_format { /* Immediate format (microMIPS) */ 739 __BITFIELD_FIELD(unsigned int opcode : 6, 740 __BITFIELD_FIELD(unsigned int rt : 5, 741 __BITFIELD_FIELD(unsigned int rs : 5, 742 __BITFIELD_FIELD(signed int simmediate : 16, 743 ;)))) 744 }; 745 746 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 747 __BITFIELD_FIELD(unsigned int opcode : 6, 748 __BITFIELD_FIELD(unsigned int rd : 5, 749 __BITFIELD_FIELD(unsigned int base : 5, 750 __BITFIELD_FIELD(unsigned int func : 4, 751 __BITFIELD_FIELD(signed int simmediate : 12, 752 ;))))) 753 }; 754 755 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 756 __BITFIELD_FIELD(unsigned int opcode : 6, 757 __BITFIELD_FIELD(unsigned int index : 5, 758 __BITFIELD_FIELD(unsigned int base : 5, 759 __BITFIELD_FIELD(unsigned int rd : 5, 760 __BITFIELD_FIELD(unsigned int func : 11, 761 ;))))) 762 }; 763 764 /* 765 * microMIPS instruction formats (16-bit length) 766 */ 767 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 768 __BITFIELD_FIELD(unsigned int opcode : 6, 769 __BITFIELD_FIELD(signed int simmediate : 10, 770 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 771 ;))) 772 }; 773 774 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 775 __BITFIELD_FIELD(unsigned int opcode : 6, 776 __BITFIELD_FIELD(unsigned int rs : 3, 777 __BITFIELD_FIELD(signed int simmediate : 7, 778 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 779 ;)))) 780 }; 781 782 struct mm16_m_format { /* Multi-word load/store format */ 783 __BITFIELD_FIELD(unsigned int opcode : 6, 784 __BITFIELD_FIELD(unsigned int func : 4, 785 __BITFIELD_FIELD(unsigned int rlist : 2, 786 __BITFIELD_FIELD(unsigned int imm : 4, 787 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 788 ;))))) 789 }; 790 791 struct mm16_rb_format { /* Signed immediate format */ 792 __BITFIELD_FIELD(unsigned int opcode : 6, 793 __BITFIELD_FIELD(unsigned int rt : 3, 794 __BITFIELD_FIELD(unsigned int base : 3, 795 __BITFIELD_FIELD(signed int simmediate : 4, 796 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 797 ;))))) 798 }; 799 800 struct mm16_r3_format { /* Load from global pointer format */ 801 __BITFIELD_FIELD(unsigned int opcode : 6, 802 __BITFIELD_FIELD(unsigned int rt : 3, 803 __BITFIELD_FIELD(signed int simmediate : 7, 804 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 805 ;)))) 806 }; 807 808 struct mm16_r5_format { /* Load/store from stack pointer format */ 809 __BITFIELD_FIELD(unsigned int opcode : 6, 810 __BITFIELD_FIELD(unsigned int rt : 5, 811 __BITFIELD_FIELD(signed int simmediate : 5, 812 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 813 ;)))) 814 }; 815 816 /* 817 * MIPS16e instruction formats (16-bit length) 818 */ 819 struct m16e_rr { 820 __BITFIELD_FIELD(unsigned int opcode : 5, 821 __BITFIELD_FIELD(unsigned int rx : 3, 822 __BITFIELD_FIELD(unsigned int nd : 1, 823 __BITFIELD_FIELD(unsigned int l : 1, 824 __BITFIELD_FIELD(unsigned int ra : 1, 825 __BITFIELD_FIELD(unsigned int func : 5, 826 ;)))))) 827 }; 828 829 struct m16e_jal { 830 __BITFIELD_FIELD(unsigned int opcode : 5, 831 __BITFIELD_FIELD(unsigned int x : 1, 832 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 833 __BITFIELD_FIELD(signed int imm25_21 : 5, 834 ;)))) 835 }; 836 837 struct m16e_i64 { 838 __BITFIELD_FIELD(unsigned int opcode : 5, 839 __BITFIELD_FIELD(unsigned int func : 3, 840 __BITFIELD_FIELD(unsigned int imm : 8, 841 ;))) 842 }; 843 844 struct m16e_ri64 { 845 __BITFIELD_FIELD(unsigned int opcode : 5, 846 __BITFIELD_FIELD(unsigned int func : 3, 847 __BITFIELD_FIELD(unsigned int ry : 3, 848 __BITFIELD_FIELD(unsigned int imm : 5, 849 ;)))) 850 }; 851 852 struct m16e_ri { 853 __BITFIELD_FIELD(unsigned int opcode : 5, 854 __BITFIELD_FIELD(unsigned int rx : 3, 855 __BITFIELD_FIELD(unsigned int imm : 8, 856 ;))) 857 }; 858 859 struct m16e_rri { 860 __BITFIELD_FIELD(unsigned int opcode : 5, 861 __BITFIELD_FIELD(unsigned int rx : 3, 862 __BITFIELD_FIELD(unsigned int ry : 3, 863 __BITFIELD_FIELD(unsigned int imm : 5, 864 ;)))) 865 }; 866 867 struct m16e_i8 { 868 __BITFIELD_FIELD(unsigned int opcode : 5, 869 __BITFIELD_FIELD(unsigned int func : 3, 870 __BITFIELD_FIELD(unsigned int imm : 8, 871 ;))) 872 }; 873 874 union mips_instruction { 875 unsigned int word; 876 unsigned short halfword[2]; 877 unsigned char byte[4]; 878 struct j_format j_format; 879 struct i_format i_format; 880 struct u_format u_format; 881 struct c_format c_format; 882 struct r_format r_format; 883 struct p_format p_format; 884 struct f_format f_format; 885 struct ma_format ma_format; 886 struct b_format b_format; 887 struct ps_format ps_format; 888 struct v_format v_format; 889 struct spec3_format spec3_format; 890 struct fb_format fb_format; 891 struct fp0_format fp0_format; 892 struct mm_fp0_format mm_fp0_format; 893 struct fp1_format fp1_format; 894 struct mm_fp1_format mm_fp1_format; 895 struct mm_fp2_format mm_fp2_format; 896 struct mm_fp3_format mm_fp3_format; 897 struct mm_fp4_format mm_fp4_format; 898 struct mm_fp5_format mm_fp5_format; 899 struct fp6_format fp6_format; 900 struct mm_fp6_format mm_fp6_format; 901 struct mm_i_format mm_i_format; 902 struct mm_m_format mm_m_format; 903 struct mm_x_format mm_x_format; 904 struct mm_b0_format mm_b0_format; 905 struct mm_b1_format mm_b1_format; 906 struct mm16_m_format mm16_m_format ; 907 struct mm16_rb_format mm16_rb_format; 908 struct mm16_r3_format mm16_r3_format; 909 struct mm16_r5_format mm16_r5_format; 910 }; 911 912 union mips16e_instruction { 913 unsigned int full : 16; 914 struct m16e_rr rr; 915 struct m16e_jal jal; 916 struct m16e_i64 i64; 917 struct m16e_ri64 ri64; 918 struct m16e_ri ri; 919 struct m16e_rri rri; 920 struct m16e_i8 i8; 921 }; 922 923 #endif /* _UAPI_ASM_INST_H */ 924