1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * Copyright (C) 2001, 2002, MontaVista Software Inc. 3384740dcSRalf Baechle * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4384740dcSRalf Baechle * Copyright (c) 2003 Maciej W. Rozycki 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * include/asm-mips/time.h 7384740dcSRalf Baechle * header file for the new style time.c file and time services. 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * This program is free software; you can redistribute it and/or modify it 10384740dcSRalf Baechle * under the terms of the GNU General Public License as published by the 11384740dcSRalf Baechle * Free Software Foundation; either version 2 of the License, or (at your 12384740dcSRalf Baechle * option) any later version. 13384740dcSRalf Baechle */ 14384740dcSRalf Baechle #ifndef _ASM_TIME_H 15384740dcSRalf Baechle #define _ASM_TIME_H 16384740dcSRalf Baechle 17384740dcSRalf Baechle #include <linux/rtc.h> 18384740dcSRalf Baechle #include <linux/spinlock.h> 19384740dcSRalf Baechle #include <linux/clockchips.h> 20384740dcSRalf Baechle #include <linux/clocksource.h> 21384740dcSRalf Baechle 22384740dcSRalf Baechle extern spinlock_t rtc_lock; 23384740dcSRalf Baechle 24384740dcSRalf Baechle /* 25384740dcSRalf Baechle * RTC ops. By default, they point to weak no-op RTC functions. 26384740dcSRalf Baechle * rtc_mips_set_time - reverse the above translation and set time to RTC. 27384740dcSRalf Baechle * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need 28384740dcSRalf Baechle * to be set. Used by RTC sync-up. 29384740dcSRalf Baechle */ 30384740dcSRalf Baechle extern int rtc_mips_set_time(unsigned long); 31384740dcSRalf Baechle extern int rtc_mips_set_mmss(unsigned long); 32384740dcSRalf Baechle 33384740dcSRalf Baechle /* 34384740dcSRalf Baechle * board specific routines required by time_init(). 35384740dcSRalf Baechle */ 36384740dcSRalf Baechle extern void plat_time_init(void); 37384740dcSRalf Baechle 38384740dcSRalf Baechle /* 39384740dcSRalf Baechle * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 40384740dcSRalf Baechle * counter as a timer interrupt source. 41384740dcSRalf Baechle */ 42384740dcSRalf Baechle extern unsigned int mips_hpt_frequency; 43384740dcSRalf Baechle 44384740dcSRalf Baechle /* 45384740dcSRalf Baechle * The performance counter IRQ on MIPS is a close relative to the timer IRQ 46384740dcSRalf Baechle * so it lives here. 47384740dcSRalf Baechle */ 48384740dcSRalf Baechle extern int (*perf_irq)(void); 49a669efc4SAndrew Bresticker extern int __weak get_c0_perfcount_int(void); 50384740dcSRalf Baechle 51384740dcSRalf Baechle /* 52384740dcSRalf Baechle * Initialize the calling CPU's compare interrupt as clockevent device 53384740dcSRalf Baechle */ 54384740dcSRalf Baechle extern unsigned int __weak get_c0_compare_int(void); 55779e7d41SManuel Lauss extern int r4k_clockevent_init(void); 56779e7d41SManuel Lauss 57384740dcSRalf Baechle static inline int mips_clockevent_init(void) 58384740dcSRalf Baechle { 59e4752dbbSAndrew Bresticker #ifdef CONFIG_CEVT_R4K 60779e7d41SManuel Lauss return r4k_clockevent_init(); 61779e7d41SManuel Lauss #else 62384740dcSRalf Baechle return -ENXIO; 63384740dcSRalf Baechle #endif 64779e7d41SManuel Lauss } 65384740dcSRalf Baechle 66384740dcSRalf Baechle /* 67384740dcSRalf Baechle * Initialize the count register as a clocksource 68384740dcSRalf Baechle */ 69779e7d41SManuel Lauss extern int init_r4k_clocksource(void); 70779e7d41SManuel Lauss 71384740dcSRalf Baechle static inline int init_mips_clocksource(void) 72384740dcSRalf Baechle { 73f7886e87SSteven J. Hill #ifdef CONFIG_CSRC_R4K 74779e7d41SManuel Lauss return init_r4k_clocksource(); 75779e7d41SManuel Lauss #else 76384740dcSRalf Baechle return 0; 77384740dcSRalf Baechle #endif 78779e7d41SManuel Lauss } 79384740dcSRalf Baechle 80e3a4fab0SThomas Gleixner static inline void clockevent_set_clock(struct clock_event_device *cd, 81e3a4fab0SThomas Gleixner unsigned int clock) 82e3a4fab0SThomas Gleixner { 83e3a4fab0SThomas Gleixner clockevents_calc_mult_shift(cd, clock, 4); 84e3a4fab0SThomas Gleixner } 85384740dcSRalf Baechle 86384740dcSRalf Baechle #endif /* _ASM_TIME_H */ 87