xref: /openbmc/linux/arch/mips/include/asm/stackframe.h (revision 12eb4683) 
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7  * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8  * Copyright (C) 1999 Silicon Graphics, Inc.
9  * Copyright (C) 2007  Maciej W. Rozycki
10  */
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
13 
14 #include <linux/threads.h>
15 
16 #include <asm/asm.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/thread_info.h>
21 
22 /*
23  * For SMTC kernel, global IE should be left set, and interrupts
24  * controlled exclusively via IXMT.
25  */
26 #ifdef CONFIG_MIPS_MT_SMTC
27 #define STATMASK 0x1e
28 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
29 #define STATMASK 0x3f
30 #else
31 #define STATMASK 0x1f
32 #endif
33 
34 #ifdef CONFIG_MIPS_MT_SMTC
35 #include <asm/mipsmtregs.h>
36 #endif /* CONFIG_MIPS_MT_SMTC */
37 
38 		.macro	SAVE_AT
39 		.set	push
40 		.set	noat
41 		LONG_S	$1, PT_R1(sp)
42 		.set	pop
43 		.endm
44 
45 		.macro	SAVE_TEMP
46 #ifdef CONFIG_CPU_HAS_SMARTMIPS
47 		mflhxu	v1
48 		LONG_S	v1, PT_LO(sp)
49 		mflhxu	v1
50 		LONG_S	v1, PT_HI(sp)
51 		mflhxu	v1
52 		LONG_S	v1, PT_ACX(sp)
53 #else
54 		mfhi	v1
55 #endif
56 #ifdef CONFIG_32BIT
57 		LONG_S	$8, PT_R8(sp)
58 		LONG_S	$9, PT_R9(sp)
59 #endif
60 		LONG_S	$10, PT_R10(sp)
61 		LONG_S	$11, PT_R11(sp)
62 		LONG_S	$12, PT_R12(sp)
63 #ifndef CONFIG_CPU_HAS_SMARTMIPS
64 		LONG_S	v1, PT_HI(sp)
65 		mflo	v1
66 #endif
67 		LONG_S	$13, PT_R13(sp)
68 		LONG_S	$14, PT_R14(sp)
69 		LONG_S	$15, PT_R15(sp)
70 		LONG_S	$24, PT_R24(sp)
71 #ifndef CONFIG_CPU_HAS_SMARTMIPS
72 		LONG_S	v1, PT_LO(sp)
73 #endif
74 #ifdef CONFIG_CPU_CAVIUM_OCTEON
75 		/*
76 		 * The Octeon multiplier state is affected by general
77 		 * multiply instructions. It must be saved before and
78 		 * kernel code might corrupt it
79 		 */
80 		jal     octeon_mult_save
81 #endif
82 		.endm
83 
84 		.macro	SAVE_STATIC
85 		LONG_S	$16, PT_R16(sp)
86 		LONG_S	$17, PT_R17(sp)
87 		LONG_S	$18, PT_R18(sp)
88 		LONG_S	$19, PT_R19(sp)
89 		LONG_S	$20, PT_R20(sp)
90 		LONG_S	$21, PT_R21(sp)
91 		LONG_S	$22, PT_R22(sp)
92 		LONG_S	$23, PT_R23(sp)
93 		LONG_S	$30, PT_R30(sp)
94 		.endm
95 
96 #ifdef CONFIG_SMP
97 		.macro	get_saved_sp	/* SMP variation */
98 		ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
99 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
100 		lui	k1, %hi(kernelsp)
101 #else
102 		lui	k1, %highest(kernelsp)
103 		daddiu	k1, %higher(kernelsp)
104 		dsll	k1, 16
105 		daddiu	k1, %hi(kernelsp)
106 		dsll	k1, 16
107 #endif
108 		LONG_SRL	k0, SMP_CPUID_PTRSHIFT
109 		LONG_ADDU	k1, k0
110 		LONG_L	k1, %lo(kernelsp)(k1)
111 		.endm
112 
113 		.macro	set_saved_sp stackp temp temp2
114 		ASM_CPUID_MFC0	\temp, ASM_SMP_CPUID_REG
115 		LONG_SRL	\temp, SMP_CPUID_PTRSHIFT
116 		LONG_S	\stackp, kernelsp(\temp)
117 		.endm
118 #else /* !CONFIG_SMP */
119 		.macro	get_saved_sp	/* Uniprocessor variation */
120 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
121 		/*
122 		 * Clear BTB (branch target buffer), forbid RAS (return address
123 		 * stack) to workaround the Out-of-order Issue in Loongson2F
124 		 * via its diagnostic register.
125 		 */
126 		move	k0, ra
127 		jal	1f
128 		 nop
129 1:		jal	1f
130 		 nop
131 1:		jal	1f
132 		 nop
133 1:		jal	1f
134 		 nop
135 1:		move	ra, k0
136 		li	k0, 3
137 		mtc0	k0, $22
138 #endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
139 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
140 		lui	k1, %hi(kernelsp)
141 #else
142 		lui	k1, %highest(kernelsp)
143 		daddiu	k1, %higher(kernelsp)
144 		dsll	k1, k1, 16
145 		daddiu	k1, %hi(kernelsp)
146 		dsll	k1, k1, 16
147 #endif
148 		LONG_L	k1, %lo(kernelsp)(k1)
149 		.endm
150 
151 		.macro	set_saved_sp stackp temp temp2
152 		LONG_S	\stackp, kernelsp
153 		.endm
154 #endif
155 
156 		.macro	SAVE_SOME
157 		.set	push
158 		.set	noat
159 		.set	reorder
160 		mfc0	k0, CP0_STATUS
161 		sll	k0, 3		/* extract cu0 bit */
162 		.set	noreorder
163 		bltz	k0, 8f
164 		 move	k1, sp
165 		.set	reorder
166 		/* Called from user mode, new stack. */
167 		get_saved_sp
168 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
169 8:		move	k0, sp
170 		PTR_SUBU sp, k1, PT_SIZE
171 #else
172 		.set	at=k0
173 8:		PTR_SUBU k1, PT_SIZE
174 		.set	noat
175 		move	k0, sp
176 		move	sp, k1
177 #endif
178 		LONG_S	k0, PT_R29(sp)
179 		LONG_S	$3, PT_R3(sp)
180 		/*
181 		 * You might think that you don't need to save $0,
182 		 * but the FPU emulator and gdb remote debug stub
183 		 * need it to operate correctly
184 		 */
185 		LONG_S	$0, PT_R0(sp)
186 		mfc0	v1, CP0_STATUS
187 		LONG_S	$2, PT_R2(sp)
188 		LONG_S	v1, PT_STATUS(sp)
189 #ifdef CONFIG_MIPS_MT_SMTC
190 		/*
191 		 * Ideally, these instructions would be shuffled in
192 		 * to cover the pipeline delay.
193 		 */
194 		.set	mips32
195 		mfc0	k0, CP0_TCSTATUS
196 		.set	mips0
197 		LONG_S	k0, PT_TCSTATUS(sp)
198 #endif /* CONFIG_MIPS_MT_SMTC */
199 		LONG_S	$4, PT_R4(sp)
200 		mfc0	v1, CP0_CAUSE
201 		LONG_S	$5, PT_R5(sp)
202 		LONG_S	v1, PT_CAUSE(sp)
203 		LONG_S	$6, PT_R6(sp)
204 		MFC0	v1, CP0_EPC
205 		LONG_S	$7, PT_R7(sp)
206 #ifdef CONFIG_64BIT
207 		LONG_S	$8, PT_R8(sp)
208 		LONG_S	$9, PT_R9(sp)
209 #endif
210 		LONG_S	v1, PT_EPC(sp)
211 		LONG_S	$25, PT_R25(sp)
212 		LONG_S	$28, PT_R28(sp)
213 		LONG_S	$31, PT_R31(sp)
214 		ori	$28, sp, _THREAD_MASK
215 		xori	$28, _THREAD_MASK
216 #ifdef CONFIG_CPU_CAVIUM_OCTEON
217 		.set    mips64
218 		pref    0, 0($28)       /* Prefetch the current pointer */
219 #endif
220 		.set	pop
221 		.endm
222 
223 		.macro	SAVE_ALL
224 		SAVE_SOME
225 		SAVE_AT
226 		SAVE_TEMP
227 		SAVE_STATIC
228 		.endm
229 
230 		.macro	RESTORE_AT
231 		.set	push
232 		.set	noat
233 		LONG_L	$1,  PT_R1(sp)
234 		.set	pop
235 		.endm
236 
237 		.macro	RESTORE_TEMP
238 #ifdef CONFIG_CPU_CAVIUM_OCTEON
239 		/* Restore the Octeon multiplier state */
240 		jal	octeon_mult_restore
241 #endif
242 #ifdef CONFIG_CPU_HAS_SMARTMIPS
243 		LONG_L	$24, PT_ACX(sp)
244 		mtlhx	$24
245 		LONG_L	$24, PT_HI(sp)
246 		mtlhx	$24
247 		LONG_L	$24, PT_LO(sp)
248 		mtlhx	$24
249 #else
250 		LONG_L	$24, PT_LO(sp)
251 		mtlo	$24
252 		LONG_L	$24, PT_HI(sp)
253 		mthi	$24
254 #endif
255 #ifdef CONFIG_32BIT
256 		LONG_L	$8, PT_R8(sp)
257 		LONG_L	$9, PT_R9(sp)
258 #endif
259 		LONG_L	$10, PT_R10(sp)
260 		LONG_L	$11, PT_R11(sp)
261 		LONG_L	$12, PT_R12(sp)
262 		LONG_L	$13, PT_R13(sp)
263 		LONG_L	$14, PT_R14(sp)
264 		LONG_L	$15, PT_R15(sp)
265 		LONG_L	$24, PT_R24(sp)
266 		.endm
267 
268 		.macro	RESTORE_STATIC
269 		LONG_L	$16, PT_R16(sp)
270 		LONG_L	$17, PT_R17(sp)
271 		LONG_L	$18, PT_R18(sp)
272 		LONG_L	$19, PT_R19(sp)
273 		LONG_L	$20, PT_R20(sp)
274 		LONG_L	$21, PT_R21(sp)
275 		LONG_L	$22, PT_R22(sp)
276 		LONG_L	$23, PT_R23(sp)
277 		LONG_L	$30, PT_R30(sp)
278 		.endm
279 
280 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
281 
282 		.macro	RESTORE_SOME
283 		.set	push
284 		.set	reorder
285 		.set	noat
286 		mfc0	a0, CP0_STATUS
287 		li	v1, 0xff00
288 		ori	a0, STATMASK
289 		xori	a0, STATMASK
290 		mtc0	a0, CP0_STATUS
291 		and	a0, v1
292 		LONG_L	v0, PT_STATUS(sp)
293 		nor	v1, $0, v1
294 		and	v0, v1
295 		or	v0, a0
296 		mtc0	v0, CP0_STATUS
297 		LONG_L	$31, PT_R31(sp)
298 		LONG_L	$28, PT_R28(sp)
299 		LONG_L	$25, PT_R25(sp)
300 		LONG_L	$7,  PT_R7(sp)
301 		LONG_L	$6,  PT_R6(sp)
302 		LONG_L	$5,  PT_R5(sp)
303 		LONG_L	$4,  PT_R4(sp)
304 		LONG_L	$3,  PT_R3(sp)
305 		LONG_L	$2,  PT_R2(sp)
306 		.set	pop
307 		.endm
308 
309 		.macro	RESTORE_SP_AND_RET
310 		.set	push
311 		.set	noreorder
312 		LONG_L	k0, PT_EPC(sp)
313 		LONG_L	sp, PT_R29(sp)
314 		jr	k0
315 		 rfe
316 		.set	pop
317 		.endm
318 
319 #else
320 		.macro	RESTORE_SOME
321 		.set	push
322 		.set	reorder
323 		.set	noat
324 #ifdef CONFIG_MIPS_MT_SMTC
325 		.set	mips32r2
326 		/*
327 		 * We need to make sure the read-modify-write
328 		 * of Status below isn't perturbed by an interrupt
329 		 * or cross-TC access, so we need to do at least a DMT,
330 		 * protected by an interrupt-inhibit. But setting IXMT
331 		 * also creates a few-cycle window where an IPI could
332 		 * be queued and not be detected before potentially
333 		 * returning to a WAIT or user-mode loop. It must be
334 		 * replayed.
335 		 *
336 		 * We're in the middle of a context switch, and
337 		 * we can't dispatch it directly without trashing
338 		 * some registers, so we'll try to detect this unlikely
339 		 * case and program a software interrupt in the VPE,
340 		 * as would be done for a cross-VPE IPI.  To accommodate
341 		 * the handling of that case, we're doing a DVPE instead
342 		 * of just a DMT here to protect against other threads.
343 		 * This is a lot of cruft to cover a tiny window.
344 		 * If you can find a better design, implement it!
345 		 *
346 		 */
347 		mfc0	v0, CP0_TCSTATUS
348 		ori	v0, TCSTATUS_IXMT
349 		mtc0	v0, CP0_TCSTATUS
350 		_ehb
351 		DVPE	5				# dvpe a1
352 		jal	mips_ihb
353 #endif /* CONFIG_MIPS_MT_SMTC */
354 		mfc0	a0, CP0_STATUS
355 		ori	a0, STATMASK
356 		xori	a0, STATMASK
357 		mtc0	a0, CP0_STATUS
358 		li	v1, 0xff00
359 		and	a0, v1
360 		LONG_L	v0, PT_STATUS(sp)
361 		nor	v1, $0, v1
362 		and	v0, v1
363 		or	v0, a0
364 		mtc0	v0, CP0_STATUS
365 #ifdef CONFIG_MIPS_MT_SMTC
366 /*
367  * Only after EXL/ERL have been restored to status can we
368  * restore TCStatus.IXMT.
369  */
370 		LONG_L	v1, PT_TCSTATUS(sp)
371 		_ehb
372 		mfc0	a0, CP0_TCSTATUS
373 		andi	v1, TCSTATUS_IXMT
374 		bnez	v1, 0f
375 
376 /*
377  * We'd like to detect any IPIs queued in the tiny window
378  * above and request an software interrupt to service them
379  * when we ERET.
380  *
381  * Computing the offset into the IPIQ array of the executing
382  * TC's IPI queue in-line would be tedious.  We use part of
383  * the TCContext register to hold 16 bits of offset that we
384  * can add in-line to find the queue head.
385  */
386 		mfc0	v0, CP0_TCCONTEXT
387 		la	a2, IPIQ
388 		srl	v0, v0, 16
389 		addu	a2, a2, v0
390 		LONG_L	v0, 0(a2)
391 		beqz	v0, 0f
392 /*
393  * If we have a queue, provoke dispatch within the VPE by setting C_SW1
394  */
395 		mfc0	v0, CP0_CAUSE
396 		ori	v0, v0, C_SW1
397 		mtc0	v0, CP0_CAUSE
398 0:
399 		/*
400 		 * This test should really never branch but
401 		 * let's be prudent here.  Having atomized
402 		 * the shared register modifications, we can
403 		 * now EVPE, and must do so before interrupts
404 		 * are potentially re-enabled.
405 		 */
406 		andi	a1, a1, MVPCONTROL_EVP
407 		beqz	a1, 1f
408 		evpe
409 1:
410 		/* We know that TCStatua.IXMT should be set from above */
411 		xori	a0, a0, TCSTATUS_IXMT
412 		or	a0, a0, v1
413 		mtc0	a0, CP0_TCSTATUS
414 		_ehb
415 
416 		.set	mips0
417 #endif /* CONFIG_MIPS_MT_SMTC */
418 		LONG_L	v1, PT_EPC(sp)
419 		MTC0	v1, CP0_EPC
420 		LONG_L	$31, PT_R31(sp)
421 		LONG_L	$28, PT_R28(sp)
422 		LONG_L	$25, PT_R25(sp)
423 #ifdef CONFIG_64BIT
424 		LONG_L	$8, PT_R8(sp)
425 		LONG_L	$9, PT_R9(sp)
426 #endif
427 		LONG_L	$7,  PT_R7(sp)
428 		LONG_L	$6,  PT_R6(sp)
429 		LONG_L	$5,  PT_R5(sp)
430 		LONG_L	$4,  PT_R4(sp)
431 		LONG_L	$3,  PT_R3(sp)
432 		LONG_L	$2,  PT_R2(sp)
433 		.set	pop
434 		.endm
435 
436 		.macro	RESTORE_SP_AND_RET
437 		LONG_L	sp, PT_R29(sp)
438 		.set	mips3
439 		eret
440 		.set	mips0
441 		.endm
442 
443 #endif
444 
445 		.macro	RESTORE_SP
446 		LONG_L	sp, PT_R29(sp)
447 		.endm
448 
449 		.macro	RESTORE_ALL
450 		RESTORE_TEMP
451 		RESTORE_STATIC
452 		RESTORE_AT
453 		RESTORE_SOME
454 		RESTORE_SP
455 		.endm
456 
457 		.macro	RESTORE_ALL_AND_RET
458 		RESTORE_TEMP
459 		RESTORE_STATIC
460 		RESTORE_AT
461 		RESTORE_SOME
462 		RESTORE_SP_AND_RET
463 		.endm
464 
465 /*
466  * Move to kernel mode and disable interrupts.
467  * Set cp0 enable bit as sign that we're running on the kernel stack
468  */
469 		.macro	CLI
470 #if !defined(CONFIG_MIPS_MT_SMTC)
471 		mfc0	t0, CP0_STATUS
472 		li	t1, ST0_CU0 | STATMASK
473 		or	t0, t1
474 		xori	t0, STATMASK
475 		mtc0	t0, CP0_STATUS
476 #else /* CONFIG_MIPS_MT_SMTC */
477 		/*
478 		 * For SMTC, we need to set privilege
479 		 * and disable interrupts only for the
480 		 * current TC, using the TCStatus register.
481 		 */
482 		mfc0	t0, CP0_TCSTATUS
483 		/* Fortunately CU 0 is in the same place in both registers */
484 		/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
485 		li	t1, ST0_CU0 | 0x08001c00
486 		or	t0, t1
487 		/* Clear TKSU, leave IXMT */
488 		xori	t0, 0x00001800
489 		mtc0	t0, CP0_TCSTATUS
490 		_ehb
491 		/* We need to leave the global IE bit set, but clear EXL...*/
492 		mfc0	t0, CP0_STATUS
493 		ori	t0, ST0_EXL | ST0_ERL
494 		xori	t0, ST0_EXL | ST0_ERL
495 		mtc0	t0, CP0_STATUS
496 #endif /* CONFIG_MIPS_MT_SMTC */
497 		irq_disable_hazard
498 		.endm
499 
500 /*
501  * Move to kernel mode and enable interrupts.
502  * Set cp0 enable bit as sign that we're running on the kernel stack
503  */
504 		.macro	STI
505 #if !defined(CONFIG_MIPS_MT_SMTC)
506 		mfc0	t0, CP0_STATUS
507 		li	t1, ST0_CU0 | STATMASK
508 		or	t0, t1
509 		xori	t0, STATMASK & ~1
510 		mtc0	t0, CP0_STATUS
511 #else /* CONFIG_MIPS_MT_SMTC */
512 		/*
513 		 * For SMTC, we need to set privilege
514 		 * and enable interrupts only for the
515 		 * current TC, using the TCStatus register.
516 		 */
517 		_ehb
518 		mfc0	t0, CP0_TCSTATUS
519 		/* Fortunately CU 0 is in the same place in both registers */
520 		/* Set TCU0, TKSU (for later inversion) and IXMT */
521 		li	t1, ST0_CU0 | 0x08001c00
522 		or	t0, t1
523 		/* Clear TKSU *and* IXMT */
524 		xori	t0, 0x00001c00
525 		mtc0	t0, CP0_TCSTATUS
526 		_ehb
527 		/* We need to leave the global IE bit set, but clear EXL...*/
528 		mfc0	t0, CP0_STATUS
529 		ori	t0, ST0_EXL
530 		xori	t0, ST0_EXL
531 		mtc0	t0, CP0_STATUS
532 		/* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
533 #endif /* CONFIG_MIPS_MT_SMTC */
534 		irq_enable_hazard
535 		.endm
536 
537 /*
538  * Just move to kernel mode and leave interrupts as they are.  Note
539  * for the R3000 this means copying the previous enable from IEp.
540  * Set cp0 enable bit as sign that we're running on the kernel stack
541  */
542 		.macro	KMODE
543 #ifdef CONFIG_MIPS_MT_SMTC
544 		/*
545 		 * This gets baroque in SMTC.  We want to
546 		 * protect the non-atomic clearing of EXL
547 		 * with DMT/EMT, but we don't want to take
548 		 * an interrupt while DMT is still in effect.
549 		 */
550 
551 		/* KMODE gets invoked from both reorder and noreorder code */
552 		.set	push
553 		.set	mips32r2
554 		.set	noreorder
555 		mfc0	v0, CP0_TCSTATUS
556 		andi	v1, v0, TCSTATUS_IXMT
557 		ori	v0, TCSTATUS_IXMT
558 		mtc0	v0, CP0_TCSTATUS
559 		_ehb
560 		DMT	2				# dmt	v0
561 		/*
562 		 * We don't know a priori if ra is "live"
563 		 */
564 		move	t0, ra
565 		jal	mips_ihb
566 		nop	/* delay slot */
567 		move	ra, t0
568 #endif /* CONFIG_MIPS_MT_SMTC */
569 		mfc0	t0, CP0_STATUS
570 		li	t1, ST0_CU0 | (STATMASK & ~1)
571 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
572 		andi	t2, t0, ST0_IEP
573 		srl	t2, 2
574 		or	t0, t2
575 #endif
576 		or	t0, t1
577 		xori	t0, STATMASK & ~1
578 		mtc0	t0, CP0_STATUS
579 #ifdef CONFIG_MIPS_MT_SMTC
580 		_ehb
581 		andi	v0, v0, VPECONTROL_TE
582 		beqz	v0, 2f
583 		nop	/* delay slot */
584 		emt
585 2:
586 		mfc0	v0, CP0_TCSTATUS
587 		/* Clear IXMT, then OR in previous value */
588 		ori	v0, TCSTATUS_IXMT
589 		xori	v0, TCSTATUS_IXMT
590 		or	v0, v1, v0
591 		mtc0	v0, CP0_TCSTATUS
592 		/*
593 		 * irq_disable_hazard below should expand to EHB
594 		 * on 24K/34K CPUS
595 		 */
596 		.set pop
597 #endif /* CONFIG_MIPS_MT_SMTC */
598 		irq_disable_hazard
599 		.endm
600 
601 #endif /* _ASM_STACKFRAME_H */
602