1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 3384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 4384740dcSRalf Baechle * for more details. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27. 7384740dcSRalf Baechle * 8384740dcSRalf Baechle * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc. 9384740dcSRalf Baechle * Copyright (C) 1999 by Ralf Baechle 10384740dcSRalf Baechle */ 11384740dcSRalf Baechle #ifndef _ASM_SGI_SN0_HUBNI_H 12384740dcSRalf Baechle #define _ASM_SGI_SN0_HUBNI_H 13384740dcSRalf Baechle 14384740dcSRalf Baechle #ifndef __ASSEMBLY__ 15384740dcSRalf Baechle #include <linux/types.h> 16384740dcSRalf Baechle #endif 17384740dcSRalf Baechle 18384740dcSRalf Baechle /* 19384740dcSRalf Baechle * Hub Network Interface registers 20384740dcSRalf Baechle * 21384740dcSRalf Baechle * All registers in this file are subject to change until Hub chip tapeout. 22384740dcSRalf Baechle */ 23384740dcSRalf Baechle 24384740dcSRalf Baechle #define NI_BASE 0x600000 25384740dcSRalf Baechle #define NI_BASE_TABLES 0x630000 26384740dcSRalf Baechle 27384740dcSRalf Baechle #define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */ 28384740dcSRalf Baechle #define NI_PORT_RESET 0x600008 /* Reset the network interface */ 29384740dcSRalf Baechle #define NI_PROTECTION 0x600010 /* NI register access permissions */ 30384740dcSRalf Baechle #define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */ 31384740dcSRalf Baechle #define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */ 32384740dcSRalf Baechle #define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */ 33384740dcSRalf Baechle #define NI_DIAG_PARMS 0x600110 /* Parameters for diags */ 34384740dcSRalf Baechle 35384740dcSRalf Baechle #define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */ 36384740dcSRalf Baechle #define NI_VECTOR 0x600208 /* Vector PIO route */ 37384740dcSRalf Baechle #define NI_VECTOR_DATA 0x600210 /* Vector PIO data */ 38384740dcSRalf Baechle #define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */ 39384740dcSRalf Baechle #define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */ 40384740dcSRalf Baechle #define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */ 41384740dcSRalf Baechle #define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */ 42384740dcSRalf Baechle 43384740dcSRalf Baechle #define NI_IO_PROTECT 0x600400 /* PIO protection bits */ 44384740dcSRalf Baechle #define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */ 45384740dcSRalf Baechle 46384740dcSRalf Baechle #define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */ 47384740dcSRalf Baechle #define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */ 48384740dcSRalf Baechle #define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */ 49384740dcSRalf Baechle #define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */ 50384740dcSRalf Baechle #define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */ 51384740dcSRalf Baechle #define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */ 52384740dcSRalf Baechle #define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */ 53384740dcSRalf Baechle #define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */ 54384740dcSRalf Baechle #define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY 55384740dcSRalf Baechle #define NI_AGE_REG_MAX NI_AGE_IO_PIO 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define NI_PORT_PARMS 0x608000 /* LLP Parameters */ 58384740dcSRalf Baechle #define NI_PORT_ERROR 0x608008 /* LLP Errors */ 59384740dcSRalf Baechle #define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */ 60384740dcSRalf Baechle 61384740dcSRalf Baechle #define NI_META_TABLE0 0x638000 /* First meta routing table entry */ 62384740dcSRalf Baechle #define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x))) 63384740dcSRalf Baechle #define NI_META_ENTRIES 32 64384740dcSRalf Baechle 65384740dcSRalf Baechle #define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */ 66384740dcSRalf Baechle #define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x))) 67384740dcSRalf Baechle #define NI_LOCAL_ENTRIES 16 68384740dcSRalf Baechle 69384740dcSRalf Baechle /* 70384740dcSRalf Baechle * NI_STATUS_REV_ID mask and shift definitions 71384740dcSRalf Baechle * Have to use UINT64_CAST instead of 'L' suffix, for assembler. 72384740dcSRalf Baechle */ 73384740dcSRalf Baechle 74384740dcSRalf Baechle #define NSRI_8BITMODE_SHFT 30 75384740dcSRalf Baechle #define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30) 76384740dcSRalf Baechle #define NSRI_LINKUP_SHFT 29 77384740dcSRalf Baechle #define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29) 78384740dcSRalf Baechle #define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */ 79384740dcSRalf Baechle #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */ 80384740dcSRalf Baechle #define NSRI_MORENODES_SHFT 18 81384740dcSRalf Baechle #define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */ 82384740dcSRalf Baechle #define MORE_MEMORY 0 83384740dcSRalf Baechle #define MORE_NODES 1 84384740dcSRalf Baechle #define NSRI_REGIONSIZE_SHFT 17 85384740dcSRalf Baechle #define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */ 86384740dcSRalf Baechle #define REGIONSIZE_FINE 1 87384740dcSRalf Baechle #define REGIONSIZE_COARSE 0 88384740dcSRalf Baechle #define NSRI_NODEID_SHFT 8 89384740dcSRalf Baechle #define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */ 90384740dcSRalf Baechle #define NSRI_REV_SHFT 4 91384740dcSRalf Baechle #define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */ 92384740dcSRalf Baechle #define NSRI_CHIPID_SHFT 0 93384740dcSRalf Baechle #define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */ 94384740dcSRalf Baechle 95384740dcSRalf Baechle /* 96384740dcSRalf Baechle * In fine mode, each node is a region. In coarse mode, there are 97384740dcSRalf Baechle * eight nodes per region. 98384740dcSRalf Baechle */ 99384740dcSRalf Baechle #define NASID_TO_FINEREG_SHFT 0 100384740dcSRalf Baechle #define NASID_TO_COARSEREG_SHFT 3 101384740dcSRalf Baechle 102384740dcSRalf Baechle /* NI_PORT_RESET mask definitions */ 103384740dcSRalf Baechle 104384740dcSRalf Baechle #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */ 105384740dcSRalf Baechle #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */ 106384740dcSRalf Baechle #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */ 107384740dcSRalf Baechle 108384740dcSRalf Baechle /* NI_PROTECTION mask and shift definitions */ 109384740dcSRalf Baechle 110384740dcSRalf Baechle #define NPROT_RESETOK (UINT64_CAST 1) 111384740dcSRalf Baechle 112384740dcSRalf Baechle /* NI_GLOBAL_PARMS mask and shift definitions */ 113384740dcSRalf Baechle 114384740dcSRalf Baechle #define NGP_MAXRETRY_SHFT 48 /* Maximum retries */ 115384740dcSRalf Baechle #define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48) 116384740dcSRalf Baechle #define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */ 117384740dcSRalf Baechle #define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32) 118384740dcSRalf Baechle 119384740dcSRalf Baechle #define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */ 120384740dcSRalf Baechle #define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16) 121384740dcSRalf Baechle #define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */ 122384740dcSRalf Baechle #define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4) 123384740dcSRalf Baechle 124384740dcSRalf Baechle /* NI_DIAG_PARMS mask and shift definitions */ 125384740dcSRalf Baechle 126384740dcSRalf Baechle #define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */ 127384740dcSRalf Baechle #define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */ 128384740dcSRalf Baechle #define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */ 129384740dcSRalf Baechle #define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */ 130384740dcSRalf Baechle 131384740dcSRalf Baechle /* 132384740dcSRalf Baechle * NI_VECTOR_PARMS mask and shift definitions. 133384740dcSRalf Baechle * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS. 134384740dcSRalf Baechle */ 135384740dcSRalf Baechle 136384740dcSRalf Baechle #define NVP_PIOID_SHFT 40 137384740dcSRalf Baechle #define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40) 138384740dcSRalf Baechle #define NVP_WRITEID_SHFT 32 139384740dcSRalf Baechle #define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32) 140384740dcSRalf Baechle #define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */ 141384740dcSRalf Baechle #define NVP_TYPE_SHFT 0 142384740dcSRalf Baechle #define NVP_TYPE_MASK (UINT64_CAST 0x3) 143384740dcSRalf Baechle 144384740dcSRalf Baechle /* NI_VECTOR_STATUS mask and shift definitions */ 145384740dcSRalf Baechle 146384740dcSRalf Baechle #define NVS_VALID (UINT64_CAST 1 << 63) 147384740dcSRalf Baechle #define NVS_OVERRUN (UINT64_CAST 1 << 62) 148384740dcSRalf Baechle #define NVS_TARGET_SHFT 51 149384740dcSRalf Baechle #define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51) 150384740dcSRalf Baechle #define NVS_PIOID_SHFT 40 151384740dcSRalf Baechle #define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40) 152384740dcSRalf Baechle #define NVS_WRITEID_SHFT 32 153384740dcSRalf Baechle #define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32) 154384740dcSRalf Baechle #define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */ 155384740dcSRalf Baechle #define NVS_TYPE_SHFT 0 156384740dcSRalf Baechle #define NVS_TYPE_MASK (UINT64_CAST 0x7) 157384740dcSRalf Baechle #define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */ 158384740dcSRalf Baechle 159384740dcSRalf Baechle 160384740dcSRalf Baechle #define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */ 161384740dcSRalf Baechle #define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */ 162384740dcSRalf Baechle #define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */ 163384740dcSRalf Baechle #define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */ 164384740dcSRalf Baechle #define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ 165384740dcSRalf Baechle #define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ 166384740dcSRalf Baechle #define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ 167384740dcSRalf Baechle #define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ 168384740dcSRalf Baechle 169384740dcSRalf Baechle /* NI_AGE_XXX mask and shift definitions */ 170384740dcSRalf Baechle 171384740dcSRalf Baechle #define NAGE_VCH_SHFT 10 172384740dcSRalf Baechle #define NAGE_VCH_MASK (UINT64_CAST 3 << 10) 173384740dcSRalf Baechle #define NAGE_CC_SHFT 8 174384740dcSRalf Baechle #define NAGE_CC_MASK (UINT64_CAST 3 << 8) 175384740dcSRalf Baechle #define NAGE_AGE_SHFT 0 176384740dcSRalf Baechle #define NAGE_AGE_MASK (UINT64_CAST 0xff) 177384740dcSRalf Baechle #define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK) 178384740dcSRalf Baechle 179384740dcSRalf Baechle #define VCHANNEL_A 0 180384740dcSRalf Baechle #define VCHANNEL_B 1 181384740dcSRalf Baechle #define VCHANNEL_ANY 2 182384740dcSRalf Baechle 183384740dcSRalf Baechle /* NI_PORT_PARMS mask and shift definitions */ 184384740dcSRalf Baechle 185384740dcSRalf Baechle #define NPP_NULLTO_SHFT 10 186384740dcSRalf Baechle #define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16) 187384740dcSRalf Baechle #define NPP_MAXBURST_SHFT 0 188384740dcSRalf Baechle #define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff) 189384740dcSRalf Baechle #define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \ 190384740dcSRalf Baechle (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT)) 191384740dcSRalf Baechle #define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \ 192384740dcSRalf Baechle (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT)) 193384740dcSRalf Baechle 194384740dcSRalf Baechle 195384740dcSRalf Baechle /* NI_PORT_ERROR mask and shift definitions */ 196384740dcSRalf Baechle 197384740dcSRalf Baechle #define NPE_LINKRESET (UINT64_CAST 1 << 37) 198384740dcSRalf Baechle #define NPE_INTERNALERROR (UINT64_CAST 1 << 36) 199384740dcSRalf Baechle #define NPE_BADMESSAGE (UINT64_CAST 1 << 35) 200384740dcSRalf Baechle #define NPE_BADDEST (UINT64_CAST 1 << 34) 201384740dcSRalf Baechle #define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33) 202384740dcSRalf Baechle #define NPE_CREDITTO_SHFT 28 203384740dcSRalf Baechle #define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28) 204384740dcSRalf Baechle #define NPE_TAILTO_SHFT 24 205384740dcSRalf Baechle #define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24) 206384740dcSRalf Baechle #define NPE_RETRYCOUNT_SHFT 16 207384740dcSRalf Baechle #define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16) 208384740dcSRalf Baechle #define NPE_CBERRCOUNT_SHFT 8 209384740dcSRalf Baechle #define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8) 210384740dcSRalf Baechle #define NPE_SNERRCOUNT_SHFT 0 211384740dcSRalf Baechle #define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0) 212384740dcSRalf Baechle #define NPE_MASK 0x3effffffff 213384740dcSRalf Baechle 214384740dcSRalf Baechle #define NPE_COUNT_MAX 0xff 215384740dcSRalf Baechle 216384740dcSRalf Baechle #define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \ 217384740dcSRalf Baechle NPE_BADMESSAGE | NPE_BADDEST | \ 218384740dcSRalf Baechle NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \ 219384740dcSRalf Baechle NPE_TAILTO_MASK) 220384740dcSRalf Baechle 221384740dcSRalf Baechle /* NI_META_TABLE mask and shift definitions */ 222384740dcSRalf Baechle 223384740dcSRalf Baechle #define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf) 224384740dcSRalf Baechle 225384740dcSRalf Baechle /* NI_LOCAL_TABLE mask and shift definitions */ 226384740dcSRalf Baechle 227384740dcSRalf Baechle #define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf) 228384740dcSRalf Baechle 229384740dcSRalf Baechle #ifndef __ASSEMBLY__ 230384740dcSRalf Baechle 231384740dcSRalf Baechle typedef union hubni_port_error_u { 232384740dcSRalf Baechle u64 nipe_reg_value; 233384740dcSRalf Baechle struct { 234384740dcSRalf Baechle u64 nipe_rsvd: 26, /* unused */ 235384740dcSRalf Baechle nipe_lnk_reset: 1, /* link reset */ 236384740dcSRalf Baechle nipe_intl_err: 1, /* internal error */ 237384740dcSRalf Baechle nipe_bad_msg: 1, /* bad message */ 238384740dcSRalf Baechle nipe_bad_dest: 1, /* bad dest */ 239384740dcSRalf Baechle nipe_fifo_ovfl: 1, /* fifo overflow */ 240384740dcSRalf Baechle nipe_rsvd1: 1, /* unused */ 241384740dcSRalf Baechle nipe_credit_to: 4, /* credit timeout */ 242384740dcSRalf Baechle nipe_tail_to: 4, /* tail timeout */ 243384740dcSRalf Baechle nipe_retry_cnt: 8, /* retry error count */ 244384740dcSRalf Baechle nipe_cb_cnt: 8, /* checkbit error count */ 245384740dcSRalf Baechle nipe_sn_cnt: 8; /* sequence number count */ 246384740dcSRalf Baechle } nipe_fields_s; 247384740dcSRalf Baechle } hubni_port_error_t; 248384740dcSRalf Baechle 249384740dcSRalf Baechle #define NI_LLP_RETRY_MAX 0xff 250384740dcSRalf Baechle #define NI_LLP_CB_MAX 0xff 251384740dcSRalf Baechle #define NI_LLP_SN_MAX 0xff 252384740dcSRalf Baechle 253384740dcSRalf Baechle #endif /* !__ASSEMBLY__ */ 254384740dcSRalf Baechle 255384740dcSRalf Baechle #endif /* _ASM_SGI_SN0_HUBNI_H */ 256