1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 1999, 2000 Ralf Baechle 4 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 5 */ 6 #ifndef MIPS_SN_IOC3_H 7 #define MIPS_SN_IOC3_H 8 9 #include <linux/types.h> 10 11 /* serial port register map */ 12 struct ioc3_serialregs { 13 u32 sscr; 14 u32 stpir; 15 u32 stcir; 16 u32 srpir; 17 u32 srcir; 18 u32 srtr; 19 u32 shadow; 20 }; 21 22 /* SUPERIO uart register map */ 23 struct ioc3_uartregs { 24 union { 25 u8 iu_rbr; /* read only, DLAB == 0 */ 26 u8 iu_thr; /* write only, DLAB == 0 */ 27 u8 iu_dll; /* DLAB == 1 */ 28 }; 29 union { 30 u8 iu_ier; /* DLAB == 0 */ 31 u8 iu_dlm; /* DLAB == 1 */ 32 }; 33 union { 34 u8 iu_iir; /* read only */ 35 u8 iu_fcr; /* write only */ 36 }; 37 u8 iu_lcr; 38 u8 iu_mcr; 39 u8 iu_lsr; 40 u8 iu_msr; 41 u8 iu_scr; 42 }; 43 44 struct ioc3_sioregs { 45 u8 fill[0x141]; /* starts at 0x141 */ 46 47 u8 uartc; 48 u8 kbdcg; 49 50 u8 fill0[0x150 - 0x142 - 1]; 51 52 u8 pp_data; 53 u8 pp_dsr; 54 u8 pp_dcr; 55 56 u8 fill1[0x158 - 0x152 - 1]; 57 58 u8 pp_fifa; 59 u8 pp_cfgb; 60 u8 pp_ecr; 61 62 u8 fill2[0x168 - 0x15a - 1]; 63 64 u8 rtcad; 65 u8 rtcdat; 66 67 u8 fill3[0x170 - 0x169 - 1]; 68 69 struct ioc3_uartregs uartb; /* 0x20170 */ 70 struct ioc3_uartregs uarta; /* 0x20178 */ 71 }; 72 73 struct ioc3_ethregs { 74 u32 emcr; /* 0x000f0 */ 75 u32 eisr; /* 0x000f4 */ 76 u32 eier; /* 0x000f8 */ 77 u32 ercsr; /* 0x000fc */ 78 u32 erbr_h; /* 0x00100 */ 79 u32 erbr_l; /* 0x00104 */ 80 u32 erbar; /* 0x00108 */ 81 u32 ercir; /* 0x0010c */ 82 u32 erpir; /* 0x00110 */ 83 u32 ertr; /* 0x00114 */ 84 u32 etcsr; /* 0x00118 */ 85 u32 ersr; /* 0x0011c */ 86 u32 etcdc; /* 0x00120 */ 87 u32 ebir; /* 0x00124 */ 88 u32 etbr_h; /* 0x00128 */ 89 u32 etbr_l; /* 0x0012c */ 90 u32 etcir; /* 0x00130 */ 91 u32 etpir; /* 0x00134 */ 92 u32 emar_h; /* 0x00138 */ 93 u32 emar_l; /* 0x0013c */ 94 u32 ehar_h; /* 0x00140 */ 95 u32 ehar_l; /* 0x00144 */ 96 u32 micr; /* 0x00148 */ 97 u32 midr_r; /* 0x0014c */ 98 u32 midr_w; /* 0x00150 */ 99 }; 100 101 struct ioc3_serioregs { 102 u32 km_csr; /* 0x0009c */ 103 u32 k_rd; /* 0x000a0 */ 104 u32 m_rd; /* 0x000a4 */ 105 u32 k_wd; /* 0x000a8 */ 106 u32 m_wd; /* 0x000ac */ 107 }; 108 109 /* Register layout of IOC3 in configuration space. */ 110 struct ioc3 { 111 /* PCI Config Space registers */ 112 u32 pci_id; /* 0x00000 */ 113 u32 pci_scr; /* 0x00004 */ 114 u32 pci_rev; /* 0x00008 */ 115 u32 pci_lat; /* 0x0000c */ 116 u32 pci_addr; /* 0x00010 */ 117 u32 pci_err_addr_l; /* 0x00014 */ 118 u32 pci_err_addr_h; /* 0x00018 */ 119 120 u32 sio_ir; /* 0x0001c */ 121 u32 sio_ies; /* 0x00020 */ 122 u32 sio_iec; /* 0x00024 */ 123 u32 sio_cr; /* 0x00028 */ 124 u32 int_out; /* 0x0002c */ 125 u32 mcr; /* 0x00030 */ 126 127 /* General Purpose I/O registers */ 128 u32 gpcr_s; /* 0x00034 */ 129 u32 gpcr_c; /* 0x00038 */ 130 u32 gpdr; /* 0x0003c */ 131 u32 gppr[16]; /* 0x00040 */ 132 133 /* Parallel Port Registers */ 134 u32 ppbr_h_a; /* 0x00080 */ 135 u32 ppbr_l_a; /* 0x00084 */ 136 u32 ppcr_a; /* 0x00088 */ 137 u32 ppcr; /* 0x0008c */ 138 u32 ppbr_h_b; /* 0x00090 */ 139 u32 ppbr_l_b; /* 0x00094 */ 140 u32 ppcr_b; /* 0x00098 */ 141 142 /* Keyboard and Mouse Registers */ 143 struct ioc3_serioregs serio; 144 145 /* Serial Port Registers */ 146 u32 sbbr_h; /* 0x000b0 */ 147 u32 sbbr_l; /* 0x000b4 */ 148 struct ioc3_serialregs port_a; 149 struct ioc3_serialregs port_b; 150 151 /* Ethernet Registers */ 152 struct ioc3_ethregs eth; 153 u32 pad1[(0x20000 - 0x00154) / 4]; 154 155 /* SuperIO Registers XXX */ 156 struct ioc3_sioregs sregs; /* 0x20000 */ 157 u32 pad2[(0x40000 - 0x20180) / 4]; 158 159 /* SSRAM Diagnostic Access */ 160 u32 ssram[(0x80000 - 0x40000) / 4]; 161 162 /* Bytebus device offsets 163 0x80000 - Access to the generic devices selected with DEV0 164 0x9FFFF bytebus DEV_SEL_0 165 0xA0000 - Access to the generic devices selected with DEV1 166 0xBFFFF bytebus DEV_SEL_1 167 0xC0000 - Access to the generic devices selected with DEV2 168 0xDFFFF bytebus DEV_SEL_2 169 0xE0000 - Access to the generic devices selected with DEV3 170 0xFFFFF bytebus DEV_SEL_3 */ 171 }; 172 173 174 #define PCI_LAT 0xc /* Latency Timer */ 175 #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ 176 #define UARTA_BASE 0x178 177 #define UARTB_BASE 0x170 178 179 /* 180 * Bytebus device space 181 */ 182 #define IOC3_BYTEBUS_DEV0 0x80000L 183 #define IOC3_BYTEBUS_DEV1 0xa0000L 184 #define IOC3_BYTEBUS_DEV2 0xc0000L 185 #define IOC3_BYTEBUS_DEV3 0xe0000L 186 187 /* 188 * Ethernet RX Buffer 189 */ 190 struct ioc3_erxbuf { 191 u32 w0; /* first word (valid,bcnt,cksum) */ 192 u32 err; /* second word various errors */ 193 /* next comes n bytes of padding */ 194 /* then the received ethernet frame itself */ 195 }; 196 197 #define ERXBUF_IPCKSUM_MASK 0x0000ffff 198 #define ERXBUF_BYTECNT_MASK 0x07ff0000 199 #define ERXBUF_BYTECNT_SHIFT 16 200 #define ERXBUF_V 0x80000000 201 202 #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ 203 #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ 204 #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ 205 #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ 206 #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ 207 #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ 208 #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ 209 #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ 210 #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ 211 #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ 212 #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ 213 #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ 214 215 /* 216 * Ethernet TX Descriptor 217 */ 218 #define ETXD_DATALEN 104 219 struct ioc3_etxd { 220 u32 cmd; /* command field */ 221 u32 bufcnt; /* buffer counts field */ 222 u64 p1; /* buffer pointer 1 */ 223 u64 p2; /* buffer pointer 2 */ 224 u8 data[ETXD_DATALEN]; /* opt. tx data */ 225 }; 226 227 #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ 228 #define ETXD_INTWHENDONE 0x00001000 /* intr when done */ 229 #define ETXD_D0V 0x00010000 /* data 0 valid */ 230 #define ETXD_B1V 0x00020000 /* buf 1 valid */ 231 #define ETXD_B2V 0x00040000 /* buf 2 valid */ 232 #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ 233 #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ 234 #define ETXD_CHKOFF_SHIFT 20 235 236 #define ETXD_D0CNT_MASK 0x0000007f 237 #define ETXD_B1CNT_MASK 0x0007ff00 238 #define ETXD_B1CNT_SHIFT 8 239 #define ETXD_B2CNT_MASK 0x7ff00000 240 #define ETXD_B2CNT_SHIFT 20 241 242 /* ------------------------------------------------------------------------- */ 243 244 /* Superio Registers (PIO Access) */ 245 #define IOC3_SIO_BASE 0x20000 246 #define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ 247 #define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ 248 #define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ 249 #define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ 250 #define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ 251 #define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ 252 253 /* SSRAM Diagnostic Access */ 254 #define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ 255 #define IOC3_SSRAM_LEN 0x40000 /* 256kb (addrspc sz, may not be populated) */ 256 #define IOC3_SSRAM_DM 0x0000ffff /* data mask */ 257 #define IOC3_SSRAM_PM 0x00010000 /* parity mask */ 258 259 /* bitmasks for PCI_SCR */ 260 #define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ 261 #define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ 262 #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ 263 #define PCI_SCR_RX_SERR (0x1 << 16) 264 #define PCI_SCR_DROP_MODE (0x1 << 17) 265 #define PCI_SCR_SIG_PAR_ERR (0x1 << 24) 266 #define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) 267 #define PCI_SCR_RX_TAR_ABRT (0x1 << 28) 268 #define PCI_SCR_SIG_MST_ABRT (0x1 << 29) 269 #define PCI_SCR_SIG_SERR (0x1 << 30) 270 #define PCI_SCR_PAR_ERR (0x1 << 31) 271 272 /* bitmasks for IOC3_KM_CSR */ 273 #define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ 274 #define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ 275 #define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ 276 #define KM_CSR_M_LCB 0x00000008 /* same for mouse */ 277 #define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ 278 #define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ 279 #define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ 280 #define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ 281 #define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ 282 #define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ 283 #define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ 284 #define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ 285 #define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ 286 #define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ 287 #define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ 288 #define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ 289 #define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ 290 #define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ 291 #define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause 292 SIO_IR to assert */ 293 #define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause 294 SIO_IR to assert */ 295 #define KM_CSR_K_CLAMP_1 0x00100000 /* Pull K_CLK low aft recv 1 char */ 296 #define KM_CSR_M_CLAMP_1 0x00200000 /* Pull M_CLK low aft recv 1 char */ 297 #define KM_CSR_K_CLAMP_3 0x00400000 /* Pull K_CLK low aft recv 3 chars */ 298 #define KM_CSR_M_CLAMP_3 0x00800000 /* Pull M_CLK low aft recv 3 chars */ 299 300 /* bitmasks for IOC3_K_RD and IOC3_M_RD */ 301 #define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ 302 #define KM_RD_DATA_2_SHIFT 0 303 #define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ 304 #define KM_RD_DATA_1_SHIFT 8 305 #define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ 306 #define KM_RD_DATA_0_SHIFT 16 307 #define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ 308 #define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ 309 #define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ 310 311 #define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ 312 #define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ 313 #define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ 314 #define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ 315 #define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ 316 #define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) 317 318 /* bitmasks for IOC3_K_WD & IOC3_M_WD */ 319 #define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ 320 #define KM_WD_WRT_DATA_SHIFT 0 321 322 /* bitmasks for serial RX status byte */ 323 #define RXSB_OVERRUN 0x01 /* char(s) lost */ 324 #define RXSB_PAR_ERR 0x02 /* parity error */ 325 #define RXSB_FRAME_ERR 0x04 /* framing error */ 326 #define RXSB_BREAK 0x08 /* break character */ 327 #define RXSB_CTS 0x10 /* state of CTS */ 328 #define RXSB_DCD 0x20 /* state of DCD */ 329 #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ 330 #define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ 331 332 /* bitmasks for serial TX control byte */ 333 #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ 334 #define TXCB_INVALID 0x00 /* byte is invalid */ 335 #define TXCB_VALID 0x40 /* byte is valid */ 336 #define TXCB_MCR 0x80 /* data<7:0> to modem control register */ 337 #define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ 338 339 /* bitmasks for IOC3_SBBR_L */ 340 #define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ 341 #define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ 342 343 /* bitmasks for IOC3_SSCR_<A:B> */ 344 #define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ 345 #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ 346 #define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ 347 #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ 348 #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ 349 #define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ 350 #define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ 351 #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ 352 #define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ 353 #define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ 354 #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ 355 #define SSCR_RESET 0x80000000 /* reset DMA channels */ 356 357 /* all producer/consumer pointers are the same bitfield */ 358 #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ 359 #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ 360 #define PROD_CONS_PTR_OFF 3 361 362 /* bitmasks for IOC3_SRCIR_<A:B> */ 363 #define SRCIR_ARM 0x80000000 /* arm RX timer */ 364 365 /* bitmasks for IOC3_SRPIR_<A:B> */ 366 #define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ 367 #define SRPIR_BYTE_CNT_SHIFT 24 368 369 /* bitmasks for IOC3_STCIR_<A:B> */ 370 #define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ 371 #define STCIR_BYTE_CNT_SHIFT 24 372 373 /* bitmasks for IOC3_SHADOW_<A:B> */ 374 #define SHADOW_DR 0x00000001 /* data ready */ 375 #define SHADOW_OE 0x00000002 /* overrun error */ 376 #define SHADOW_PE 0x00000004 /* parity error */ 377 #define SHADOW_FE 0x00000008 /* framing error */ 378 #define SHADOW_BI 0x00000010 /* break interrupt */ 379 #define SHADOW_THRE 0x00000020 /* transmit holding register empty */ 380 #define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ 381 #define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ 382 #define SHADOW_DCTS 0x00010000 /* delta clear to send */ 383 #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ 384 #define SHADOW_CTS 0x00100000 /* clear to send */ 385 #define SHADOW_DCD 0x00800000 /* data carrier detect */ 386 #define SHADOW_DTR 0x01000000 /* data terminal ready */ 387 #define SHADOW_RTS 0x02000000 /* request to send */ 388 #define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ 389 #define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ 390 #define SHADOW_LOOP 0x10000000 /* loopback enabled */ 391 392 /* bitmasks for IOC3_SRTR_<A:B> */ 393 #define SRTR_CNT 0x00000fff /* reload value for RX timer */ 394 #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ 395 #define SRTR_CNT_VAL_SHIFT 16 396 #define SRTR_HZ 16000 /* SRTR clock frequency */ 397 398 /* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ 399 #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ 400 #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ 401 #define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ 402 #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ 403 #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ 404 #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ 405 #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ 406 #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ 407 #define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ 408 #define SIO_IR_SB_TX_MT 0x00000200 /* */ 409 #define SIO_IR_SB_RX_FULL 0x00000400 /* */ 410 #define SIO_IR_SB_RX_HIGH 0x00000800 /* */ 411 #define SIO_IR_SB_RX_TIMER 0x00001000 /* */ 412 #define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ 413 #define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ 414 #define SIO_IR_SB_INT 0x00008000 /* */ 415 #define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ 416 #define SIO_IR_SB_MEMERR 0x00020000 /* */ 417 #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ 418 #define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ 419 #define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ 420 #define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ 421 #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ 422 #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ 423 #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ 424 #define SIO_IR_GEN_INT_SHIFT 28 425 426 /* per device interrupt masks */ 427 #define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ 428 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ 429 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ 430 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ 431 SIO_IR_SA_MEMERR) 432 #define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ 433 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ 434 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ 435 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ 436 SIO_IR_SB_MEMERR) 437 #define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ 438 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) 439 #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) 440 441 /* bitmasks for SIO_CR */ 442 #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ 443 #define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ 444 #define SIO_CR_SER_A_BASE_SHIFT 1 445 #define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ 446 #define SIO_CR_SER_B_BASE_SHIFT 8 447 #define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ 448 #define SIO_CR_CMD_PULSE_SHIFT 15 449 #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ 450 #define SIO_CR_ARB_DIAG_TXA 0x00000000 451 #define SIO_CR_ARB_DIAG_RXA 0x00080000 452 #define SIO_CR_ARB_DIAG_TXB 0x00100000 453 #define SIO_CR_ARB_DIAG_RXB 0x00180000 454 #define SIO_CR_ARB_DIAG_PP 0x00200000 455 #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ 456 457 /* bitmasks for INT_OUT */ 458 #define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ 459 #define INT_OUT_MODE 0x00070000 /* mode mask */ 460 #define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ 461 #define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ 462 #define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ 463 #define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ 464 #define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ 465 #define INT_OUT_DIAG 0x40000000 /* diag mode */ 466 #define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ 467 468 /* time constants for INT_OUT */ 469 #define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ 470 #define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ 471 #define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ 472 (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ 473 100 / INT_OUT_NS_PER_TICK - 1) 474 #define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ 475 (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) 476 #define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ 477 #define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ 478 479 /* bitmasks for GPCR */ 480 #define GPCR_DIR 0x000000ff /* tristate pin input or output */ 481 #define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ 482 #define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ 483 #define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ 484 485 /* values for GPCR */ 486 #define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ 487 #define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ 488 #define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ 489 #define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ 490 #define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ 491 492 /* defs for some of the generic I/O pins */ 493 #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ 494 #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ 495 #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ 496 497 #define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */ 498 #define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrlling uart b mode sel */ 499 #define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrlling uart a mode sel */ 500 501 /* ethernet */ 502 #define EMCR_DUPLEX 0x00000001 503 #define EMCR_PROMISC 0x00000002 504 #define EMCR_PADEN 0x00000004 505 #define EMCR_RXOFF_MASK 0x000001f8 506 #define EMCR_RXOFF_SHIFT 3 507 #define EMCR_RAMPAR 0x00000200 508 #define EMCR_BADPAR 0x00000800 509 #define EMCR_BUFSIZ 0x00001000 510 #define EMCR_TXDMAEN 0x00002000 511 #define EMCR_TXEN 0x00004000 512 #define EMCR_RXDMAEN 0x00008000 513 #define EMCR_RXEN 0x00010000 514 #define EMCR_LOOPBACK 0x00020000 515 #define EMCR_ARB_DIAG 0x001c0000 516 #define EMCR_ARB_DIAG_IDLE 0x00200000 517 #define EMCR_RST 0x80000000 518 519 #define EISR_RXTIMERINT 0x00000001 520 #define EISR_RXTHRESHINT 0x00000002 521 #define EISR_RXOFLO 0x00000004 522 #define EISR_RXBUFOFLO 0x00000008 523 #define EISR_RXMEMERR 0x00000010 524 #define EISR_RXPARERR 0x00000020 525 #define EISR_TXEMPTY 0x00010000 526 #define EISR_TXRTRY 0x00020000 527 #define EISR_TXEXDEF 0x00040000 528 #define EISR_TXLCOL 0x00080000 529 #define EISR_TXGIANT 0x00100000 530 #define EISR_TXBUFUFLO 0x00200000 531 #define EISR_TXEXPLICIT 0x00400000 532 #define EISR_TXCOLLWRAP 0x00800000 533 #define EISR_TXDEFERWRAP 0x01000000 534 #define EISR_TXMEMERR 0x02000000 535 #define EISR_TXPARERR 0x04000000 536 537 #define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ 538 #define ERCSR_RX_TMR 0x40000000 /* simulation only */ 539 #define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ 540 541 #define ERBR_ALIGNMENT 4096 542 #define ERBR_L_RXRINGBASE_MASK 0xfffff000 543 544 #define ERBAR_BARRIER_BIT 0x0100 545 #define ERBAR_RXBARR_MASK 0xffff0000 546 #define ERBAR_RXBARR_SHIFT 16 547 548 #define ERCIR_RXCONSUME_MASK 0x00000fff 549 550 #define ERPIR_RXPRODUCE_MASK 0x00000fff 551 #define ERPIR_ARM 0x80000000 552 553 #define ERTR_CNT_MASK 0x000007ff 554 555 #define ETCSR_IPGT_MASK 0x0000007f 556 #define ETCSR_IPGR1_MASK 0x00007f00 557 #define ETCSR_IPGR1_SHIFT 8 558 #define ETCSR_IPGR2_MASK 0x007f0000 559 #define ETCSR_IPGR2_SHIFT 16 560 #define ETCSR_NOTXCLK 0x80000000 561 562 #define ETCDC_COLLCNT_MASK 0x0000ffff 563 #define ETCDC_DEFERCNT_MASK 0xffff0000 564 #define ETCDC_DEFERCNT_SHIFT 16 565 566 #define ETBR_ALIGNMENT (64*1024) 567 #define ETBR_L_RINGSZ_MASK 0x00000001 568 #define ETBR_L_RINGSZ128 0 569 #define ETBR_L_RINGSZ512 1 570 #define ETBR_L_TXRINGBASE_MASK 0xffffc000 571 572 #define ETCIR_TXCONSUME_MASK 0x0000ffff 573 #define ETCIR_IDLE 0x80000000 574 575 #define ETPIR_TXPRODUCE_MASK 0x0000ffff 576 577 #define EBIR_TXBUFPROD_MASK 0x0000001f 578 #define EBIR_TXBUFCONS_MASK 0x00001f00 579 #define EBIR_TXBUFCONS_SHIFT 8 580 #define EBIR_RXBUFPROD_MASK 0x007fc000 581 #define EBIR_RXBUFPROD_SHIFT 14 582 #define EBIR_RXBUFCONS_MASK 0xff800000 583 #define EBIR_RXBUFCONS_SHIFT 23 584 585 #define MICR_REGADDR_MASK 0x0000001f 586 #define MICR_PHYADDR_MASK 0x000003e0 587 #define MICR_PHYADDR_SHIFT 5 588 #define MICR_READTRIG 0x00000400 589 #define MICR_BUSY 0x00000800 590 591 #define MIDR_DATA_MASK 0x0000ffff 592 593 /* subsystem IDs supplied by card detection in pci-xtalk-bridge */ 594 #define IOC3_SUBSYS_IP27_BASEIO6G 0xc300 595 #define IOC3_SUBSYS_IP27_MIO 0xc301 596 #define IOC3_SUBSYS_IP27_BASEIO 0xc302 597 #define IOC3_SUBSYS_IP29_SYSBOARD 0xc303 598 #define IOC3_SUBSYS_IP30_SYSBOARD 0xc304 599 #define IOC3_SUBSYS_MENET 0xc305 600 #define IOC3_SUBSYS_MENET4 0xc306 601 602 #endif /* MIPS_SN_IOC3_H */ 603