1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * Copyright (C) 1999, 2000 Ralf Baechle 3384740dcSRalf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 4384740dcSRalf Baechle */ 5384740dcSRalf Baechle #ifndef _IOC3_H 6384740dcSRalf Baechle #define _IOC3_H 7384740dcSRalf Baechle 8384740dcSRalf Baechle #include <linux/types.h> 9384740dcSRalf Baechle 10384740dcSRalf Baechle /* SUPERIO uart register map */ 11384740dcSRalf Baechle typedef volatile struct ioc3_uartregs { 12384740dcSRalf Baechle union { 13384740dcSRalf Baechle volatile u8 rbr; /* read only, DLAB == 0 */ 14384740dcSRalf Baechle volatile u8 thr; /* write only, DLAB == 0 */ 15384740dcSRalf Baechle volatile u8 dll; /* DLAB == 1 */ 16384740dcSRalf Baechle } u1; 17384740dcSRalf Baechle union { 18384740dcSRalf Baechle volatile u8 ier; /* DLAB == 0 */ 19384740dcSRalf Baechle volatile u8 dlm; /* DLAB == 1 */ 20384740dcSRalf Baechle } u2; 21384740dcSRalf Baechle union { 22384740dcSRalf Baechle volatile u8 iir; /* read only */ 23384740dcSRalf Baechle volatile u8 fcr; /* write only */ 24384740dcSRalf Baechle } u3; 25384740dcSRalf Baechle volatile u8 iu_lcr; 26384740dcSRalf Baechle volatile u8 iu_mcr; 27384740dcSRalf Baechle volatile u8 iu_lsr; 28384740dcSRalf Baechle volatile u8 iu_msr; 29384740dcSRalf Baechle volatile u8 iu_scr; 30384740dcSRalf Baechle } ioc3_uregs_t; 31384740dcSRalf Baechle 32384740dcSRalf Baechle #define iu_rbr u1.rbr 33384740dcSRalf Baechle #define iu_thr u1.thr 34384740dcSRalf Baechle #define iu_dll u1.dll 35384740dcSRalf Baechle #define iu_ier u2.ier 36384740dcSRalf Baechle #define iu_dlm u2.dlm 37384740dcSRalf Baechle #define iu_iir u3.iir 38384740dcSRalf Baechle #define iu_fcr u3.fcr 39384740dcSRalf Baechle 40384740dcSRalf Baechle struct ioc3_sioregs { 41384740dcSRalf Baechle volatile u8 fill[0x141]; /* starts at 0x141 */ 42384740dcSRalf Baechle 43384740dcSRalf Baechle volatile u8 uartc; 44384740dcSRalf Baechle volatile u8 kbdcg; 45384740dcSRalf Baechle 46384740dcSRalf Baechle volatile u8 fill0[0x150 - 0x142 - 1]; 47384740dcSRalf Baechle 48384740dcSRalf Baechle volatile u8 pp_data; 49384740dcSRalf Baechle volatile u8 pp_dsr; 50384740dcSRalf Baechle volatile u8 pp_dcr; 51384740dcSRalf Baechle 52384740dcSRalf Baechle volatile u8 fill1[0x158 - 0x152 - 1]; 53384740dcSRalf Baechle 54384740dcSRalf Baechle volatile u8 pp_fifa; 55384740dcSRalf Baechle volatile u8 pp_cfgb; 56384740dcSRalf Baechle volatile u8 pp_ecr; 57384740dcSRalf Baechle 58384740dcSRalf Baechle volatile u8 fill2[0x168 - 0x15a - 1]; 59384740dcSRalf Baechle 60384740dcSRalf Baechle volatile u8 rtcad; 61384740dcSRalf Baechle volatile u8 rtcdat; 62384740dcSRalf Baechle 63384740dcSRalf Baechle volatile u8 fill3[0x170 - 0x169 - 1]; 64384740dcSRalf Baechle 65384740dcSRalf Baechle struct ioc3_uartregs uartb; /* 0x20170 */ 66384740dcSRalf Baechle struct ioc3_uartregs uarta; /* 0x20178 */ 67384740dcSRalf Baechle }; 68384740dcSRalf Baechle 69384740dcSRalf Baechle /* Register layout of IOC3 in configuration space. */ 70384740dcSRalf Baechle struct ioc3 { 71384740dcSRalf Baechle volatile u32 pad0[7]; /* 0x00000 */ 72384740dcSRalf Baechle volatile u32 sio_ir; /* 0x0001c */ 73384740dcSRalf Baechle volatile u32 sio_ies; /* 0x00020 */ 74384740dcSRalf Baechle volatile u32 sio_iec; /* 0x00024 */ 75384740dcSRalf Baechle volatile u32 sio_cr; /* 0x00028 */ 76384740dcSRalf Baechle volatile u32 int_out; /* 0x0002c */ 77384740dcSRalf Baechle volatile u32 mcr; /* 0x00030 */ 78384740dcSRalf Baechle 79384740dcSRalf Baechle /* General Purpose I/O registers */ 80384740dcSRalf Baechle volatile u32 gpcr_s; /* 0x00034 */ 81384740dcSRalf Baechle volatile u32 gpcr_c; /* 0x00038 */ 82384740dcSRalf Baechle volatile u32 gpdr; /* 0x0003c */ 83384740dcSRalf Baechle volatile u32 gppr_0; /* 0x00040 */ 84384740dcSRalf Baechle volatile u32 gppr_1; /* 0x00044 */ 85384740dcSRalf Baechle volatile u32 gppr_2; /* 0x00048 */ 86384740dcSRalf Baechle volatile u32 gppr_3; /* 0x0004c */ 87384740dcSRalf Baechle volatile u32 gppr_4; /* 0x00050 */ 88384740dcSRalf Baechle volatile u32 gppr_5; /* 0x00054 */ 89384740dcSRalf Baechle volatile u32 gppr_6; /* 0x00058 */ 90384740dcSRalf Baechle volatile u32 gppr_7; /* 0x0005c */ 91384740dcSRalf Baechle volatile u32 gppr_8; /* 0x00060 */ 92384740dcSRalf Baechle volatile u32 gppr_9; /* 0x00064 */ 93384740dcSRalf Baechle volatile u32 gppr_10; /* 0x00068 */ 94384740dcSRalf Baechle volatile u32 gppr_11; /* 0x0006c */ 95384740dcSRalf Baechle volatile u32 gppr_12; /* 0x00070 */ 96384740dcSRalf Baechle volatile u32 gppr_13; /* 0x00074 */ 97384740dcSRalf Baechle volatile u32 gppr_14; /* 0x00078 */ 98384740dcSRalf Baechle volatile u32 gppr_15; /* 0x0007c */ 99384740dcSRalf Baechle 100384740dcSRalf Baechle /* Parallel Port Registers */ 101384740dcSRalf Baechle volatile u32 ppbr_h_a; /* 0x00080 */ 102384740dcSRalf Baechle volatile u32 ppbr_l_a; /* 0x00084 */ 103384740dcSRalf Baechle volatile u32 ppcr_a; /* 0x00088 */ 104384740dcSRalf Baechle volatile u32 ppcr; /* 0x0008c */ 105384740dcSRalf Baechle volatile u32 ppbr_h_b; /* 0x00090 */ 106384740dcSRalf Baechle volatile u32 ppbr_l_b; /* 0x00094 */ 107384740dcSRalf Baechle volatile u32 ppcr_b; /* 0x00098 */ 108384740dcSRalf Baechle 109384740dcSRalf Baechle /* Keyboard and Mouse Registers */ 110384740dcSRalf Baechle volatile u32 km_csr; /* 0x0009c */ 111384740dcSRalf Baechle volatile u32 k_rd; /* 0x000a0 */ 112384740dcSRalf Baechle volatile u32 m_rd; /* 0x000a4 */ 113384740dcSRalf Baechle volatile u32 k_wd; /* 0x000a8 */ 114384740dcSRalf Baechle volatile u32 m_wd; /* 0x000ac */ 115384740dcSRalf Baechle 116384740dcSRalf Baechle /* Serial Port Registers */ 117384740dcSRalf Baechle volatile u32 sbbr_h; /* 0x000b0 */ 118384740dcSRalf Baechle volatile u32 sbbr_l; /* 0x000b4 */ 119384740dcSRalf Baechle volatile u32 sscr_a; /* 0x000b8 */ 120384740dcSRalf Baechle volatile u32 stpir_a; /* 0x000bc */ 121384740dcSRalf Baechle volatile u32 stcir_a; /* 0x000c0 */ 122384740dcSRalf Baechle volatile u32 srpir_a; /* 0x000c4 */ 123384740dcSRalf Baechle volatile u32 srcir_a; /* 0x000c8 */ 124384740dcSRalf Baechle volatile u32 srtr_a; /* 0x000cc */ 125384740dcSRalf Baechle volatile u32 shadow_a; /* 0x000d0 */ 126384740dcSRalf Baechle volatile u32 sscr_b; /* 0x000d4 */ 127384740dcSRalf Baechle volatile u32 stpir_b; /* 0x000d8 */ 128384740dcSRalf Baechle volatile u32 stcir_b; /* 0x000dc */ 129384740dcSRalf Baechle volatile u32 srpir_b; /* 0x000e0 */ 130384740dcSRalf Baechle volatile u32 srcir_b; /* 0x000e4 */ 131384740dcSRalf Baechle volatile u32 srtr_b; /* 0x000e8 */ 132384740dcSRalf Baechle volatile u32 shadow_b; /* 0x000ec */ 133384740dcSRalf Baechle 134384740dcSRalf Baechle /* Ethernet Registers */ 135384740dcSRalf Baechle volatile u32 emcr; /* 0x000f0 */ 136384740dcSRalf Baechle volatile u32 eisr; /* 0x000f4 */ 137384740dcSRalf Baechle volatile u32 eier; /* 0x000f8 */ 138384740dcSRalf Baechle volatile u32 ercsr; /* 0x000fc */ 139384740dcSRalf Baechle volatile u32 erbr_h; /* 0x00100 */ 140384740dcSRalf Baechle volatile u32 erbr_l; /* 0x00104 */ 141384740dcSRalf Baechle volatile u32 erbar; /* 0x00108 */ 142384740dcSRalf Baechle volatile u32 ercir; /* 0x0010c */ 143384740dcSRalf Baechle volatile u32 erpir; /* 0x00110 */ 144384740dcSRalf Baechle volatile u32 ertr; /* 0x00114 */ 145384740dcSRalf Baechle volatile u32 etcsr; /* 0x00118 */ 146384740dcSRalf Baechle volatile u32 ersr; /* 0x0011c */ 147384740dcSRalf Baechle volatile u32 etcdc; /* 0x00120 */ 148384740dcSRalf Baechle volatile u32 ebir; /* 0x00124 */ 149384740dcSRalf Baechle volatile u32 etbr_h; /* 0x00128 */ 150384740dcSRalf Baechle volatile u32 etbr_l; /* 0x0012c */ 151384740dcSRalf Baechle volatile u32 etcir; /* 0x00130 */ 152384740dcSRalf Baechle volatile u32 etpir; /* 0x00134 */ 153384740dcSRalf Baechle volatile u32 emar_h; /* 0x00138 */ 154384740dcSRalf Baechle volatile u32 emar_l; /* 0x0013c */ 155384740dcSRalf Baechle volatile u32 ehar_h; /* 0x00140 */ 156384740dcSRalf Baechle volatile u32 ehar_l; /* 0x00144 */ 157384740dcSRalf Baechle volatile u32 micr; /* 0x00148 */ 158384740dcSRalf Baechle volatile u32 midr_r; /* 0x0014c */ 159384740dcSRalf Baechle volatile u32 midr_w; /* 0x00150 */ 160384740dcSRalf Baechle volatile u32 pad1[(0x20000 - 0x00154) / 4]; 161384740dcSRalf Baechle 162384740dcSRalf Baechle /* SuperIO Registers XXX */ 163384740dcSRalf Baechle struct ioc3_sioregs sregs; /* 0x20000 */ 164384740dcSRalf Baechle volatile u32 pad2[(0x40000 - 0x20180) / 4]; 165384740dcSRalf Baechle 166384740dcSRalf Baechle /* SSRAM Diagnostic Access */ 167384740dcSRalf Baechle volatile u32 ssram[(0x80000 - 0x40000) / 4]; 168384740dcSRalf Baechle 169384740dcSRalf Baechle /* Bytebus device offsets 170384740dcSRalf Baechle 0x80000 - Access to the generic devices selected with DEV0 171384740dcSRalf Baechle 0x9FFFF bytebus DEV_SEL_0 172384740dcSRalf Baechle 0xA0000 - Access to the generic devices selected with DEV1 173384740dcSRalf Baechle 0xBFFFF bytebus DEV_SEL_1 174384740dcSRalf Baechle 0xC0000 - Access to the generic devices selected with DEV2 175384740dcSRalf Baechle 0xDFFFF bytebus DEV_SEL_2 176384740dcSRalf Baechle 0xE0000 - Access to the generic devices selected with DEV3 177384740dcSRalf Baechle 0xFFFFF bytebus DEV_SEL_3 */ 178384740dcSRalf Baechle }; 179384740dcSRalf Baechle 180384740dcSRalf Baechle /* 181384740dcSRalf Baechle * Ethernet RX Buffer 182384740dcSRalf Baechle */ 183384740dcSRalf Baechle struct ioc3_erxbuf { 184384740dcSRalf Baechle u32 w0; /* first word (valid,bcnt,cksum) */ 185384740dcSRalf Baechle u32 err; /* second word various errors */ 186384740dcSRalf Baechle /* next comes n bytes of padding */ 187384740dcSRalf Baechle /* then the received ethernet frame itself */ 188384740dcSRalf Baechle }; 189384740dcSRalf Baechle 190384740dcSRalf Baechle #define ERXBUF_IPCKSUM_MASK 0x0000ffff 191384740dcSRalf Baechle #define ERXBUF_BYTECNT_MASK 0x07ff0000 192384740dcSRalf Baechle #define ERXBUF_BYTECNT_SHIFT 16 193384740dcSRalf Baechle #define ERXBUF_V 0x80000000 194384740dcSRalf Baechle 195384740dcSRalf Baechle #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ 196384740dcSRalf Baechle #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ 197384740dcSRalf Baechle #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ 198384740dcSRalf Baechle #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ 199384740dcSRalf Baechle #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ 200384740dcSRalf Baechle #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ 201384740dcSRalf Baechle #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ 202384740dcSRalf Baechle #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ 203384740dcSRalf Baechle #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ 204384740dcSRalf Baechle #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ 205384740dcSRalf Baechle #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ 206384740dcSRalf Baechle #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ 207384740dcSRalf Baechle 208384740dcSRalf Baechle /* 209384740dcSRalf Baechle * Ethernet TX Descriptor 210384740dcSRalf Baechle */ 211384740dcSRalf Baechle #define ETXD_DATALEN 104 212384740dcSRalf Baechle struct ioc3_etxd { 213384740dcSRalf Baechle u32 cmd; /* command field */ 214384740dcSRalf Baechle u32 bufcnt; /* buffer counts field */ 215384740dcSRalf Baechle u64 p1; /* buffer pointer 1 */ 216384740dcSRalf Baechle u64 p2; /* buffer pointer 2 */ 217384740dcSRalf Baechle u8 data[ETXD_DATALEN]; /* opt. tx data */ 218384740dcSRalf Baechle }; 219384740dcSRalf Baechle 220384740dcSRalf Baechle #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ 221384740dcSRalf Baechle #define ETXD_INTWHENDONE 0x00001000 /* intr when done */ 222384740dcSRalf Baechle #define ETXD_D0V 0x00010000 /* data 0 valid */ 223384740dcSRalf Baechle #define ETXD_B1V 0x00020000 /* buf 1 valid */ 224384740dcSRalf Baechle #define ETXD_B2V 0x00040000 /* buf 2 valid */ 225384740dcSRalf Baechle #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ 226384740dcSRalf Baechle #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ 227384740dcSRalf Baechle #define ETXD_CHKOFF_SHIFT 20 228384740dcSRalf Baechle 229384740dcSRalf Baechle #define ETXD_D0CNT_MASK 0x0000007f 230384740dcSRalf Baechle #define ETXD_B1CNT_MASK 0x0007ff00 231384740dcSRalf Baechle #define ETXD_B1CNT_SHIFT 8 232384740dcSRalf Baechle #define ETXD_B2CNT_MASK 0x7ff00000 233384740dcSRalf Baechle #define ETXD_B2CNT_SHIFT 20 234384740dcSRalf Baechle 235384740dcSRalf Baechle /* 236384740dcSRalf Baechle * Bytebus device space 237384740dcSRalf Baechle */ 238384740dcSRalf Baechle #define IOC3_BYTEBUS_DEV0 0x80000L 239384740dcSRalf Baechle #define IOC3_BYTEBUS_DEV1 0xa0000L 240384740dcSRalf Baechle #define IOC3_BYTEBUS_DEV2 0xc0000L 241384740dcSRalf Baechle #define IOC3_BYTEBUS_DEV3 0xe0000L 242384740dcSRalf Baechle 243384740dcSRalf Baechle /* ------------------------------------------------------------------------- */ 244384740dcSRalf Baechle 245384740dcSRalf Baechle /* Superio Registers (PIO Access) */ 246384740dcSRalf Baechle #define IOC3_SIO_BASE 0x20000 247384740dcSRalf Baechle #define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ 248384740dcSRalf Baechle #define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ 249384740dcSRalf Baechle #define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ 250384740dcSRalf Baechle #define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ 251384740dcSRalf Baechle #define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ 252384740dcSRalf Baechle #define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ 253384740dcSRalf Baechle 254384740dcSRalf Baechle /* SSRAM Diagnostic Access */ 255384740dcSRalf Baechle #define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ 256384740dcSRalf Baechle #define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ 257384740dcSRalf Baechle #define IOC3_SSRAM_DM 0x0000ffff /* data mask */ 258384740dcSRalf Baechle #define IOC3_SSRAM_PM 0x00010000 /* parity mask */ 259384740dcSRalf Baechle 260384740dcSRalf Baechle /* bitmasks for PCI_SCR */ 261384740dcSRalf Baechle #define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ 262384740dcSRalf Baechle #define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ 263384740dcSRalf Baechle #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ 264384740dcSRalf Baechle #define PCI_SCR_RX_SERR (0x1 << 16) 265384740dcSRalf Baechle #define PCI_SCR_DROP_MODE (0x1 << 17) 266384740dcSRalf Baechle #define PCI_SCR_SIG_PAR_ERR (0x1 << 24) 267384740dcSRalf Baechle #define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) 268384740dcSRalf Baechle #define PCI_SCR_RX_TAR_ABRT (0x1 << 28) 269384740dcSRalf Baechle #define PCI_SCR_SIG_MST_ABRT (0x1 << 29) 270384740dcSRalf Baechle #define PCI_SCR_SIG_SERR (0x1 << 30) 271384740dcSRalf Baechle #define PCI_SCR_PAR_ERR (0x1 << 31) 272384740dcSRalf Baechle 273384740dcSRalf Baechle /* bitmasks for IOC3_KM_CSR */ 274384740dcSRalf Baechle #define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ 275384740dcSRalf Baechle #define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ 276384740dcSRalf Baechle #define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ 277384740dcSRalf Baechle #define KM_CSR_M_LCB 0x00000008 /* same for mouse */ 278384740dcSRalf Baechle #define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ 279384740dcSRalf Baechle #define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ 280384740dcSRalf Baechle #define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ 281384740dcSRalf Baechle #define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ 282384740dcSRalf Baechle #define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ 283384740dcSRalf Baechle #define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ 284384740dcSRalf Baechle #define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ 285384740dcSRalf Baechle #define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ 286384740dcSRalf Baechle #define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ 287384740dcSRalf Baechle #define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ 288384740dcSRalf Baechle #define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ 289384740dcSRalf Baechle #define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ 290384740dcSRalf Baechle #define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ 291384740dcSRalf Baechle #define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ 292384740dcSRalf Baechle #define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause 293384740dcSRalf Baechle SIO_IR to assert */ 294384740dcSRalf Baechle #define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause 295384740dcSRalf Baechle SIO_IR to assert */ 296384740dcSRalf Baechle #define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ 297384740dcSRalf Baechle #define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ 298384740dcSRalf Baechle #define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ 299384740dcSRalf Baechle #define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ 300384740dcSRalf Baechle 301384740dcSRalf Baechle /* bitmasks for IOC3_K_RD and IOC3_M_RD */ 302384740dcSRalf Baechle #define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ 303384740dcSRalf Baechle #define KM_RD_DATA_2_SHIFT 0 304384740dcSRalf Baechle #define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ 305384740dcSRalf Baechle #define KM_RD_DATA_1_SHIFT 8 306384740dcSRalf Baechle #define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ 307384740dcSRalf Baechle #define KM_RD_DATA_0_SHIFT 16 308384740dcSRalf Baechle #define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ 309384740dcSRalf Baechle #define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ 310384740dcSRalf Baechle #define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ 311384740dcSRalf Baechle 312384740dcSRalf Baechle #define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ 313384740dcSRalf Baechle #define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ 314384740dcSRalf Baechle #define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ 315384740dcSRalf Baechle #define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ 316384740dcSRalf Baechle #define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ 317384740dcSRalf Baechle #define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) 318384740dcSRalf Baechle 319384740dcSRalf Baechle /* bitmasks for IOC3_K_WD & IOC3_M_WD */ 320384740dcSRalf Baechle #define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ 321384740dcSRalf Baechle #define KM_WD_WRT_DATA_SHIFT 0 322384740dcSRalf Baechle 323384740dcSRalf Baechle /* bitmasks for serial RX status byte */ 324384740dcSRalf Baechle #define RXSB_OVERRUN 0x01 /* char(s) lost */ 325384740dcSRalf Baechle #define RXSB_PAR_ERR 0x02 /* parity error */ 326384740dcSRalf Baechle #define RXSB_FRAME_ERR 0x04 /* framing error */ 327384740dcSRalf Baechle #define RXSB_BREAK 0x08 /* break character */ 328384740dcSRalf Baechle #define RXSB_CTS 0x10 /* state of CTS */ 329384740dcSRalf Baechle #define RXSB_DCD 0x20 /* state of DCD */ 330384740dcSRalf Baechle #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ 331384740dcSRalf Baechle #define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ 332384740dcSRalf Baechle 333384740dcSRalf Baechle /* bitmasks for serial TX control byte */ 334384740dcSRalf Baechle #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ 335384740dcSRalf Baechle #define TXCB_INVALID 0x00 /* byte is invalid */ 336384740dcSRalf Baechle #define TXCB_VALID 0x40 /* byte is valid */ 337384740dcSRalf Baechle #define TXCB_MCR 0x80 /* data<7:0> to modem control register */ 338384740dcSRalf Baechle #define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ 339384740dcSRalf Baechle 340384740dcSRalf Baechle /* bitmasks for IOC3_SBBR_L */ 341384740dcSRalf Baechle #define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ 342384740dcSRalf Baechle #define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ 343384740dcSRalf Baechle 344384740dcSRalf Baechle /* bitmasks for IOC3_SSCR_<A:B> */ 345384740dcSRalf Baechle #define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ 346384740dcSRalf Baechle #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ 347384740dcSRalf Baechle #define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ 348384740dcSRalf Baechle #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ 349384740dcSRalf Baechle #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ 350384740dcSRalf Baechle #define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ 351384740dcSRalf Baechle #define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ 352384740dcSRalf Baechle #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ 353384740dcSRalf Baechle #define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ 354384740dcSRalf Baechle #define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ 355384740dcSRalf Baechle #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ 356384740dcSRalf Baechle #define SSCR_RESET 0x80000000 /* reset DMA channels */ 357384740dcSRalf Baechle 358384740dcSRalf Baechle /* all producer/comsumer pointers are the same bitfield */ 359384740dcSRalf Baechle #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ 360384740dcSRalf Baechle #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ 361384740dcSRalf Baechle #define PROD_CONS_PTR_OFF 3 362384740dcSRalf Baechle 363384740dcSRalf Baechle /* bitmasks for IOC3_SRCIR_<A:B> */ 364384740dcSRalf Baechle #define SRCIR_ARM 0x80000000 /* arm RX timer */ 365384740dcSRalf Baechle 366384740dcSRalf Baechle /* bitmasks for IOC3_SRPIR_<A:B> */ 367384740dcSRalf Baechle #define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ 368384740dcSRalf Baechle #define SRPIR_BYTE_CNT_SHIFT 24 369384740dcSRalf Baechle 370384740dcSRalf Baechle /* bitmasks for IOC3_STCIR_<A:B> */ 371384740dcSRalf Baechle #define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ 372384740dcSRalf Baechle #define STCIR_BYTE_CNT_SHIFT 24 373384740dcSRalf Baechle 374384740dcSRalf Baechle /* bitmasks for IOC3_SHADOW_<A:B> */ 375384740dcSRalf Baechle #define SHADOW_DR 0x00000001 /* data ready */ 376384740dcSRalf Baechle #define SHADOW_OE 0x00000002 /* overrun error */ 377384740dcSRalf Baechle #define SHADOW_PE 0x00000004 /* parity error */ 378384740dcSRalf Baechle #define SHADOW_FE 0x00000008 /* framing error */ 379384740dcSRalf Baechle #define SHADOW_BI 0x00000010 /* break interrupt */ 380384740dcSRalf Baechle #define SHADOW_THRE 0x00000020 /* transmit holding register empty */ 381384740dcSRalf Baechle #define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ 382384740dcSRalf Baechle #define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ 383384740dcSRalf Baechle #define SHADOW_DCTS 0x00010000 /* delta clear to send */ 384384740dcSRalf Baechle #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ 385384740dcSRalf Baechle #define SHADOW_CTS 0x00100000 /* clear to send */ 386384740dcSRalf Baechle #define SHADOW_DCD 0x00800000 /* data carrier detect */ 387384740dcSRalf Baechle #define SHADOW_DTR 0x01000000 /* data terminal ready */ 388384740dcSRalf Baechle #define SHADOW_RTS 0x02000000 /* request to send */ 389384740dcSRalf Baechle #define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ 390384740dcSRalf Baechle #define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ 391384740dcSRalf Baechle #define SHADOW_LOOP 0x10000000 /* loopback enabled */ 392384740dcSRalf Baechle 393384740dcSRalf Baechle /* bitmasks for IOC3_SRTR_<A:B> */ 394384740dcSRalf Baechle #define SRTR_CNT 0x00000fff /* reload value for RX timer */ 395384740dcSRalf Baechle #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ 396384740dcSRalf Baechle #define SRTR_CNT_VAL_SHIFT 16 397384740dcSRalf Baechle #define SRTR_HZ 16000 /* SRTR clock frequency */ 398384740dcSRalf Baechle 399384740dcSRalf Baechle /* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ 400384740dcSRalf Baechle #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ 401384740dcSRalf Baechle #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ 402384740dcSRalf Baechle #define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ 403384740dcSRalf Baechle #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ 404384740dcSRalf Baechle #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ 405384740dcSRalf Baechle #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ 406384740dcSRalf Baechle #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ 407384740dcSRalf Baechle #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ 408384740dcSRalf Baechle #define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ 409384740dcSRalf Baechle #define SIO_IR_SB_TX_MT 0x00000200 /* */ 410384740dcSRalf Baechle #define SIO_IR_SB_RX_FULL 0x00000400 /* */ 411384740dcSRalf Baechle #define SIO_IR_SB_RX_HIGH 0x00000800 /* */ 412384740dcSRalf Baechle #define SIO_IR_SB_RX_TIMER 0x00001000 /* */ 413384740dcSRalf Baechle #define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ 414384740dcSRalf Baechle #define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ 415384740dcSRalf Baechle #define SIO_IR_SB_INT 0x00008000 /* */ 416384740dcSRalf Baechle #define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ 417384740dcSRalf Baechle #define SIO_IR_SB_MEMERR 0x00020000 /* */ 418384740dcSRalf Baechle #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ 419384740dcSRalf Baechle #define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ 420384740dcSRalf Baechle #define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ 421384740dcSRalf Baechle #define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ 422384740dcSRalf Baechle #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ 423384740dcSRalf Baechle #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ 424384740dcSRalf Baechle #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ 425384740dcSRalf Baechle #define SIO_IR_GEN_INT_SHIFT 28 426384740dcSRalf Baechle 427384740dcSRalf Baechle /* per device interrupt masks */ 428384740dcSRalf Baechle #define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ 429384740dcSRalf Baechle SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ 430384740dcSRalf Baechle SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ 431384740dcSRalf Baechle SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ 432384740dcSRalf Baechle SIO_IR_SA_MEMERR) 433384740dcSRalf Baechle #define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ 434384740dcSRalf Baechle SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ 435384740dcSRalf Baechle SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ 436384740dcSRalf Baechle SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ 437384740dcSRalf Baechle SIO_IR_SB_MEMERR) 438384740dcSRalf Baechle #define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ 439384740dcSRalf Baechle SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) 440384740dcSRalf Baechle #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) 441384740dcSRalf Baechle 442384740dcSRalf Baechle /* macro to load pending interrupts */ 443384740dcSRalf Baechle #define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ 444384740dcSRalf Baechle PCI_INW(&((mem)->sio_ies_ro))) 445384740dcSRalf Baechle 446384740dcSRalf Baechle /* bitmasks for SIO_CR */ 447384740dcSRalf Baechle #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ 448384740dcSRalf Baechle #define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ 449384740dcSRalf Baechle #define SIO_CR_SER_A_BASE_SHIFT 1 450384740dcSRalf Baechle #define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ 451384740dcSRalf Baechle #define SIO_CR_SER_B_BASE_SHIFT 8 452384740dcSRalf Baechle #define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ 453384740dcSRalf Baechle #define SIO_CR_CMD_PULSE_SHIFT 15 454384740dcSRalf Baechle #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ 455384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_TXA 0x00000000 456384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_RXA 0x00080000 457384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_TXB 0x00100000 458384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_RXB 0x00180000 459384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_PP 0x00200000 460384740dcSRalf Baechle #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ 461384740dcSRalf Baechle 462384740dcSRalf Baechle /* bitmasks for INT_OUT */ 463384740dcSRalf Baechle #define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ 464384740dcSRalf Baechle #define INT_OUT_MODE 0x00070000 /* mode mask */ 465384740dcSRalf Baechle #define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ 466384740dcSRalf Baechle #define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ 467384740dcSRalf Baechle #define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ 468384740dcSRalf Baechle #define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ 469384740dcSRalf Baechle #define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ 470384740dcSRalf Baechle #define INT_OUT_DIAG 0x40000000 /* diag mode */ 471384740dcSRalf Baechle #define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ 472384740dcSRalf Baechle 473384740dcSRalf Baechle /* time constants for INT_OUT */ 474384740dcSRalf Baechle #define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ 475384740dcSRalf Baechle #define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ 476384740dcSRalf Baechle #define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ 477384740dcSRalf Baechle (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ 478384740dcSRalf Baechle 100 / INT_OUT_NS_PER_TICK - 1) 479384740dcSRalf Baechle #define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ 480384740dcSRalf Baechle (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) 481384740dcSRalf Baechle #define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ 482384740dcSRalf Baechle #define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ 483384740dcSRalf Baechle 484384740dcSRalf Baechle /* bitmasks for GPCR */ 485384740dcSRalf Baechle #define GPCR_DIR 0x000000ff /* tristate pin input or output */ 486384740dcSRalf Baechle #define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ 487384740dcSRalf Baechle #define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ 488384740dcSRalf Baechle #define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ 489384740dcSRalf Baechle 490384740dcSRalf Baechle /* values for GPCR */ 491384740dcSRalf Baechle #define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ 492384740dcSRalf Baechle #define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ 493384740dcSRalf Baechle #define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ 494384740dcSRalf Baechle #define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ 495384740dcSRalf Baechle #define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ 496384740dcSRalf Baechle 497384740dcSRalf Baechle /* defs for some of the generic I/O pins */ 498384740dcSRalf Baechle #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ 499384740dcSRalf Baechle #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ 500384740dcSRalf Baechle #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ 501384740dcSRalf Baechle 502384740dcSRalf Baechle #define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ 503384740dcSRalf Baechle #define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ 504384740dcSRalf Baechle #define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ 505384740dcSRalf Baechle 506384740dcSRalf Baechle #define EMCR_DUPLEX 0x00000001 507384740dcSRalf Baechle #define EMCR_PROMISC 0x00000002 508384740dcSRalf Baechle #define EMCR_PADEN 0x00000004 509384740dcSRalf Baechle #define EMCR_RXOFF_MASK 0x000001f8 510384740dcSRalf Baechle #define EMCR_RXOFF_SHIFT 3 511384740dcSRalf Baechle #define EMCR_RAMPAR 0x00000200 512384740dcSRalf Baechle #define EMCR_BADPAR 0x00000800 513384740dcSRalf Baechle #define EMCR_BUFSIZ 0x00001000 514384740dcSRalf Baechle #define EMCR_TXDMAEN 0x00002000 515384740dcSRalf Baechle #define EMCR_TXEN 0x00004000 516384740dcSRalf Baechle #define EMCR_RXDMAEN 0x00008000 517384740dcSRalf Baechle #define EMCR_RXEN 0x00010000 518384740dcSRalf Baechle #define EMCR_LOOPBACK 0x00020000 519384740dcSRalf Baechle #define EMCR_ARB_DIAG 0x001c0000 520384740dcSRalf Baechle #define EMCR_ARB_DIAG_IDLE 0x00200000 521384740dcSRalf Baechle #define EMCR_RST 0x80000000 522384740dcSRalf Baechle 523384740dcSRalf Baechle #define EISR_RXTIMERINT 0x00000001 524384740dcSRalf Baechle #define EISR_RXTHRESHINT 0x00000002 525384740dcSRalf Baechle #define EISR_RXOFLO 0x00000004 526384740dcSRalf Baechle #define EISR_RXBUFOFLO 0x00000008 527384740dcSRalf Baechle #define EISR_RXMEMERR 0x00000010 528384740dcSRalf Baechle #define EISR_RXPARERR 0x00000020 529384740dcSRalf Baechle #define EISR_TXEMPTY 0x00010000 530384740dcSRalf Baechle #define EISR_TXRTRY 0x00020000 531384740dcSRalf Baechle #define EISR_TXEXDEF 0x00040000 532384740dcSRalf Baechle #define EISR_TXLCOL 0x00080000 533384740dcSRalf Baechle #define EISR_TXGIANT 0x00100000 534384740dcSRalf Baechle #define EISR_TXBUFUFLO 0x00200000 535384740dcSRalf Baechle #define EISR_TXEXPLICIT 0x00400000 536384740dcSRalf Baechle #define EISR_TXCOLLWRAP 0x00800000 537384740dcSRalf Baechle #define EISR_TXDEFERWRAP 0x01000000 538384740dcSRalf Baechle #define EISR_TXMEMERR 0x02000000 539384740dcSRalf Baechle #define EISR_TXPARERR 0x04000000 540384740dcSRalf Baechle 541384740dcSRalf Baechle #define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ 542384740dcSRalf Baechle #define ERCSR_RX_TMR 0x40000000 /* simulation only */ 543384740dcSRalf Baechle #define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ 544384740dcSRalf Baechle 545384740dcSRalf Baechle #define ERBR_ALIGNMENT 4096 546384740dcSRalf Baechle #define ERBR_L_RXRINGBASE_MASK 0xfffff000 547384740dcSRalf Baechle 548384740dcSRalf Baechle #define ERBAR_BARRIER_BIT 0x0100 549384740dcSRalf Baechle #define ERBAR_RXBARR_MASK 0xffff0000 550384740dcSRalf Baechle #define ERBAR_RXBARR_SHIFT 16 551384740dcSRalf Baechle 552384740dcSRalf Baechle #define ERCIR_RXCONSUME_MASK 0x00000fff 553384740dcSRalf Baechle 554384740dcSRalf Baechle #define ERPIR_RXPRODUCE_MASK 0x00000fff 555384740dcSRalf Baechle #define ERPIR_ARM 0x80000000 556384740dcSRalf Baechle 557384740dcSRalf Baechle #define ERTR_CNT_MASK 0x000007ff 558384740dcSRalf Baechle 559384740dcSRalf Baechle #define ETCSR_IPGT_MASK 0x0000007f 560384740dcSRalf Baechle #define ETCSR_IPGR1_MASK 0x00007f00 561384740dcSRalf Baechle #define ETCSR_IPGR1_SHIFT 8 562384740dcSRalf Baechle #define ETCSR_IPGR2_MASK 0x007f0000 563384740dcSRalf Baechle #define ETCSR_IPGR2_SHIFT 16 564384740dcSRalf Baechle #define ETCSR_NOTXCLK 0x80000000 565384740dcSRalf Baechle 566384740dcSRalf Baechle #define ETCDC_COLLCNT_MASK 0x0000ffff 567384740dcSRalf Baechle #define ETCDC_DEFERCNT_MASK 0xffff0000 568384740dcSRalf Baechle #define ETCDC_DEFERCNT_SHIFT 16 569384740dcSRalf Baechle 570384740dcSRalf Baechle #define ETBR_ALIGNMENT (64*1024) 571384740dcSRalf Baechle #define ETBR_L_RINGSZ_MASK 0x00000001 572384740dcSRalf Baechle #define ETBR_L_RINGSZ128 0 573384740dcSRalf Baechle #define ETBR_L_RINGSZ512 1 574384740dcSRalf Baechle #define ETBR_L_TXRINGBASE_MASK 0xffffc000 575384740dcSRalf Baechle 576384740dcSRalf Baechle #define ETCIR_TXCONSUME_MASK 0x0000ffff 577384740dcSRalf Baechle #define ETCIR_IDLE 0x80000000 578384740dcSRalf Baechle 579384740dcSRalf Baechle #define ETPIR_TXPRODUCE_MASK 0x0000ffff 580384740dcSRalf Baechle 581384740dcSRalf Baechle #define EBIR_TXBUFPROD_MASK 0x0000001f 582384740dcSRalf Baechle #define EBIR_TXBUFCONS_MASK 0x00001f00 583384740dcSRalf Baechle #define EBIR_TXBUFCONS_SHIFT 8 584384740dcSRalf Baechle #define EBIR_RXBUFPROD_MASK 0x007fc000 585384740dcSRalf Baechle #define EBIR_RXBUFPROD_SHIFT 14 586384740dcSRalf Baechle #define EBIR_RXBUFCONS_MASK 0xff800000 587384740dcSRalf Baechle #define EBIR_RXBUFCONS_SHIFT 23 588384740dcSRalf Baechle 589384740dcSRalf Baechle #define MICR_REGADDR_MASK 0x0000001f 590384740dcSRalf Baechle #define MICR_PHYADDR_MASK 0x000003e0 591384740dcSRalf Baechle #define MICR_PHYADDR_SHIFT 5 592384740dcSRalf Baechle #define MICR_READTRIG 0x00000400 593384740dcSRalf Baechle #define MICR_BUSY 0x00000800 594384740dcSRalf Baechle 595384740dcSRalf Baechle #define MIDR_DATA_MASK 0x0000ffff 596384740dcSRalf Baechle 597384740dcSRalf Baechle #define ERXBUF_IPCKSUM_MASK 0x0000ffff 598384740dcSRalf Baechle #define ERXBUF_BYTECNT_MASK 0x07ff0000 599384740dcSRalf Baechle #define ERXBUF_BYTECNT_SHIFT 16 600384740dcSRalf Baechle #define ERXBUF_V 0x80000000 601384740dcSRalf Baechle 602384740dcSRalf Baechle #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ 603384740dcSRalf Baechle #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ 604384740dcSRalf Baechle #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ 605384740dcSRalf Baechle #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ 606384740dcSRalf Baechle #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ 607384740dcSRalf Baechle #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ 608384740dcSRalf Baechle #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ 609384740dcSRalf Baechle #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ 610384740dcSRalf Baechle #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ 611384740dcSRalf Baechle #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ 612384740dcSRalf Baechle #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ 613384740dcSRalf Baechle #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ 614384740dcSRalf Baechle 615384740dcSRalf Baechle #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ 616384740dcSRalf Baechle #define ETXD_INTWHENDONE 0x00001000 /* intr when done */ 617384740dcSRalf Baechle #define ETXD_D0V 0x00010000 /* data 0 valid */ 618384740dcSRalf Baechle #define ETXD_B1V 0x00020000 /* buf 1 valid */ 619384740dcSRalf Baechle #define ETXD_B2V 0x00040000 /* buf 2 valid */ 620384740dcSRalf Baechle #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ 621384740dcSRalf Baechle #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ 622384740dcSRalf Baechle #define ETXD_CHKOFF_SHIFT 20 623384740dcSRalf Baechle 624384740dcSRalf Baechle #define ETXD_D0CNT_MASK 0x0000007f 625384740dcSRalf Baechle #define ETXD_B1CNT_MASK 0x0007ff00 626384740dcSRalf Baechle #define ETXD_B1CNT_SHIFT 8 627384740dcSRalf Baechle #define ETXD_B2CNT_MASK 0x7ff00000 628384740dcSRalf Baechle #define ETXD_B2CNT_SHIFT 20 629384740dcSRalf Baechle 630384740dcSRalf Baechle typedef enum ioc3_subdevs_e { 631384740dcSRalf Baechle ioc3_subdev_ether, 632384740dcSRalf Baechle ioc3_subdev_generic, 633384740dcSRalf Baechle ioc3_subdev_nic, 634384740dcSRalf Baechle ioc3_subdev_kbms, 635384740dcSRalf Baechle ioc3_subdev_ttya, 636384740dcSRalf Baechle ioc3_subdev_ttyb, 637384740dcSRalf Baechle ioc3_subdev_ecpp, 638384740dcSRalf Baechle ioc3_subdev_rt, 639384740dcSRalf Baechle ioc3_nsubdevs 640384740dcSRalf Baechle } ioc3_subdev_t; 641384740dcSRalf Baechle 642384740dcSRalf Baechle /* subdevice disable bits, 643384740dcSRalf Baechle * from the standard INFO_LBL_SUBDEVS 644384740dcSRalf Baechle */ 645384740dcSRalf Baechle #define IOC3_SDB_ETHER (1<<ioc3_subdev_ether) 646384740dcSRalf Baechle #define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic) 647384740dcSRalf Baechle #define IOC3_SDB_NIC (1<<ioc3_subdev_nic) 648384740dcSRalf Baechle #define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms) 649384740dcSRalf Baechle #define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya) 650384740dcSRalf Baechle #define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb) 651384740dcSRalf Baechle #define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp) 652384740dcSRalf Baechle #define IOC3_SDB_RT (1<<ioc3_subdev_rt) 653384740dcSRalf Baechle 654384740dcSRalf Baechle #define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1) 655384740dcSRalf Baechle 656384740dcSRalf Baechle #define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB) 657384740dcSRalf Baechle 658384740dcSRalf Baechle #define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS 659384740dcSRalf Baechle 660384740dcSRalf Baechle #define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER 661384740dcSRalf Baechle #define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT) 662384740dcSRalf Baechle 663384740dcSRalf Baechle #endif /* _IOC3_H */ 664