1384740dcSRalf Baechle /* ********************************************************************* 2384740dcSRalf Baechle * SB1250 Board Support Package 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * UART Constants File: sb1250_uart.h 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * This module contains constants and macros useful for 7384740dcSRalf Baechle * manipulating the SB1250's UARTs 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * SB1250 specification level: User's manual 1/02/02 10384740dcSRalf Baechle * 11384740dcSRalf Baechle ********************************************************************* 12384740dcSRalf Baechle * 13384740dcSRalf Baechle * Copyright 2000,2001,2002,2003 14384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 15384740dcSRalf Baechle * 16384740dcSRalf Baechle * This program is free software; you can redistribute it and/or 17384740dcSRalf Baechle * modify it under the terms of the GNU General Public License as 18384740dcSRalf Baechle * published by the Free Software Foundation; either version 2 of 19384740dcSRalf Baechle * the License, or (at your option) any later version. 20384740dcSRalf Baechle * 21384740dcSRalf Baechle * This program is distributed in the hope that it will be useful, 22384740dcSRalf Baechle * but WITHOUT ANY WARRANTY; without even the implied warranty of 23384740dcSRalf Baechle * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24384740dcSRalf Baechle * GNU General Public License for more details. 25384740dcSRalf Baechle * 26384740dcSRalf Baechle * You should have received a copy of the GNU General Public License 27384740dcSRalf Baechle * along with this program; if not, write to the Free Software 28384740dcSRalf Baechle * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29384740dcSRalf Baechle * MA 02111-1307 USA 30384740dcSRalf Baechle ********************************************************************* */ 31384740dcSRalf Baechle 32384740dcSRalf Baechle 33384740dcSRalf Baechle #ifndef _SB1250_UART_H 34384740dcSRalf Baechle #define _SB1250_UART_H 35384740dcSRalf Baechle 36384740dcSRalf Baechle #include "sb1250_defs.h" 37384740dcSRalf Baechle 38384740dcSRalf Baechle /* ********************************************************************** 39384740dcSRalf Baechle * DUART Registers 40384740dcSRalf Baechle ********************************************************************** */ 41384740dcSRalf Baechle 42384740dcSRalf Baechle /* 43384740dcSRalf Baechle * DUART Mode Register #1 (Table 10-3) 44384740dcSRalf Baechle * Register: DUART_MODE_REG_1_A 45384740dcSRalf Baechle * Register: DUART_MODE_REG_1_B 46384740dcSRalf Baechle */ 47384740dcSRalf Baechle 48384740dcSRalf Baechle #define S_DUART_BITS_PER_CHAR 0 49384740dcSRalf Baechle #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) 50384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) 51384740dcSRalf Baechle 52384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_RSV0 0 53384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_RSV1 1 54384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_7 2 55384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_8 3 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) 58384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) 59384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) 60384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) 61384740dcSRalf Baechle 62384740dcSRalf Baechle 63384740dcSRalf Baechle #define M_DUART_PARITY_TYPE_EVEN 0x00 64384740dcSRalf Baechle #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 65384740dcSRalf Baechle 66384740dcSRalf Baechle #define S_DUART_PARITY_MODE 3 67384740dcSRalf Baechle #define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) 68384740dcSRalf Baechle #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) 69384740dcSRalf Baechle 70384740dcSRalf Baechle #define K_DUART_PARITY_MODE_ADD 0 71384740dcSRalf Baechle #define K_DUART_PARITY_MODE_ADD_FIXED 1 72384740dcSRalf Baechle #define K_DUART_PARITY_MODE_NONE 2 73384740dcSRalf Baechle 74384740dcSRalf Baechle #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) 75384740dcSRalf Baechle #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) 76384740dcSRalf Baechle #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) 77384740dcSRalf Baechle 78384740dcSRalf Baechle #define M_DUART_TX_IRQ_SEL_TXRDY 0 79384740dcSRalf Baechle #define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) 80384740dcSRalf Baechle 81384740dcSRalf Baechle #define M_DUART_RX_IRQ_SEL_RXRDY 0 82384740dcSRalf Baechle #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) 83384740dcSRalf Baechle 84384740dcSRalf Baechle #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) 85384740dcSRalf Baechle 86384740dcSRalf Baechle /* 87384740dcSRalf Baechle * DUART Mode Register #2 (Table 10-4) 88384740dcSRalf Baechle * Register: DUART_MODE_REG_2_A 89384740dcSRalf Baechle * Register: DUART_MODE_REG_2_B 90384740dcSRalf Baechle */ 91384740dcSRalf Baechle 92384740dcSRalf Baechle #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ 93384740dcSRalf Baechle 94384740dcSRalf Baechle #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 95384740dcSRalf Baechle #define M_DUART_STOP_BIT_LEN_1 0 96384740dcSRalf Baechle 97384740dcSRalf Baechle #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) 98384740dcSRalf Baechle 99384740dcSRalf Baechle 100384740dcSRalf Baechle #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 101384740dcSRalf Baechle 102384740dcSRalf Baechle #define S_DUART_CHAN_MODE 6 103384740dcSRalf Baechle #define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) 104384740dcSRalf Baechle #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) 105384740dcSRalf Baechle 106384740dcSRalf Baechle #define K_DUART_CHAN_MODE_NORMAL 0 107384740dcSRalf Baechle #define K_DUART_CHAN_MODE_LCL_LOOP 2 108384740dcSRalf Baechle #define K_DUART_CHAN_MODE_REM_LOOP 3 109384740dcSRalf Baechle 110384740dcSRalf Baechle #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) 111384740dcSRalf Baechle #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) 112384740dcSRalf Baechle #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) 113384740dcSRalf Baechle 114384740dcSRalf Baechle /* 115384740dcSRalf Baechle * DUART Command Register (Table 10-5) 116384740dcSRalf Baechle * Register: DUART_CMD_A 117384740dcSRalf Baechle * Register: DUART_CMD_B 118384740dcSRalf Baechle */ 119384740dcSRalf Baechle 120384740dcSRalf Baechle #define M_DUART_RX_EN _SB_MAKEMASK1(0) 121384740dcSRalf Baechle #define M_DUART_RX_DIS _SB_MAKEMASK1(1) 122384740dcSRalf Baechle #define M_DUART_TX_EN _SB_MAKEMASK1(2) 123384740dcSRalf Baechle #define M_DUART_TX_DIS _SB_MAKEMASK1(3) 124384740dcSRalf Baechle 125384740dcSRalf Baechle #define S_DUART_MISC_CMD 4 126384740dcSRalf Baechle #define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) 127384740dcSRalf Baechle #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) 128384740dcSRalf Baechle 129384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION0 0 130384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION1 1 131384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_RX 2 132384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_TX 3 133384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION4 4 134384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 135384740dcSRalf Baechle #define K_DUART_MISC_CMD_START_BREAK 6 136384740dcSRalf Baechle #define K_DUART_MISC_CMD_STOP_BREAK 7 137384740dcSRalf Baechle 138384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) 139384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) 140384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) 141384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) 142384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) 143384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) 144384740dcSRalf Baechle #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 145384740dcSRalf Baechle #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 146384740dcSRalf Baechle 147384740dcSRalf Baechle #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 148384740dcSRalf Baechle 149384740dcSRalf Baechle /* 150384740dcSRalf Baechle * DUART Status Register (Table 10-6) 151384740dcSRalf Baechle * Register: DUART_STATUS_A 152384740dcSRalf Baechle * Register: DUART_STATUS_B 153384740dcSRalf Baechle * READ-ONLY 154384740dcSRalf Baechle */ 155384740dcSRalf Baechle 156384740dcSRalf Baechle #define M_DUART_RX_RDY _SB_MAKEMASK1(0) 157384740dcSRalf Baechle #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) 158384740dcSRalf Baechle #define M_DUART_TX_RDY _SB_MAKEMASK1(2) 159384740dcSRalf Baechle #define M_DUART_TX_EMT _SB_MAKEMASK1(3) 160384740dcSRalf Baechle #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) 161384740dcSRalf Baechle #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) 162384740dcSRalf Baechle #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) 163384740dcSRalf Baechle #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) 164384740dcSRalf Baechle 165384740dcSRalf Baechle /* 166384740dcSRalf Baechle * DUART Baud Rate Register (Table 10-7) 167384740dcSRalf Baechle * Register: DUART_CLK_SEL_A 168384740dcSRalf Baechle * Register: DUART_CLK_SEL_B 169384740dcSRalf Baechle */ 170384740dcSRalf Baechle 171384740dcSRalf Baechle #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) 172384740dcSRalf Baechle #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 173384740dcSRalf Baechle 174384740dcSRalf Baechle /* 175384740dcSRalf Baechle * DUART Data Registers (Table 10-8 and 10-9) 176384740dcSRalf Baechle * Register: DUART_RX_HOLD_A 177384740dcSRalf Baechle * Register: DUART_RX_HOLD_B 178384740dcSRalf Baechle * Register: DUART_TX_HOLD_A 179384740dcSRalf Baechle * Register: DUART_TX_HOLD_B 180384740dcSRalf Baechle */ 181384740dcSRalf Baechle 182384740dcSRalf Baechle #define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) 183384740dcSRalf Baechle #define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) 184384740dcSRalf Baechle 185384740dcSRalf Baechle /* 186384740dcSRalf Baechle * DUART Input Port Register (Table 10-10) 187384740dcSRalf Baechle * Register: DUART_IN_PORT 188384740dcSRalf Baechle */ 189384740dcSRalf Baechle 190384740dcSRalf Baechle #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) 191384740dcSRalf Baechle #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) 192384740dcSRalf Baechle #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) 193384740dcSRalf Baechle #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) 194384740dcSRalf Baechle #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) 195384740dcSRalf Baechle #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) 196384740dcSRalf Baechle #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) 197384740dcSRalf Baechle #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) 198384740dcSRalf Baechle 199384740dcSRalf Baechle /* 200384740dcSRalf Baechle * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) 201384740dcSRalf Baechle * Register: DUART_INPORT_CHNG 202384740dcSRalf Baechle */ 203384740dcSRalf Baechle 204384740dcSRalf Baechle #define S_DUART_IN_PIN_VAL 0 205384740dcSRalf Baechle #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) 206384740dcSRalf Baechle 207384740dcSRalf Baechle #define S_DUART_IN_PIN_CHNG 4 208384740dcSRalf Baechle #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) 209384740dcSRalf Baechle 210384740dcSRalf Baechle 211384740dcSRalf Baechle /* 212384740dcSRalf Baechle * DUART Output port control register (Table 10-14) 213384740dcSRalf Baechle * Register: DUART_OPCR 214384740dcSRalf Baechle */ 215384740dcSRalf Baechle 216384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ 217384740dcSRalf Baechle #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 218384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 219384740dcSRalf Baechle #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 220384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ 221384740dcSRalf Baechle 222384740dcSRalf Baechle /* 223384740dcSRalf Baechle * DUART Aux Control Register (Table 10-15) 224384740dcSRalf Baechle * Register: DUART_AUX_CTRL 225384740dcSRalf Baechle */ 226384740dcSRalf Baechle 227384740dcSRalf Baechle #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) 228384740dcSRalf Baechle #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 229384740dcSRalf Baechle #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 230384740dcSRalf Baechle #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 231384740dcSRalf Baechle #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) 232384740dcSRalf Baechle 233384740dcSRalf Baechle #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 234384740dcSRalf Baechle #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 235384740dcSRalf Baechle 236384740dcSRalf Baechle /* 237384740dcSRalf Baechle * DUART Interrupt Status Register (Table 10-16) 238384740dcSRalf Baechle * Register: DUART_ISR 239384740dcSRalf Baechle */ 240384740dcSRalf Baechle 241384740dcSRalf Baechle #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 242384740dcSRalf Baechle 243384740dcSRalf Baechle #define S_DUART_ISR_RX_A 1 244384740dcSRalf Baechle #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) 245384740dcSRalf Baechle #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) 246384740dcSRalf Baechle #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) 247384740dcSRalf Baechle 248384740dcSRalf Baechle #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 249384740dcSRalf Baechle #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 250384740dcSRalf Baechle #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) 251384740dcSRalf Baechle 252384740dcSRalf Baechle #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 253384740dcSRalf Baechle #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 254384740dcSRalf Baechle #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 255384740dcSRalf Baechle #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 256384740dcSRalf Baechle #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) 257384740dcSRalf Baechle 258384740dcSRalf Baechle /* 259384740dcSRalf Baechle * DUART Channel A Interrupt Status Register (Table 10-17) 260384740dcSRalf Baechle * DUART Channel B Interrupt Status Register (Table 10-18) 261384740dcSRalf Baechle * Register: DUART_ISR_A 262384740dcSRalf Baechle * Register: DUART_ISR_B 263384740dcSRalf Baechle */ 264384740dcSRalf Baechle 265384740dcSRalf Baechle #define M_DUART_ISR_TX _SB_MAKEMASK1(0) 266384740dcSRalf Baechle #define M_DUART_ISR_RX _SB_MAKEMASK1(1) 267384740dcSRalf Baechle #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 268384740dcSRalf Baechle #define M_DUART_ISR_IN _SB_MAKEMASK1(3) 269384740dcSRalf Baechle #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) 270384740dcSRalf Baechle #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) 271384740dcSRalf Baechle 272384740dcSRalf Baechle /* 273384740dcSRalf Baechle * DUART Interrupt Mask Register (Table 10-19) 274384740dcSRalf Baechle * Register: DUART_IMR 275384740dcSRalf Baechle */ 276384740dcSRalf Baechle 277384740dcSRalf Baechle #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) 278384740dcSRalf Baechle #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 279384740dcSRalf Baechle #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 280384740dcSRalf Baechle #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 281384740dcSRalf Baechle #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) 282384740dcSRalf Baechle 283384740dcSRalf Baechle #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 284384740dcSRalf Baechle #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 285384740dcSRalf Baechle #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 286384740dcSRalf Baechle #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 287384740dcSRalf Baechle #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) 288384740dcSRalf Baechle 289384740dcSRalf Baechle /* 290384740dcSRalf Baechle * DUART Channel A Interrupt Mask Register (Table 10-20) 291384740dcSRalf Baechle * DUART Channel B Interrupt Mask Register (Table 10-21) 292384740dcSRalf Baechle * Register: DUART_IMR_A 293384740dcSRalf Baechle * Register: DUART_IMR_B 294384740dcSRalf Baechle */ 295384740dcSRalf Baechle 296384740dcSRalf Baechle #define M_DUART_IMR_TX _SB_MAKEMASK1(0) 297384740dcSRalf Baechle #define M_DUART_IMR_RX _SB_MAKEMASK1(1) 298384740dcSRalf Baechle #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 299384740dcSRalf Baechle #define M_DUART_IMR_IN _SB_MAKEMASK1(3) 300384740dcSRalf Baechle #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) 301384740dcSRalf Baechle #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) 302384740dcSRalf Baechle 303384740dcSRalf Baechle 304384740dcSRalf Baechle /* 305384740dcSRalf Baechle * DUART Output Port Set Register (Table 10-22) 306384740dcSRalf Baechle * Register: DUART_SET_OPR 307384740dcSRalf Baechle */ 308384740dcSRalf Baechle 309384740dcSRalf Baechle #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) 310384740dcSRalf Baechle #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 311384740dcSRalf Baechle #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 312384740dcSRalf Baechle #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 313384740dcSRalf Baechle #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) 314384740dcSRalf Baechle 315384740dcSRalf Baechle /* 316384740dcSRalf Baechle * DUART Output Port Clear Register (Table 10-23) 317384740dcSRalf Baechle * Register: DUART_CLEAR_OPR 318384740dcSRalf Baechle */ 319384740dcSRalf Baechle 320384740dcSRalf Baechle #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) 321384740dcSRalf Baechle #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 322384740dcSRalf Baechle #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 323384740dcSRalf Baechle #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 324384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) 325384740dcSRalf Baechle 326384740dcSRalf Baechle /* 327384740dcSRalf Baechle * DUART Output Port RTS Register (Table 10-24) 328384740dcSRalf Baechle * Register: DUART_OUT_PORT 329384740dcSRalf Baechle */ 330384740dcSRalf Baechle 331384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) 332384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 333384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 334384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 335384740dcSRalf Baechle #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) 336384740dcSRalf Baechle 337384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET(chan) \ 338384740dcSRalf Baechle (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 339384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR(chan) \ 340384740dcSRalf Baechle (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 341384740dcSRalf Baechle 342384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 343384740dcSRalf Baechle /* 344384740dcSRalf Baechle * Full Interrupt Control Register 345384740dcSRalf Baechle */ 346384740dcSRalf Baechle 347384740dcSRalf Baechle #define S_DUART_SIG_FULL _SB_MAKE64(0) 348384740dcSRalf Baechle #define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) 349384740dcSRalf Baechle #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) 350384740dcSRalf Baechle #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) 351384740dcSRalf Baechle 352384740dcSRalf Baechle #define S_DUART_INT_TIME _SB_MAKE64(4) 353384740dcSRalf Baechle #define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) 354384740dcSRalf Baechle #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) 355384740dcSRalf Baechle #define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) 356384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 357384740dcSRalf Baechle 358384740dcSRalf Baechle 359384740dcSRalf Baechle /* ********************************************************************** */ 360384740dcSRalf Baechle 361384740dcSRalf Baechle 362384740dcSRalf Baechle #endif 363