11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* ********************************************************************* 3384740dcSRalf Baechle * SB1250 Board Support Package 4384740dcSRalf Baechle * 5384740dcSRalf Baechle * UART Constants File: sb1250_uart.h 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * This module contains constants and macros useful for 8384740dcSRalf Baechle * manipulating the SB1250's UARTs 9384740dcSRalf Baechle * 10384740dcSRalf Baechle * SB1250 specification level: User's manual 1/02/02 11384740dcSRalf Baechle * 12384740dcSRalf Baechle ********************************************************************* 13384740dcSRalf Baechle * 14384740dcSRalf Baechle * Copyright 2000,2001,2002,2003 15384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 16384740dcSRalf Baechle * 17384740dcSRalf Baechle ********************************************************************* */ 18384740dcSRalf Baechle 19384740dcSRalf Baechle 20384740dcSRalf Baechle #ifndef _SB1250_UART_H 21384740dcSRalf Baechle #define _SB1250_UART_H 22384740dcSRalf Baechle 23a1ce3928SDavid Howells #include <asm/sibyte/sb1250_defs.h> 24384740dcSRalf Baechle 25384740dcSRalf Baechle /* ********************************************************************** 26384740dcSRalf Baechle * DUART Registers 27384740dcSRalf Baechle ********************************************************************** */ 28384740dcSRalf Baechle 29384740dcSRalf Baechle /* 30384740dcSRalf Baechle * DUART Mode Register #1 (Table 10-3) 31384740dcSRalf Baechle * Register: DUART_MODE_REG_1_A 32384740dcSRalf Baechle * Register: DUART_MODE_REG_1_B 33384740dcSRalf Baechle */ 34384740dcSRalf Baechle 35384740dcSRalf Baechle #define S_DUART_BITS_PER_CHAR 0 36384740dcSRalf Baechle #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) 37384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) 38384740dcSRalf Baechle 39384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_RSV0 0 40384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_RSV1 1 41384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_7 2 42384740dcSRalf Baechle #define K_DUART_BITS_PER_CHAR_8 3 43384740dcSRalf Baechle 44384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) 45384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) 46384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) 47384740dcSRalf Baechle #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) 48384740dcSRalf Baechle 49384740dcSRalf Baechle 50384740dcSRalf Baechle #define M_DUART_PARITY_TYPE_EVEN 0x00 51384740dcSRalf Baechle #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 52384740dcSRalf Baechle 53384740dcSRalf Baechle #define S_DUART_PARITY_MODE 3 54384740dcSRalf Baechle #define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) 55384740dcSRalf Baechle #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define K_DUART_PARITY_MODE_ADD 0 58384740dcSRalf Baechle #define K_DUART_PARITY_MODE_ADD_FIXED 1 59384740dcSRalf Baechle #define K_DUART_PARITY_MODE_NONE 2 60384740dcSRalf Baechle 61384740dcSRalf Baechle #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) 62384740dcSRalf Baechle #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) 63384740dcSRalf Baechle #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) 64384740dcSRalf Baechle 65384740dcSRalf Baechle #define M_DUART_TX_IRQ_SEL_TXRDY 0 66384740dcSRalf Baechle #define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) 67384740dcSRalf Baechle 68384740dcSRalf Baechle #define M_DUART_RX_IRQ_SEL_RXRDY 0 69384740dcSRalf Baechle #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) 70384740dcSRalf Baechle 71384740dcSRalf Baechle #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) 72384740dcSRalf Baechle 73384740dcSRalf Baechle /* 74384740dcSRalf Baechle * DUART Mode Register #2 (Table 10-4) 75384740dcSRalf Baechle * Register: DUART_MODE_REG_2_A 76384740dcSRalf Baechle * Register: DUART_MODE_REG_2_B 77384740dcSRalf Baechle */ 78384740dcSRalf Baechle 79384740dcSRalf Baechle #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ 80384740dcSRalf Baechle 81384740dcSRalf Baechle #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 82384740dcSRalf Baechle #define M_DUART_STOP_BIT_LEN_1 0 83384740dcSRalf Baechle 84384740dcSRalf Baechle #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) 85384740dcSRalf Baechle 86384740dcSRalf Baechle 87384740dcSRalf Baechle #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 88384740dcSRalf Baechle 89384740dcSRalf Baechle #define S_DUART_CHAN_MODE 6 90384740dcSRalf Baechle #define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) 91384740dcSRalf Baechle #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) 92384740dcSRalf Baechle 93384740dcSRalf Baechle #define K_DUART_CHAN_MODE_NORMAL 0 94384740dcSRalf Baechle #define K_DUART_CHAN_MODE_LCL_LOOP 2 95384740dcSRalf Baechle #define K_DUART_CHAN_MODE_REM_LOOP 3 96384740dcSRalf Baechle 97384740dcSRalf Baechle #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) 98384740dcSRalf Baechle #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) 99384740dcSRalf Baechle #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) 100384740dcSRalf Baechle 101384740dcSRalf Baechle /* 102384740dcSRalf Baechle * DUART Command Register (Table 10-5) 103384740dcSRalf Baechle * Register: DUART_CMD_A 104384740dcSRalf Baechle * Register: DUART_CMD_B 105384740dcSRalf Baechle */ 106384740dcSRalf Baechle 107384740dcSRalf Baechle #define M_DUART_RX_EN _SB_MAKEMASK1(0) 108384740dcSRalf Baechle #define M_DUART_RX_DIS _SB_MAKEMASK1(1) 109384740dcSRalf Baechle #define M_DUART_TX_EN _SB_MAKEMASK1(2) 110384740dcSRalf Baechle #define M_DUART_TX_DIS _SB_MAKEMASK1(3) 111384740dcSRalf Baechle 112384740dcSRalf Baechle #define S_DUART_MISC_CMD 4 113384740dcSRalf Baechle #define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) 114384740dcSRalf Baechle #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) 115384740dcSRalf Baechle 116384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION0 0 117384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION1 1 118384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_RX 2 119384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_TX 3 120384740dcSRalf Baechle #define K_DUART_MISC_CMD_NOACTION4 4 121384740dcSRalf Baechle #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 122384740dcSRalf Baechle #define K_DUART_MISC_CMD_START_BREAK 6 123384740dcSRalf Baechle #define K_DUART_MISC_CMD_STOP_BREAK 7 124384740dcSRalf Baechle 125384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) 126384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) 127384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) 128384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) 129384740dcSRalf Baechle #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) 130384740dcSRalf Baechle #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) 131384740dcSRalf Baechle #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 132384740dcSRalf Baechle #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 133384740dcSRalf Baechle 134384740dcSRalf Baechle #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 135384740dcSRalf Baechle 136384740dcSRalf Baechle /* 137384740dcSRalf Baechle * DUART Status Register (Table 10-6) 138384740dcSRalf Baechle * Register: DUART_STATUS_A 139384740dcSRalf Baechle * Register: DUART_STATUS_B 140384740dcSRalf Baechle * READ-ONLY 141384740dcSRalf Baechle */ 142384740dcSRalf Baechle 143384740dcSRalf Baechle #define M_DUART_RX_RDY _SB_MAKEMASK1(0) 144384740dcSRalf Baechle #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) 145384740dcSRalf Baechle #define M_DUART_TX_RDY _SB_MAKEMASK1(2) 146384740dcSRalf Baechle #define M_DUART_TX_EMT _SB_MAKEMASK1(3) 147384740dcSRalf Baechle #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) 148384740dcSRalf Baechle #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) 149384740dcSRalf Baechle #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) 150384740dcSRalf Baechle #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) 151384740dcSRalf Baechle 152384740dcSRalf Baechle /* 153384740dcSRalf Baechle * DUART Baud Rate Register (Table 10-7) 154384740dcSRalf Baechle * Register: DUART_CLK_SEL_A 155384740dcSRalf Baechle * Register: DUART_CLK_SEL_B 156384740dcSRalf Baechle */ 157384740dcSRalf Baechle 158384740dcSRalf Baechle #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) 159384740dcSRalf Baechle #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 160384740dcSRalf Baechle 161384740dcSRalf Baechle /* 162384740dcSRalf Baechle * DUART Data Registers (Table 10-8 and 10-9) 163384740dcSRalf Baechle * Register: DUART_RX_HOLD_A 164384740dcSRalf Baechle * Register: DUART_RX_HOLD_B 165384740dcSRalf Baechle * Register: DUART_TX_HOLD_A 166384740dcSRalf Baechle * Register: DUART_TX_HOLD_B 167384740dcSRalf Baechle */ 168384740dcSRalf Baechle 169384740dcSRalf Baechle #define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) 170384740dcSRalf Baechle #define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) 171384740dcSRalf Baechle 172384740dcSRalf Baechle /* 173384740dcSRalf Baechle * DUART Input Port Register (Table 10-10) 174384740dcSRalf Baechle * Register: DUART_IN_PORT 175384740dcSRalf Baechle */ 176384740dcSRalf Baechle 177384740dcSRalf Baechle #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) 178384740dcSRalf Baechle #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) 179384740dcSRalf Baechle #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) 180384740dcSRalf Baechle #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) 181384740dcSRalf Baechle #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) 182384740dcSRalf Baechle #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) 183384740dcSRalf Baechle #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) 184384740dcSRalf Baechle #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) 185384740dcSRalf Baechle 186384740dcSRalf Baechle /* 187384740dcSRalf Baechle * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) 188384740dcSRalf Baechle * Register: DUART_INPORT_CHNG 189384740dcSRalf Baechle */ 190384740dcSRalf Baechle 191384740dcSRalf Baechle #define S_DUART_IN_PIN_VAL 0 192384740dcSRalf Baechle #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) 193384740dcSRalf Baechle 194384740dcSRalf Baechle #define S_DUART_IN_PIN_CHNG 4 195384740dcSRalf Baechle #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) 196384740dcSRalf Baechle 197384740dcSRalf Baechle 198384740dcSRalf Baechle /* 199384740dcSRalf Baechle * DUART Output port control register (Table 10-14) 200384740dcSRalf Baechle * Register: DUART_OPCR 201384740dcSRalf Baechle */ 202384740dcSRalf Baechle 203384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ 204384740dcSRalf Baechle #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 205384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 206384740dcSRalf Baechle #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 207384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ 208384740dcSRalf Baechle 209384740dcSRalf Baechle /* 210384740dcSRalf Baechle * DUART Aux Control Register (Table 10-15) 211384740dcSRalf Baechle * Register: DUART_AUX_CTRL 212384740dcSRalf Baechle */ 213384740dcSRalf Baechle 214384740dcSRalf Baechle #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) 215384740dcSRalf Baechle #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 216384740dcSRalf Baechle #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 217384740dcSRalf Baechle #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 218384740dcSRalf Baechle #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) 219384740dcSRalf Baechle 220384740dcSRalf Baechle #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 221384740dcSRalf Baechle #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 222384740dcSRalf Baechle 223384740dcSRalf Baechle /* 224384740dcSRalf Baechle * DUART Interrupt Status Register (Table 10-16) 225384740dcSRalf Baechle * Register: DUART_ISR 226384740dcSRalf Baechle */ 227384740dcSRalf Baechle 228384740dcSRalf Baechle #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 229384740dcSRalf Baechle 230384740dcSRalf Baechle #define S_DUART_ISR_RX_A 1 231384740dcSRalf Baechle #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) 232384740dcSRalf Baechle #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) 233384740dcSRalf Baechle #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) 234384740dcSRalf Baechle 235384740dcSRalf Baechle #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 236384740dcSRalf Baechle #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 237384740dcSRalf Baechle #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) 238384740dcSRalf Baechle 239384740dcSRalf Baechle #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 240384740dcSRalf Baechle #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 241384740dcSRalf Baechle #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 242384740dcSRalf Baechle #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 243384740dcSRalf Baechle #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) 244384740dcSRalf Baechle 245384740dcSRalf Baechle /* 246384740dcSRalf Baechle * DUART Channel A Interrupt Status Register (Table 10-17) 247384740dcSRalf Baechle * DUART Channel B Interrupt Status Register (Table 10-18) 248384740dcSRalf Baechle * Register: DUART_ISR_A 249384740dcSRalf Baechle * Register: DUART_ISR_B 250384740dcSRalf Baechle */ 251384740dcSRalf Baechle 252384740dcSRalf Baechle #define M_DUART_ISR_TX _SB_MAKEMASK1(0) 253384740dcSRalf Baechle #define M_DUART_ISR_RX _SB_MAKEMASK1(1) 254384740dcSRalf Baechle #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 255384740dcSRalf Baechle #define M_DUART_ISR_IN _SB_MAKEMASK1(3) 256384740dcSRalf Baechle #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) 257384740dcSRalf Baechle #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) 258384740dcSRalf Baechle 259384740dcSRalf Baechle /* 260384740dcSRalf Baechle * DUART Interrupt Mask Register (Table 10-19) 261384740dcSRalf Baechle * Register: DUART_IMR 262384740dcSRalf Baechle */ 263384740dcSRalf Baechle 264384740dcSRalf Baechle #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) 265384740dcSRalf Baechle #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 266384740dcSRalf Baechle #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 267384740dcSRalf Baechle #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 268384740dcSRalf Baechle #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) 269384740dcSRalf Baechle 270384740dcSRalf Baechle #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 271384740dcSRalf Baechle #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 272384740dcSRalf Baechle #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 273384740dcSRalf Baechle #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 274384740dcSRalf Baechle #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) 275384740dcSRalf Baechle 276384740dcSRalf Baechle /* 277384740dcSRalf Baechle * DUART Channel A Interrupt Mask Register (Table 10-20) 278384740dcSRalf Baechle * DUART Channel B Interrupt Mask Register (Table 10-21) 279384740dcSRalf Baechle * Register: DUART_IMR_A 280384740dcSRalf Baechle * Register: DUART_IMR_B 281384740dcSRalf Baechle */ 282384740dcSRalf Baechle 283384740dcSRalf Baechle #define M_DUART_IMR_TX _SB_MAKEMASK1(0) 284384740dcSRalf Baechle #define M_DUART_IMR_RX _SB_MAKEMASK1(1) 285384740dcSRalf Baechle #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 286384740dcSRalf Baechle #define M_DUART_IMR_IN _SB_MAKEMASK1(3) 287384740dcSRalf Baechle #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) 288384740dcSRalf Baechle #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) 289384740dcSRalf Baechle 290384740dcSRalf Baechle 291384740dcSRalf Baechle /* 292384740dcSRalf Baechle * DUART Output Port Set Register (Table 10-22) 293384740dcSRalf Baechle * Register: DUART_SET_OPR 294384740dcSRalf Baechle */ 295384740dcSRalf Baechle 296384740dcSRalf Baechle #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) 297384740dcSRalf Baechle #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 298384740dcSRalf Baechle #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 299384740dcSRalf Baechle #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 300384740dcSRalf Baechle #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) 301384740dcSRalf Baechle 302384740dcSRalf Baechle /* 303384740dcSRalf Baechle * DUART Output Port Clear Register (Table 10-23) 304384740dcSRalf Baechle * Register: DUART_CLEAR_OPR 305384740dcSRalf Baechle */ 306384740dcSRalf Baechle 307384740dcSRalf Baechle #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) 308384740dcSRalf Baechle #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 309384740dcSRalf Baechle #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 310384740dcSRalf Baechle #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 311384740dcSRalf Baechle #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) 312384740dcSRalf Baechle 313384740dcSRalf Baechle /* 314384740dcSRalf Baechle * DUART Output Port RTS Register (Table 10-24) 315384740dcSRalf Baechle * Register: DUART_OUT_PORT 316384740dcSRalf Baechle */ 317384740dcSRalf Baechle 318384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) 319384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 320384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 321384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 322384740dcSRalf Baechle #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) 323384740dcSRalf Baechle 324384740dcSRalf Baechle #define M_DUART_OUT_PIN_SET(chan) \ 325384740dcSRalf Baechle (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 326384740dcSRalf Baechle #define M_DUART_OUT_PIN_CLR(chan) \ 327384740dcSRalf Baechle (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 328384740dcSRalf Baechle 329384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 330384740dcSRalf Baechle /* 331384740dcSRalf Baechle * Full Interrupt Control Register 332384740dcSRalf Baechle */ 333384740dcSRalf Baechle 334384740dcSRalf Baechle #define S_DUART_SIG_FULL _SB_MAKE64(0) 335384740dcSRalf Baechle #define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) 336384740dcSRalf Baechle #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) 337384740dcSRalf Baechle #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) 338384740dcSRalf Baechle 339384740dcSRalf Baechle #define S_DUART_INT_TIME _SB_MAKE64(4) 340384740dcSRalf Baechle #define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) 341384740dcSRalf Baechle #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) 342384740dcSRalf Baechle #define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) 343384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 344384740dcSRalf Baechle 345384740dcSRalf Baechle 346384740dcSRalf Baechle /* ********************************************************************** */ 347384740dcSRalf Baechle 348384740dcSRalf Baechle 349384740dcSRalf Baechle #endif 350