1384740dcSRalf Baechle /* ********************************************************************* 2384740dcSRalf Baechle * SB1250 Board Support Package 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * SCD Constants and Macros File: sb1250_scd.h 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * This module contains constants and macros useful for 7384740dcSRalf Baechle * manipulating the System Control and Debug module on the 1250. 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * SB1250 specification level: User's manual 1/02/02 10384740dcSRalf Baechle * 11384740dcSRalf Baechle ********************************************************************* 12384740dcSRalf Baechle * 13384740dcSRalf Baechle * Copyright 2000,2001,2002,2003,2004,2005 14384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 15384740dcSRalf Baechle * 16384740dcSRalf Baechle * This program is free software; you can redistribute it and/or 17384740dcSRalf Baechle * modify it under the terms of the GNU General Public License as 18384740dcSRalf Baechle * published by the Free Software Foundation; either version 2 of 19384740dcSRalf Baechle * the License, or (at your option) any later version. 20384740dcSRalf Baechle * 21384740dcSRalf Baechle * This program is distributed in the hope that it will be useful, 22384740dcSRalf Baechle * but WITHOUT ANY WARRANTY; without even the implied warranty of 23384740dcSRalf Baechle * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24384740dcSRalf Baechle * GNU General Public License for more details. 25384740dcSRalf Baechle * 26384740dcSRalf Baechle * You should have received a copy of the GNU General Public License 27384740dcSRalf Baechle * along with this program; if not, write to the Free Software 28384740dcSRalf Baechle * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29384740dcSRalf Baechle * MA 02111-1307 USA 30384740dcSRalf Baechle ********************************************************************* */ 31384740dcSRalf Baechle 32384740dcSRalf Baechle #ifndef _SB1250_SCD_H 33384740dcSRalf Baechle #define _SB1250_SCD_H 34384740dcSRalf Baechle 35a1ce3928SDavid Howells #include <asm/sibyte/sb1250_defs.h> 36384740dcSRalf Baechle 37384740dcSRalf Baechle /* ********************************************************************* 38384740dcSRalf Baechle * System control/debug registers 39384740dcSRalf Baechle ********************************************************************* */ 40384740dcSRalf Baechle 41384740dcSRalf Baechle /* 42384740dcSRalf Baechle * System Revision Register (Table 4-1) 43384740dcSRalf Baechle */ 44384740dcSRalf Baechle 45384740dcSRalf Baechle #define M_SYS_RESERVED _SB_MAKEMASK(8, 0) 46384740dcSRalf Baechle 47384740dcSRalf Baechle #define S_SYS_REVISION _SB_MAKE64(8) 48384740dcSRalf Baechle #define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) 49384740dcSRalf Baechle #define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) 50384740dcSRalf Baechle #define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) 51384740dcSRalf Baechle 52384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_PASS1 0x01 53384740dcSRalf Baechle 54384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_PASS2 0x03 55384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ 56384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ 57384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ 58384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ 59384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ 60384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ 61384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A9 0x08 62384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 63384740dcSRalf Baechle 64384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 65384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 66384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_B1 0x10 67384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_B2 0x11 68384740dcSRalf Baechle 69384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_C0 0x20 70384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_C1 0x21 71384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_C2 0x22 72384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_C3 0x23 73384740dcSRalf Baechle 74384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1250) 75384740dcSRalf Baechle /* XXX: discourage people from using these constants. */ 76384740dcSRalf Baechle #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 77384740dcSRalf Baechle #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 78384740dcSRalf Baechle #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 79384740dcSRalf Baechle #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 80384740dcSRalf Baechle #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 81384740dcSRalf Baechle #endif /* 1250 */ 82384740dcSRalf Baechle 83384740dcSRalf Baechle #define K_SYS_REVISION_BCM112x_A1 0x20 84384740dcSRalf Baechle #define K_SYS_REVISION_BCM112x_A2 0x21 85384740dcSRalf Baechle #define K_SYS_REVISION_BCM112x_A3 0x22 86384740dcSRalf Baechle #define K_SYS_REVISION_BCM112x_A4 0x23 87384740dcSRalf Baechle #define K_SYS_REVISION_BCM112x_B0 0x30 88384740dcSRalf Baechle 89384740dcSRalf Baechle #define K_SYS_REVISION_BCM1480_S0 0x01 90384740dcSRalf Baechle #define K_SYS_REVISION_BCM1480_A1 0x02 91384740dcSRalf Baechle #define K_SYS_REVISION_BCM1480_A2 0x03 92384740dcSRalf Baechle #define K_SYS_REVISION_BCM1480_A3 0x04 93384740dcSRalf Baechle #define K_SYS_REVISION_BCM1480_B0 0x11 94384740dcSRalf Baechle 95384740dcSRalf Baechle /*Cache size - 23:20 of revision register*/ 96384740dcSRalf Baechle #define S_SYS_L2C_SIZE _SB_MAKE64(20) 97384740dcSRalf Baechle #define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) 98384740dcSRalf Baechle #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) 99384740dcSRalf Baechle #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) 100384740dcSRalf Baechle 101384740dcSRalf Baechle #define K_SYS_L2C_SIZE_1MB 0 102384740dcSRalf Baechle #define K_SYS_L2C_SIZE_512KB 5 103384740dcSRalf Baechle #define K_SYS_L2C_SIZE_256KB 2 104384740dcSRalf Baechle #define K_SYS_L2C_SIZE_128KB 1 105384740dcSRalf Baechle 106384740dcSRalf Baechle #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB 107384740dcSRalf Baechle #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB 108384740dcSRalf Baechle #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB 109384740dcSRalf Baechle 110384740dcSRalf Baechle 111384740dcSRalf Baechle /* Number of CPU cores, bits 27:24 of revision register*/ 112384740dcSRalf Baechle #define S_SYS_NUM_CPUS _SB_MAKE64(24) 113384740dcSRalf Baechle #define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) 114384740dcSRalf Baechle #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) 115384740dcSRalf Baechle #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) 116384740dcSRalf Baechle 117384740dcSRalf Baechle 118384740dcSRalf Baechle /* XXX: discourage people from using these constants. */ 119384740dcSRalf Baechle #define S_SYS_PART _SB_MAKE64(16) 120384740dcSRalf Baechle #define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) 121384740dcSRalf Baechle #define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) 122384740dcSRalf Baechle #define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) 123384740dcSRalf Baechle 124384740dcSRalf Baechle /* XXX: discourage people from using these constants. */ 125384740dcSRalf Baechle #define K_SYS_PART_SB1250 0x1250 126384740dcSRalf Baechle #define K_SYS_PART_BCM1120 0x1121 127384740dcSRalf Baechle #define K_SYS_PART_BCM1125 0x1123 128384740dcSRalf Baechle #define K_SYS_PART_BCM1125H 0x1124 129384740dcSRalf Baechle #define K_SYS_PART_BCM1122 0x1113 130384740dcSRalf Baechle 131384740dcSRalf Baechle 132384740dcSRalf Baechle /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 133384740dcSRalf Baechle #define S_SYS_SOC_TYPE _SB_MAKE64(16) 134384740dcSRalf Baechle #define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) 135384740dcSRalf Baechle #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) 136384740dcSRalf Baechle #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) 137384740dcSRalf Baechle 138384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1250 0x0 139384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1120 0x1 140384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 141384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1125 0x3 142384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1125H 0x4 143384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 144384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1x80 0x6 145384740dcSRalf Baechle #define K_SYS_SOC_TYPE_BCM1x55 0x7 146384740dcSRalf Baechle 147384740dcSRalf Baechle /* 148384740dcSRalf Baechle * Calculate correct SOC type given a copy of system revision register. 149384740dcSRalf Baechle * 150384740dcSRalf Baechle * (For the assembler version, sysrev and dest may be the same register. 151384740dcSRalf Baechle * Also, it clobbers AT.) 152384740dcSRalf Baechle */ 153384740dcSRalf Baechle #ifdef __ASSEMBLER__ 154384740dcSRalf Baechle #define SYS_SOC_TYPE(dest, sysrev) \ 155384740dcSRalf Baechle .set push ; \ 156384740dcSRalf Baechle .set reorder ; \ 157384740dcSRalf Baechle dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 158384740dcSRalf Baechle andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 159384740dcSRalf Baechle beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 160384740dcSRalf Baechle beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 161384740dcSRalf Baechle b 992f ; \ 162384740dcSRalf Baechle 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 163384740dcSRalf Baechle 992: \ 164384740dcSRalf Baechle .set pop 165384740dcSRalf Baechle #else 166384740dcSRalf Baechle #define SYS_SOC_TYPE(sysrev) \ 167384740dcSRalf Baechle ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 168384740dcSRalf Baechle || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 169384740dcSRalf Baechle ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 170384740dcSRalf Baechle #endif 171384740dcSRalf Baechle 172384740dcSRalf Baechle #define S_SYS_WID _SB_MAKE64(32) 173384740dcSRalf Baechle #define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) 174384740dcSRalf Baechle #define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) 175384740dcSRalf Baechle #define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) 176384740dcSRalf Baechle 177384740dcSRalf Baechle /* 178384740dcSRalf Baechle * System Manufacturing Register 179384740dcSRalf Baechle * Register: SCD_SYSTEM_MANUF 180384740dcSRalf Baechle */ 181384740dcSRalf Baechle 182384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 183384740dcSRalf Baechle /* Wafer ID: bits 31:0 */ 184384740dcSRalf Baechle #define S_SYS_WAFERID1_200 _SB_MAKE64(0) 185384740dcSRalf Baechle #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) 186384740dcSRalf Baechle #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) 187384740dcSRalf Baechle #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) 188384740dcSRalf Baechle 189384740dcSRalf Baechle #define S_SYS_BIN _SB_MAKE64(32) 190384740dcSRalf Baechle #define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) 191384740dcSRalf Baechle #define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) 192384740dcSRalf Baechle #define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) 193384740dcSRalf Baechle 194384740dcSRalf Baechle /* Wafer ID: bits 39:36 */ 195384740dcSRalf Baechle #define S_SYS_WAFERID2_200 _SB_MAKE64(36) 196384740dcSRalf Baechle #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) 197384740dcSRalf Baechle #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) 198384740dcSRalf Baechle #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) 199384740dcSRalf Baechle 200384740dcSRalf Baechle /* Wafer ID: bits 39:0 */ 201384740dcSRalf Baechle #define S_SYS_WAFERID_300 _SB_MAKE64(0) 202384740dcSRalf Baechle #define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) 203384740dcSRalf Baechle #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) 204384740dcSRalf Baechle #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) 205384740dcSRalf Baechle 206384740dcSRalf Baechle #define S_SYS_XPOS _SB_MAKE64(40) 207384740dcSRalf Baechle #define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) 208384740dcSRalf Baechle #define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) 209384740dcSRalf Baechle #define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) 210384740dcSRalf Baechle 211384740dcSRalf Baechle #define S_SYS_YPOS _SB_MAKE64(46) 212384740dcSRalf Baechle #define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) 213384740dcSRalf Baechle #define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) 214384740dcSRalf Baechle #define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) 215384740dcSRalf Baechle #endif 216384740dcSRalf Baechle 217384740dcSRalf Baechle 218384740dcSRalf Baechle /* 219384740dcSRalf Baechle * System Config Register (Table 4-2) 220384740dcSRalf Baechle * Register: SCD_SYSTEM_CFG 221384740dcSRalf Baechle */ 222384740dcSRalf Baechle 223384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 224384740dcSRalf Baechle #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 225384740dcSRalf Baechle #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 226384740dcSRalf Baechle #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 227384740dcSRalf Baechle #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 228384740dcSRalf Baechle 229384740dcSRalf Baechle #define S_SYS_PLL_DIV _SB_MAKE64(7) 230384740dcSRalf Baechle #define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) 231384740dcSRalf Baechle #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) 232384740dcSRalf Baechle #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) 233384740dcSRalf Baechle 234384740dcSRalf Baechle #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 235384740dcSRalf Baechle #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 236384740dcSRalf Baechle #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 237384740dcSRalf Baechle #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 238384740dcSRalf Baechle #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 239384740dcSRalf Baechle 240384740dcSRalf Baechle #define S_SYS_BOOT_MODE _SB_MAKE64(17) 241384740dcSRalf Baechle #define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) 242384740dcSRalf Baechle #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) 243384740dcSRalf Baechle #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) 244384740dcSRalf Baechle #define K_SYS_BOOT_MODE_ROM32 0 245384740dcSRalf Baechle #define K_SYS_BOOT_MODE_ROM8 1 246384740dcSRalf Baechle #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 247384740dcSRalf Baechle #define K_SYS_BOOT_MODE_SMBUS_BIG 3 248384740dcSRalf Baechle 249384740dcSRalf Baechle #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 250384740dcSRalf Baechle #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 251384740dcSRalf Baechle #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 252384740dcSRalf Baechle #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 253384740dcSRalf Baechle #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 254384740dcSRalf Baechle #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 255384740dcSRalf Baechle #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 256384740dcSRalf Baechle 257384740dcSRalf Baechle #define S_SYS_CONFIG 26 258384740dcSRalf Baechle #define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) 259384740dcSRalf Baechle #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) 260384740dcSRalf Baechle #define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) 261384740dcSRalf Baechle 262384740dcSRalf Baechle /* The following bits are writeable by JTAG only. */ 263384740dcSRalf Baechle 264384740dcSRalf Baechle #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 265384740dcSRalf Baechle #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 266384740dcSRalf Baechle 267384740dcSRalf Baechle #define S_SYS_CLKCOUNT 34 268384740dcSRalf Baechle #define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) 269384740dcSRalf Baechle #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) 270384740dcSRalf Baechle #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) 271384740dcSRalf Baechle 272384740dcSRalf Baechle #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 273384740dcSRalf Baechle 274384740dcSRalf Baechle #define S_SYS_PLL_IREF 43 275384740dcSRalf Baechle #define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) 276384740dcSRalf Baechle 277384740dcSRalf Baechle #define S_SYS_PLL_VCO 45 278384740dcSRalf Baechle #define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) 279384740dcSRalf Baechle 280384740dcSRalf Baechle #define S_SYS_PLL_VREG 47 281384740dcSRalf Baechle #define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) 282384740dcSRalf Baechle 283384740dcSRalf Baechle #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 284384740dcSRalf Baechle #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 285384740dcSRalf Baechle #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 286384740dcSRalf Baechle #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 287384740dcSRalf Baechle #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 288384740dcSRalf Baechle 289384740dcSRalf Baechle /* End of bits writable by JTAG only. */ 290384740dcSRalf Baechle 291384740dcSRalf Baechle #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 292384740dcSRalf Baechle #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 293384740dcSRalf Baechle 294384740dcSRalf Baechle #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 295384740dcSRalf Baechle #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 296384740dcSRalf Baechle 297384740dcSRalf Baechle #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 298384740dcSRalf Baechle #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 299384740dcSRalf Baechle #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 300384740dcSRalf Baechle 301384740dcSRalf Baechle #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 302384740dcSRalf Baechle #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 303384740dcSRalf Baechle 304384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 305384740dcSRalf Baechle #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 306384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 */ 307384740dcSRalf Baechle 308384740dcSRalf Baechle #endif 309384740dcSRalf Baechle 310384740dcSRalf Baechle 311384740dcSRalf Baechle /* 312384740dcSRalf Baechle * Mailbox Registers (Table 4-3) 313384740dcSRalf Baechle * Registers: SCD_MBOX_CPU_x 314384740dcSRalf Baechle */ 315384740dcSRalf Baechle 316384740dcSRalf Baechle #define S_MBOX_INT_3 0 317384740dcSRalf Baechle #define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) 318384740dcSRalf Baechle #define S_MBOX_INT_2 16 319384740dcSRalf Baechle #define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) 320384740dcSRalf Baechle #define S_MBOX_INT_1 32 321384740dcSRalf Baechle #define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) 322384740dcSRalf Baechle #define S_MBOX_INT_0 48 323384740dcSRalf Baechle #define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) 324384740dcSRalf Baechle 325384740dcSRalf Baechle /* 326384740dcSRalf Baechle * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 327384740dcSRalf Baechle * Registers: SCD_WDOG_INIT_CNT_x 328384740dcSRalf Baechle */ 329384740dcSRalf Baechle 330384740dcSRalf Baechle #define V_SCD_WDOG_FREQ 1000000 331384740dcSRalf Baechle 332384740dcSRalf Baechle #define S_SCD_WDOG_INIT 0 333384740dcSRalf Baechle #define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) 334384740dcSRalf Baechle 335384740dcSRalf Baechle #define S_SCD_WDOG_CNT 0 336384740dcSRalf Baechle #define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) 337384740dcSRalf Baechle 338384740dcSRalf Baechle #define S_SCD_WDOG_ENABLE 0 339384740dcSRalf Baechle #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 340384740dcSRalf Baechle 341384740dcSRalf Baechle #define S_SCD_WDOG_RESET_TYPE 2 342384740dcSRalf Baechle #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) 343384740dcSRalf Baechle #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) 344384740dcSRalf Baechle #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) 345384740dcSRalf Baechle 346384740dcSRalf Baechle #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 347384740dcSRalf Baechle #define K_SCD_WDOG_RESET_SOFT 1 348384740dcSRalf Baechle #define K_SCD_WDOG_RESET_CPU0 3 349384740dcSRalf Baechle #define K_SCD_WDOG_RESET_CPU1 5 350384740dcSRalf Baechle #define K_SCD_WDOG_RESET_BOTH_CPUS 7 351384740dcSRalf Baechle 352384740dcSRalf Baechle /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ 353384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) 354384740dcSRalf Baechle #define S_SCD_WDOG_HAS_RESET 8 355384740dcSRalf Baechle #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) 356384740dcSRalf Baechle #endif 357384740dcSRalf Baechle 358384740dcSRalf Baechle 359384740dcSRalf Baechle /* 360384740dcSRalf Baechle * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 361384740dcSRalf Baechle */ 362384740dcSRalf Baechle 363384740dcSRalf Baechle #define V_SCD_TIMER_FREQ 1000000 364384740dcSRalf Baechle 365384740dcSRalf Baechle #define S_SCD_TIMER_INIT 0 366384740dcSRalf Baechle #define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) 367384740dcSRalf Baechle #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) 368384740dcSRalf Baechle #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) 369384740dcSRalf Baechle 370384740dcSRalf Baechle #define V_SCD_TIMER_WIDTH 23 371384740dcSRalf Baechle #define S_SCD_TIMER_CNT 0 372384740dcSRalf Baechle #define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) 373384740dcSRalf Baechle #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) 374384740dcSRalf Baechle #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) 375384740dcSRalf Baechle 376384740dcSRalf Baechle #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 377384740dcSRalf Baechle #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 378384740dcSRalf Baechle #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 379384740dcSRalf Baechle 380384740dcSRalf Baechle /* 381384740dcSRalf Baechle * System Performance Counters 382384740dcSRalf Baechle */ 383384740dcSRalf Baechle 384384740dcSRalf Baechle #define S_SPC_CFG_SRC0 0 385384740dcSRalf Baechle #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) 386384740dcSRalf Baechle #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) 387384740dcSRalf Baechle #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) 388384740dcSRalf Baechle 389384740dcSRalf Baechle #define S_SPC_CFG_SRC1 8 390384740dcSRalf Baechle #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) 391384740dcSRalf Baechle #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) 392384740dcSRalf Baechle #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) 393384740dcSRalf Baechle 394384740dcSRalf Baechle #define S_SPC_CFG_SRC2 16 395384740dcSRalf Baechle #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) 396384740dcSRalf Baechle #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) 397384740dcSRalf Baechle #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) 398384740dcSRalf Baechle 399384740dcSRalf Baechle #define S_SPC_CFG_SRC3 24 400384740dcSRalf Baechle #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) 401384740dcSRalf Baechle #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) 402384740dcSRalf Baechle #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) 403384740dcSRalf Baechle 404384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 405384740dcSRalf Baechle #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 406384740dcSRalf Baechle #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 407384740dcSRalf Baechle #endif 408384740dcSRalf Baechle 409384740dcSRalf Baechle 410384740dcSRalf Baechle /* 411384740dcSRalf Baechle * Bus Watcher 412384740dcSRalf Baechle */ 413384740dcSRalf Baechle 414384740dcSRalf Baechle #define S_SCD_BERR_TID 8 415384740dcSRalf Baechle #define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) 416384740dcSRalf Baechle #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) 417384740dcSRalf Baechle #define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) 418384740dcSRalf Baechle 419384740dcSRalf Baechle #define S_SCD_BERR_RID 18 420384740dcSRalf Baechle #define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) 421384740dcSRalf Baechle #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) 422384740dcSRalf Baechle #define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) 423384740dcSRalf Baechle 424384740dcSRalf Baechle #define S_SCD_BERR_DCODE 22 425384740dcSRalf Baechle #define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) 426384740dcSRalf Baechle #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) 427384740dcSRalf Baechle #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) 428384740dcSRalf Baechle 429384740dcSRalf Baechle #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 430384740dcSRalf Baechle 431384740dcSRalf Baechle 432384740dcSRalf Baechle #define S_SCD_L2ECC_CORR_D 0 433384740dcSRalf Baechle #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) 434384740dcSRalf Baechle #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) 435384740dcSRalf Baechle #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) 436384740dcSRalf Baechle 437384740dcSRalf Baechle #define S_SCD_L2ECC_BAD_D 8 438384740dcSRalf Baechle #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) 439384740dcSRalf Baechle #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) 440384740dcSRalf Baechle #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) 441384740dcSRalf Baechle 442384740dcSRalf Baechle #define S_SCD_L2ECC_CORR_T 16 443384740dcSRalf Baechle #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) 444384740dcSRalf Baechle #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) 445384740dcSRalf Baechle #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) 446384740dcSRalf Baechle 447384740dcSRalf Baechle #define S_SCD_L2ECC_BAD_T 24 448384740dcSRalf Baechle #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) 449384740dcSRalf Baechle #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) 450384740dcSRalf Baechle #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) 451384740dcSRalf Baechle 452384740dcSRalf Baechle #define S_SCD_MEM_ECC_CORR 0 453384740dcSRalf Baechle #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) 454384740dcSRalf Baechle #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) 455384740dcSRalf Baechle #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) 456384740dcSRalf Baechle 457384740dcSRalf Baechle #define S_SCD_MEM_ECC_BAD 8 458384740dcSRalf Baechle #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) 459384740dcSRalf Baechle #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) 460384740dcSRalf Baechle #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) 461384740dcSRalf Baechle 462384740dcSRalf Baechle #define S_SCD_MEM_BUSERR 16 463384740dcSRalf Baechle #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) 464384740dcSRalf Baechle #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) 465384740dcSRalf Baechle #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) 466384740dcSRalf Baechle 467384740dcSRalf Baechle 468384740dcSRalf Baechle /* 469384740dcSRalf Baechle * Address Trap Registers 470384740dcSRalf Baechle */ 471384740dcSRalf Baechle 472384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 473384740dcSRalf Baechle #define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) 474384740dcSRalf Baechle #define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) 475384740dcSRalf Baechle 476384740dcSRalf Baechle #define S_ATRAP_CFG_CNT 0 477384740dcSRalf Baechle #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) 478384740dcSRalf Baechle #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) 479384740dcSRalf Baechle #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) 480384740dcSRalf Baechle 481384740dcSRalf Baechle #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 482384740dcSRalf Baechle #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 483384740dcSRalf Baechle #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 484384740dcSRalf Baechle #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 485384740dcSRalf Baechle #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 486384740dcSRalf Baechle 487384740dcSRalf Baechle #define S_ATRAP_CFG_AGENTID 8 488384740dcSRalf Baechle #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) 489384740dcSRalf Baechle #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) 490384740dcSRalf Baechle #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) 491384740dcSRalf Baechle 492384740dcSRalf Baechle #define K_BUS_AGENT_CPU0 0 493384740dcSRalf Baechle #define K_BUS_AGENT_CPU1 1 494384740dcSRalf Baechle #define K_BUS_AGENT_IOB0 2 495384740dcSRalf Baechle #define K_BUS_AGENT_IOB1 3 496384740dcSRalf Baechle #define K_BUS_AGENT_SCD 4 497384740dcSRalf Baechle #define K_BUS_AGENT_L2C 6 498384740dcSRalf Baechle #define K_BUS_AGENT_MC 7 499384740dcSRalf Baechle 500384740dcSRalf Baechle #define S_ATRAP_CFG_CATTR 12 501384740dcSRalf Baechle #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) 502384740dcSRalf Baechle #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) 503384740dcSRalf Baechle #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) 504384740dcSRalf Baechle 505384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_IGNORE 0 506384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_UNC 1 507384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_CACHEABLE 2 508384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_NONCOH 3 509384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_COHERENT 4 510384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_NOTUNC 5 511384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 512384740dcSRalf Baechle #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 513384740dcSRalf Baechle 514384740dcSRalf Baechle #endif /* 1250/112x */ 515384740dcSRalf Baechle 516384740dcSRalf Baechle /* 517384740dcSRalf Baechle * Trace Buffer Config register 518384740dcSRalf Baechle */ 519384740dcSRalf Baechle 520384740dcSRalf Baechle #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 521384740dcSRalf Baechle #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 522384740dcSRalf Baechle #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 523384740dcSRalf Baechle #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 524384740dcSRalf Baechle #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 525384740dcSRalf Baechle #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 526384740dcSRalf Baechle #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 527384740dcSRalf Baechle #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 528384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 529384740dcSRalf Baechle #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 530384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 531384740dcSRalf Baechle 532384740dcSRalf Baechle /* 533384740dcSRalf Baechle * This field is the same on the 1250/112x and 1480, just located in 534384740dcSRalf Baechle * a slightly different place in the register. 535384740dcSRalf Baechle */ 536384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 537384740dcSRalf Baechle #define S_SCD_TRACE_CFG_CUR_ADDR 10 538384740dcSRalf Baechle #else 539384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1480) 540384740dcSRalf Baechle #define S_SCD_TRACE_CFG_CUR_ADDR 24 541384740dcSRalf Baechle #endif /* 1480 */ 542384740dcSRalf Baechle #endif /* 1250/112x */ 543384740dcSRalf Baechle 544384740dcSRalf Baechle #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) 545384740dcSRalf Baechle #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) 546384740dcSRalf Baechle #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) 547384740dcSRalf Baechle 548384740dcSRalf Baechle /* 549384740dcSRalf Baechle * Trace Event registers 550384740dcSRalf Baechle */ 551384740dcSRalf Baechle 552384740dcSRalf Baechle #define S_SCD_TREVT_ADDR_MATCH 0 553384740dcSRalf Baechle #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) 554384740dcSRalf Baechle #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) 555384740dcSRalf Baechle #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) 556384740dcSRalf Baechle 557384740dcSRalf Baechle #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 558384740dcSRalf Baechle #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 559384740dcSRalf Baechle #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 560384740dcSRalf Baechle #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 561384740dcSRalf Baechle #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 562384740dcSRalf Baechle #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 563384740dcSRalf Baechle #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 564384740dcSRalf Baechle 565384740dcSRalf Baechle #define S_SCD_TREVT_REQID 12 566384740dcSRalf Baechle #define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) 567384740dcSRalf Baechle #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) 568384740dcSRalf Baechle #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) 569384740dcSRalf Baechle 570384740dcSRalf Baechle #define S_SCD_TREVT_RESPID 16 571384740dcSRalf Baechle #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) 572384740dcSRalf Baechle #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) 573384740dcSRalf Baechle #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) 574384740dcSRalf Baechle 575384740dcSRalf Baechle #define S_SCD_TREVT_DATAID 20 576384740dcSRalf Baechle #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) 577384740dcSRalf Baechle #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) 578384740dcSRalf Baechle #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) 579384740dcSRalf Baechle 580384740dcSRalf Baechle #define S_SCD_TREVT_COUNT 24 581384740dcSRalf Baechle #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) 582384740dcSRalf Baechle #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) 583384740dcSRalf Baechle #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) 584384740dcSRalf Baechle 585384740dcSRalf Baechle /* 586384740dcSRalf Baechle * Trace Sequence registers 587384740dcSRalf Baechle */ 588384740dcSRalf Baechle 589384740dcSRalf Baechle #define S_SCD_TRSEQ_EVENT4 0 590384740dcSRalf Baechle #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) 591384740dcSRalf Baechle #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) 592384740dcSRalf Baechle #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) 593384740dcSRalf Baechle 594384740dcSRalf Baechle #define S_SCD_TRSEQ_EVENT3 4 595384740dcSRalf Baechle #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) 596384740dcSRalf Baechle #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) 597384740dcSRalf Baechle #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) 598384740dcSRalf Baechle 599384740dcSRalf Baechle #define S_SCD_TRSEQ_EVENT2 8 600384740dcSRalf Baechle #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) 601384740dcSRalf Baechle #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) 602384740dcSRalf Baechle #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) 603384740dcSRalf Baechle 604384740dcSRalf Baechle #define S_SCD_TRSEQ_EVENT1 12 605384740dcSRalf Baechle #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) 606384740dcSRalf Baechle #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) 607384740dcSRalf Baechle #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) 608384740dcSRalf Baechle 609384740dcSRalf Baechle #define K_SCD_TRSEQ_E0 0 610384740dcSRalf Baechle #define K_SCD_TRSEQ_E1 1 611384740dcSRalf Baechle #define K_SCD_TRSEQ_E2 2 612384740dcSRalf Baechle #define K_SCD_TRSEQ_E3 3 613384740dcSRalf Baechle #define K_SCD_TRSEQ_E0_E1 4 614384740dcSRalf Baechle #define K_SCD_TRSEQ_E1_E2 5 615384740dcSRalf Baechle #define K_SCD_TRSEQ_E2_E3 6 616384740dcSRalf Baechle #define K_SCD_TRSEQ_E0_E1_E2 7 617384740dcSRalf Baechle #define K_SCD_TRSEQ_E0_E1_E2_E3 8 618384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1 9 619384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1E2 10 620384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1E2E3 11 621384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1_E2 12 622384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1_E2E3 13 623384740dcSRalf Baechle #define K_SCD_TRSEQ_E0E1_E2_E3 14 624384740dcSRalf Baechle #define K_SCD_TRSEQ_IGNORED 15 625384740dcSRalf Baechle 626384740dcSRalf Baechle #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 627384740dcSRalf Baechle V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 628384740dcSRalf Baechle V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 629384740dcSRalf Baechle V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 630384740dcSRalf Baechle 631384740dcSRalf Baechle #define S_SCD_TRSEQ_FUNCTION 16 632384740dcSRalf Baechle #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) 633384740dcSRalf Baechle #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) 634384740dcSRalf Baechle #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) 635384740dcSRalf Baechle 636384740dcSRalf Baechle #define K_SCD_TRSEQ_FUNC_NOP 0 637384740dcSRalf Baechle #define K_SCD_TRSEQ_FUNC_START 1 638384740dcSRalf Baechle #define K_SCD_TRSEQ_FUNC_STOP 2 639384740dcSRalf Baechle #define K_SCD_TRSEQ_FUNC_FREEZE 3 640384740dcSRalf Baechle 641384740dcSRalf Baechle #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 642384740dcSRalf Baechle #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 643384740dcSRalf Baechle #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 644384740dcSRalf Baechle #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 645384740dcSRalf Baechle 646384740dcSRalf Baechle #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 647384740dcSRalf Baechle #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 648384740dcSRalf Baechle #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 649384740dcSRalf Baechle #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 650384740dcSRalf Baechle #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 651384740dcSRalf Baechle #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) 652384740dcSRalf Baechle #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) 653384740dcSRalf Baechle 654384740dcSRalf Baechle #endif 655