1384740dcSRalf Baechle /* ********************************************************************* 2384740dcSRalf Baechle * SB1250 Board Support Package 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * Register Definitions File: sb1250_regs.h 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * This module contains the addresses of the on-chip peripherals 7384740dcSRalf Baechle * on the SB1250. 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * SB1250 specification level: 01/02/2002 10384740dcSRalf Baechle * 11384740dcSRalf Baechle ********************************************************************* 12384740dcSRalf Baechle * 13384740dcSRalf Baechle * Copyright 2000,2001,2002,2003 14384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 15384740dcSRalf Baechle * 16384740dcSRalf Baechle * This program is free software; you can redistribute it and/or 17384740dcSRalf Baechle * modify it under the terms of the GNU General Public License as 18384740dcSRalf Baechle * published by the Free Software Foundation; either version 2 of 19384740dcSRalf Baechle * the License, or (at your option) any later version. 20384740dcSRalf Baechle * 21384740dcSRalf Baechle * This program is distributed in the hope that it will be useful, 22384740dcSRalf Baechle * but WITHOUT ANY WARRANTY; without even the implied warranty of 23384740dcSRalf Baechle * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24384740dcSRalf Baechle * GNU General Public License for more details. 25384740dcSRalf Baechle * 26384740dcSRalf Baechle * You should have received a copy of the GNU General Public License 27384740dcSRalf Baechle * along with this program; if not, write to the Free Software 28384740dcSRalf Baechle * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29384740dcSRalf Baechle * MA 02111-1307 USA 30384740dcSRalf Baechle ********************************************************************* */ 31384740dcSRalf Baechle 32384740dcSRalf Baechle 33384740dcSRalf Baechle #ifndef _SB1250_REGS_H 34384740dcSRalf Baechle #define _SB1250_REGS_H 35384740dcSRalf Baechle 36a1ce3928SDavid Howells #include <asm/sibyte/sb1250_defs.h> 37384740dcSRalf Baechle 38384740dcSRalf Baechle 39384740dcSRalf Baechle /* ********************************************************************* 40384740dcSRalf Baechle * Some general notes: 41384740dcSRalf Baechle * 42384740dcSRalf Baechle * For the most part, when there is more than one peripheral 43384740dcSRalf Baechle * of the same type on the SOC, the constants below will be 44384740dcSRalf Baechle * offsets from the base of each peripheral. For example, 45384740dcSRalf Baechle * the MAC registers are described as offsets from the first 46384740dcSRalf Baechle * MAC register, and there will be a MAC_REGISTER() macro 47384740dcSRalf Baechle * to calculate the base address of a given MAC. 48384740dcSRalf Baechle * 49384740dcSRalf Baechle * The information in this file is based on the SB1250 SOC 50384740dcSRalf Baechle * manual version 0.2, July 2000. 51384740dcSRalf Baechle ********************************************************************* */ 52384740dcSRalf Baechle 53384740dcSRalf Baechle 54384740dcSRalf Baechle /* ********************************************************************* 55384740dcSRalf Baechle * Memory Controller Registers 56384740dcSRalf Baechle ********************************************************************* */ 57384740dcSRalf Baechle 58384740dcSRalf Baechle /* 59384740dcSRalf Baechle * XXX: can't remove MC base 0 if 112x, since it's used by other macros, 60384740dcSRalf Baechle * since there is one reg there (but it could get its addr/offset constant). 61384740dcSRalf Baechle */ 62384740dcSRalf Baechle 63384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 64384740dcSRalf Baechle #define A_MC_BASE_0 0x0010051000 65384740dcSRalf Baechle #define A_MC_BASE_1 0x0010052000 66384740dcSRalf Baechle #define MC_REGISTER_SPACING 0x1000 67384740dcSRalf Baechle 68384740dcSRalf Baechle #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 69384740dcSRalf Baechle #define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) 70384740dcSRalf Baechle 71384740dcSRalf Baechle #define R_MC_CONFIG 0x0000000100 72384740dcSRalf Baechle #define R_MC_DRAMCMD 0x0000000120 73384740dcSRalf Baechle #define R_MC_DRAMMODE 0x0000000140 74384740dcSRalf Baechle #define R_MC_TIMING1 0x0000000160 75384740dcSRalf Baechle #define R_MC_TIMING2 0x0000000180 76384740dcSRalf Baechle #define R_MC_CS_START 0x00000001A0 77384740dcSRalf Baechle #define R_MC_CS_END 0x00000001C0 78384740dcSRalf Baechle #define R_MC_CS_INTERLEAVE 0x00000001E0 79384740dcSRalf Baechle #define S_MC_CS_STARTEND 16 80384740dcSRalf Baechle 81384740dcSRalf Baechle #define R_MC_CSX_BASE 0x0000000200 82384740dcSRalf Baechle #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 83384740dcSRalf Baechle #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 84384740dcSRalf Baechle #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 85384740dcSRalf Baechle #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 86384740dcSRalf Baechle 87384740dcSRalf Baechle #define R_MC_CS0_ROW 0x0000000200 88384740dcSRalf Baechle #define R_MC_CS0_COL 0x0000000220 89384740dcSRalf Baechle #define R_MC_CS0_BA 0x0000000240 90384740dcSRalf Baechle #define R_MC_CS1_ROW 0x0000000260 91384740dcSRalf Baechle #define R_MC_CS1_COL 0x0000000280 92384740dcSRalf Baechle #define R_MC_CS1_BA 0x00000002A0 93384740dcSRalf Baechle #define R_MC_CS2_ROW 0x00000002C0 94384740dcSRalf Baechle #define R_MC_CS2_COL 0x00000002E0 95384740dcSRalf Baechle #define R_MC_CS2_BA 0x0000000300 96384740dcSRalf Baechle #define R_MC_CS3_ROW 0x0000000320 97384740dcSRalf Baechle #define R_MC_CS3_COL 0x0000000340 98384740dcSRalf Baechle #define R_MC_CS3_BA 0x0000000360 99384740dcSRalf Baechle #define R_MC_CS_ATTR 0x0000000380 100384740dcSRalf Baechle #define R_MC_TEST_DATA 0x0000000400 101384740dcSRalf Baechle #define R_MC_TEST_ECC 0x0000000420 102384740dcSRalf Baechle #define R_MC_MCLK_CFG 0x0000000500 103384740dcSRalf Baechle 104384740dcSRalf Baechle #endif /* 1250 & 112x */ 105384740dcSRalf Baechle 106384740dcSRalf Baechle /* ********************************************************************* 107384740dcSRalf Baechle * L2 Cache Control Registers 108384740dcSRalf Baechle ********************************************************************* */ 109384740dcSRalf Baechle 110384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ 111384740dcSRalf Baechle 112384740dcSRalf Baechle #define A_L2_READ_TAG 0x0010040018 113384740dcSRalf Baechle #define A_L2_ECC_TAG 0x0010040038 114384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 115384740dcSRalf Baechle #define A_L2_READ_MISC 0x0010040058 116384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 */ 117384740dcSRalf Baechle #define A_L2_WAY_DISABLE 0x0010041000 118384740dcSRalf Baechle #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 119384740dcSRalf Baechle #define A_L2_MGMT_TAG_BASE 0x00D0000000 120384740dcSRalf Baechle 121384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 122384740dcSRalf Baechle #define A_L2_CACHE_DISABLE 0x0010042000 123384740dcSRalf Baechle #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 124384740dcSRalf Baechle #define A_L2_MISC_CONFIG 0x0010043000 125384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 */ 126384740dcSRalf Baechle 127384740dcSRalf Baechle /* Backward-compatibility definitions. */ 128384740dcSRalf Baechle /* XXX: discourage people from using these constants. */ 129384740dcSRalf Baechle #define A_L2_READ_ADDRESS A_L2_READ_TAG 130384740dcSRalf Baechle #define A_L2_EEC_ADDRESS A_L2_ECC_TAG 131384740dcSRalf Baechle 132384740dcSRalf Baechle #endif 133384740dcSRalf Baechle 134384740dcSRalf Baechle 135384740dcSRalf Baechle /* ********************************************************************* 136384740dcSRalf Baechle * PCI Interface Registers 137384740dcSRalf Baechle ********************************************************************* */ 138384740dcSRalf Baechle 139384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ 140384740dcSRalf Baechle #define A_PCI_TYPE00_HEADER 0x00DE000000 141384740dcSRalf Baechle #define A_PCI_TYPE01_HEADER 0x00DE000800 142384740dcSRalf Baechle #endif 143384740dcSRalf Baechle 144384740dcSRalf Baechle 145384740dcSRalf Baechle /* ********************************************************************* 146384740dcSRalf Baechle * Ethernet DMA and MACs 147384740dcSRalf Baechle ********************************************************************* */ 148384740dcSRalf Baechle 149384740dcSRalf Baechle #define A_MAC_BASE_0 0x0010064000 150384740dcSRalf Baechle #define A_MAC_BASE_1 0x0010065000 151384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1250) 152384740dcSRalf Baechle #define A_MAC_BASE_2 0x0010066000 153384740dcSRalf Baechle #endif /* 1250 */ 154384740dcSRalf Baechle 155384740dcSRalf Baechle #define MAC_SPACING 0x1000 156384740dcSRalf Baechle #define MAC_DMA_TXRX_SPACING 0x0400 157384740dcSRalf Baechle #define MAC_DMA_CHANNEL_SPACING 0x0100 158384740dcSRalf Baechle #define DMA_RX 0 159384740dcSRalf Baechle #define DMA_TX 1 160384740dcSRalf Baechle #define MAC_NUM_DMACHAN 2 /* channels per direction */ 161384740dcSRalf Baechle 162384740dcSRalf Baechle /* XXX: not correct; depends on SOC type. */ 163384740dcSRalf Baechle #define MAC_NUM_PORTS 3 164384740dcSRalf Baechle 165384740dcSRalf Baechle #define A_MAC_CHANNEL_BASE(macnum) \ 166384740dcSRalf Baechle (A_MAC_BASE_0 + \ 167384740dcSRalf Baechle MAC_SPACING*(macnum)) 168384740dcSRalf Baechle 169384740dcSRalf Baechle #define A_MAC_REGISTER(macnum,reg) \ 170384740dcSRalf Baechle (A_MAC_BASE_0 + \ 171384740dcSRalf Baechle MAC_SPACING*(macnum) + (reg)) 172384740dcSRalf Baechle 173384740dcSRalf Baechle 174384740dcSRalf Baechle #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 175384740dcSRalf Baechle 176384740dcSRalf Baechle #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ 177384740dcSRalf Baechle ((A_MAC_CHANNEL_BASE(macnum)) + \ 178384740dcSRalf Baechle R_MAC_DMA_CHANNELS + \ 179384740dcSRalf Baechle (MAC_DMA_TXRX_SPACING*(txrx)) + \ 180384740dcSRalf Baechle (MAC_DMA_CHANNEL_SPACING*(chan))) 181384740dcSRalf Baechle 182384740dcSRalf Baechle #define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ 183384740dcSRalf Baechle (R_MAC_DMA_CHANNELS + \ 184384740dcSRalf Baechle (MAC_DMA_TXRX_SPACING*(txrx)) + \ 185384740dcSRalf Baechle (MAC_DMA_CHANNEL_SPACING*(chan))) 186384740dcSRalf Baechle 187384740dcSRalf Baechle #define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ 188384740dcSRalf Baechle (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ 189384740dcSRalf Baechle (reg)) 190384740dcSRalf Baechle 191384740dcSRalf Baechle #define R_MAC_DMA_REGISTER(txrx, chan, reg) \ 192384740dcSRalf Baechle (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ 193384740dcSRalf Baechle (reg)) 194384740dcSRalf Baechle 195384740dcSRalf Baechle /* 196384740dcSRalf Baechle * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 197384740dcSRalf Baechle */ 198384740dcSRalf Baechle 199384740dcSRalf Baechle #define R_MAC_DMA_CONFIG0 0x00000000 200384740dcSRalf Baechle #define R_MAC_DMA_CONFIG1 0x00000008 201384740dcSRalf Baechle #define R_MAC_DMA_DSCR_BASE 0x00000010 202384740dcSRalf Baechle #define R_MAC_DMA_DSCR_CNT 0x00000018 203384740dcSRalf Baechle #define R_MAC_DMA_CUR_DSCRA 0x00000020 204384740dcSRalf Baechle #define R_MAC_DMA_CUR_DSCRB 0x00000028 205384740dcSRalf Baechle #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 206384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 207384740dcSRalf Baechle #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 208384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 */ 209384740dcSRalf Baechle 210384740dcSRalf Baechle /* 211384740dcSRalf Baechle * RMON Counters 212384740dcSRalf Baechle */ 213384740dcSRalf Baechle 214384740dcSRalf Baechle #define R_MAC_RMON_TX_BYTES 0x00000000 215384740dcSRalf Baechle #define R_MAC_RMON_COLLISIONS 0x00000008 216384740dcSRalf Baechle #define R_MAC_RMON_LATE_COL 0x00000010 217384740dcSRalf Baechle #define R_MAC_RMON_EX_COL 0x00000018 218384740dcSRalf Baechle #define R_MAC_RMON_FCS_ERROR 0x00000020 219384740dcSRalf Baechle #define R_MAC_RMON_TX_ABORT 0x00000028 220384740dcSRalf Baechle /* Counter #6 (0x30) now reserved */ 221384740dcSRalf Baechle #define R_MAC_RMON_TX_BAD 0x00000038 222384740dcSRalf Baechle #define R_MAC_RMON_TX_GOOD 0x00000040 223384740dcSRalf Baechle #define R_MAC_RMON_TX_RUNT 0x00000048 224384740dcSRalf Baechle #define R_MAC_RMON_TX_OVERSIZE 0x00000050 225384740dcSRalf Baechle #define R_MAC_RMON_RX_BYTES 0x00000080 226384740dcSRalf Baechle #define R_MAC_RMON_RX_MCAST 0x00000088 227384740dcSRalf Baechle #define R_MAC_RMON_RX_BCAST 0x00000090 228384740dcSRalf Baechle #define R_MAC_RMON_RX_BAD 0x00000098 229384740dcSRalf Baechle #define R_MAC_RMON_RX_GOOD 0x000000A0 230384740dcSRalf Baechle #define R_MAC_RMON_RX_RUNT 0x000000A8 231384740dcSRalf Baechle #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 232384740dcSRalf Baechle #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 233384740dcSRalf Baechle #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 234384740dcSRalf Baechle #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 235384740dcSRalf Baechle #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 236384740dcSRalf Baechle 237384740dcSRalf Baechle /* Updated to spec 0.2 */ 238384740dcSRalf Baechle #define R_MAC_CFG 0x00000100 239384740dcSRalf Baechle #define R_MAC_THRSH_CFG 0x00000108 240384740dcSRalf Baechle #define R_MAC_VLANTAG 0x00000110 241384740dcSRalf Baechle #define R_MAC_FRAMECFG 0x00000118 242384740dcSRalf Baechle #define R_MAC_EOPCNT 0x00000120 243384740dcSRalf Baechle #define R_MAC_FIFO_PTRS 0x00000128 244384740dcSRalf Baechle #define R_MAC_ADFILTER_CFG 0x00000200 245384740dcSRalf Baechle #define R_MAC_ETHERNET_ADDR 0x00000208 246384740dcSRalf Baechle #define R_MAC_PKT_TYPE 0x00000210 247384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 248384740dcSRalf Baechle #define R_MAC_ADMASK0 0x00000218 249384740dcSRalf Baechle #define R_MAC_ADMASK1 0x00000220 250384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 251384740dcSRalf Baechle #define R_MAC_HASH_BASE 0x00000240 252384740dcSRalf Baechle #define R_MAC_ADDR_BASE 0x00000280 253384740dcSRalf Baechle #define R_MAC_CHLO0_BASE 0x00000300 254384740dcSRalf Baechle #define R_MAC_CHUP0_BASE 0x00000320 255384740dcSRalf Baechle #define R_MAC_ENABLE 0x00000400 256384740dcSRalf Baechle #define R_MAC_STATUS 0x00000408 257384740dcSRalf Baechle #define R_MAC_INT_MASK 0x00000410 258384740dcSRalf Baechle #define R_MAC_TXD_CTL 0x00000420 259384740dcSRalf Baechle #define R_MAC_MDIO 0x00000428 260384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 261384740dcSRalf Baechle #define R_MAC_STATUS1 0x00000430 262384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 263384740dcSRalf Baechle #define R_MAC_DEBUG_STATUS 0x00000448 264384740dcSRalf Baechle 265384740dcSRalf Baechle #define MAC_HASH_COUNT 8 266384740dcSRalf Baechle #define MAC_ADDR_COUNT 8 267384740dcSRalf Baechle #define MAC_CHMAP_COUNT 4 268384740dcSRalf Baechle 269384740dcSRalf Baechle 270384740dcSRalf Baechle /* ********************************************************************* 271384740dcSRalf Baechle * DUART Registers 272384740dcSRalf Baechle ********************************************************************* */ 273384740dcSRalf Baechle 274384740dcSRalf Baechle 275384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 276384740dcSRalf Baechle #define R_DUART_NUM_PORTS 2 277384740dcSRalf Baechle 278384740dcSRalf Baechle #define A_DUART 0x0010060000 279384740dcSRalf Baechle 280384740dcSRalf Baechle #define DUART_CHANREG_SPACING 0x100 281384740dcSRalf Baechle 282384740dcSRalf Baechle #define A_DUART_CHANREG(chan, reg) \ 283384740dcSRalf Baechle (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) 284384740dcSRalf Baechle #endif /* 1250 & 112x */ 285384740dcSRalf Baechle 286384740dcSRalf Baechle #define R_DUART_MODE_REG_1 0x000 287384740dcSRalf Baechle #define R_DUART_MODE_REG_2 0x010 288384740dcSRalf Baechle #define R_DUART_STATUS 0x020 289384740dcSRalf Baechle #define R_DUART_CLK_SEL 0x030 290384740dcSRalf Baechle #define R_DUART_CMD 0x050 291384740dcSRalf Baechle #define R_DUART_RX_HOLD 0x060 292384740dcSRalf Baechle #define R_DUART_TX_HOLD 0x070 293384740dcSRalf Baechle 294384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 295384740dcSRalf Baechle #define R_DUART_FULL_CTL 0x040 296384740dcSRalf Baechle #define R_DUART_OPCR_X 0x080 297384740dcSRalf Baechle #define R_DUART_AUXCTL_X 0x090 298384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 299384740dcSRalf Baechle 300384740dcSRalf Baechle 301384740dcSRalf Baechle /* 302384740dcSRalf Baechle * The IMR and ISR can't be addressed with A_DUART_CHANREG, 303384740dcSRalf Baechle * so use these macros instead. 304384740dcSRalf Baechle */ 305384740dcSRalf Baechle 306384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 307384740dcSRalf Baechle #define DUART_IMRISR_SPACING 0x20 308384740dcSRalf Baechle #define DUART_INCHNG_SPACING 0x10 309384740dcSRalf Baechle 310384740dcSRalf Baechle #define A_DUART_CTRLREG(reg) \ 311384740dcSRalf Baechle (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) 312384740dcSRalf Baechle 313384740dcSRalf Baechle #define R_DUART_IMRREG(chan) \ 314384740dcSRalf Baechle (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) 315384740dcSRalf Baechle #define R_DUART_ISRREG(chan) \ 316384740dcSRalf Baechle (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) 317384740dcSRalf Baechle #define R_DUART_INCHREG(chan) \ 318384740dcSRalf Baechle (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) 319384740dcSRalf Baechle 320384740dcSRalf Baechle #define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) 321384740dcSRalf Baechle #define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) 322384740dcSRalf Baechle #define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) 323384740dcSRalf Baechle #endif /* 1250 & 112x */ 324384740dcSRalf Baechle 325384740dcSRalf Baechle #define R_DUART_AUX_CTRL 0x010 326384740dcSRalf Baechle #define R_DUART_ISR_A 0x020 327384740dcSRalf Baechle #define R_DUART_IMR_A 0x030 328384740dcSRalf Baechle #define R_DUART_ISR_B 0x040 329384740dcSRalf Baechle #define R_DUART_IMR_B 0x050 330384740dcSRalf Baechle #define R_DUART_OUT_PORT 0x060 331384740dcSRalf Baechle #define R_DUART_OPCR 0x070 332384740dcSRalf Baechle #define R_DUART_IN_PORT 0x080 333384740dcSRalf Baechle 334384740dcSRalf Baechle #define R_DUART_SET_OPR 0x0B0 335384740dcSRalf Baechle #define R_DUART_CLEAR_OPR 0x0C0 336384740dcSRalf Baechle #define R_DUART_IN_CHNG_A 0x0D0 337384740dcSRalf Baechle #define R_DUART_IN_CHNG_B 0x0E0 338384740dcSRalf Baechle 339384740dcSRalf Baechle 340384740dcSRalf Baechle /* 341384740dcSRalf Baechle * These constants are the absolute addresses. 342384740dcSRalf Baechle */ 343384740dcSRalf Baechle 344384740dcSRalf Baechle #define A_DUART_MODE_REG_1_A 0x0010060100 345384740dcSRalf Baechle #define A_DUART_MODE_REG_2_A 0x0010060110 346384740dcSRalf Baechle #define A_DUART_STATUS_A 0x0010060120 347384740dcSRalf Baechle #define A_DUART_CLK_SEL_A 0x0010060130 348384740dcSRalf Baechle #define A_DUART_CMD_A 0x0010060150 349384740dcSRalf Baechle #define A_DUART_RX_HOLD_A 0x0010060160 350384740dcSRalf Baechle #define A_DUART_TX_HOLD_A 0x0010060170 351384740dcSRalf Baechle 352384740dcSRalf Baechle #define A_DUART_MODE_REG_1_B 0x0010060200 353384740dcSRalf Baechle #define A_DUART_MODE_REG_2_B 0x0010060210 354384740dcSRalf Baechle #define A_DUART_STATUS_B 0x0010060220 355384740dcSRalf Baechle #define A_DUART_CLK_SEL_B 0x0010060230 356384740dcSRalf Baechle #define A_DUART_CMD_B 0x0010060250 357384740dcSRalf Baechle #define A_DUART_RX_HOLD_B 0x0010060260 358384740dcSRalf Baechle #define A_DUART_TX_HOLD_B 0x0010060270 359384740dcSRalf Baechle 360384740dcSRalf Baechle #define A_DUART_INPORT_CHNG 0x0010060300 361384740dcSRalf Baechle #define A_DUART_AUX_CTRL 0x0010060310 362384740dcSRalf Baechle #define A_DUART_ISR_A 0x0010060320 363384740dcSRalf Baechle #define A_DUART_IMR_A 0x0010060330 364384740dcSRalf Baechle #define A_DUART_ISR_B 0x0010060340 365384740dcSRalf Baechle #define A_DUART_IMR_B 0x0010060350 366384740dcSRalf Baechle #define A_DUART_OUT_PORT 0x0010060360 367384740dcSRalf Baechle #define A_DUART_OPCR 0x0010060370 368384740dcSRalf Baechle #define A_DUART_IN_PORT 0x0010060380 369384740dcSRalf Baechle #define A_DUART_ISR 0x0010060390 370384740dcSRalf Baechle #define A_DUART_IMR 0x00100603A0 371384740dcSRalf Baechle #define A_DUART_SET_OPR 0x00100603B0 372384740dcSRalf Baechle #define A_DUART_CLEAR_OPR 0x00100603C0 373384740dcSRalf Baechle #define A_DUART_INPORT_CHNG_A 0x00100603D0 374384740dcSRalf Baechle #define A_DUART_INPORT_CHNG_B 0x00100603E0 375384740dcSRalf Baechle 376384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 377384740dcSRalf Baechle #define A_DUART_FULL_CTL_A 0x0010060140 378384740dcSRalf Baechle #define A_DUART_FULL_CTL_B 0x0010060240 379384740dcSRalf Baechle 380384740dcSRalf Baechle #define A_DUART_OPCR_A 0x0010060180 381384740dcSRalf Baechle #define A_DUART_OPCR_B 0x0010060280 382384740dcSRalf Baechle 383384740dcSRalf Baechle #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 384384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 */ 385384740dcSRalf Baechle 386384740dcSRalf Baechle 387384740dcSRalf Baechle /* ********************************************************************* 388384740dcSRalf Baechle * Synchronous Serial Registers 389384740dcSRalf Baechle ********************************************************************* */ 390384740dcSRalf Baechle 391384740dcSRalf Baechle 392384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ 393384740dcSRalf Baechle 394384740dcSRalf Baechle #define A_SER_BASE_0 0x0010060400 395384740dcSRalf Baechle #define A_SER_BASE_1 0x0010060800 396384740dcSRalf Baechle #define SER_SPACING 0x400 397384740dcSRalf Baechle 398384740dcSRalf Baechle #define SER_DMA_TXRX_SPACING 0x80 399384740dcSRalf Baechle 400384740dcSRalf Baechle #define SER_NUM_PORTS 2 401384740dcSRalf Baechle 402384740dcSRalf Baechle #define A_SER_CHANNEL_BASE(sernum) \ 403384740dcSRalf Baechle (A_SER_BASE_0 + \ 404384740dcSRalf Baechle SER_SPACING*(sernum)) 405384740dcSRalf Baechle 406384740dcSRalf Baechle #define A_SER_REGISTER(sernum,reg) \ 407384740dcSRalf Baechle (A_SER_BASE_0 + \ 408384740dcSRalf Baechle SER_SPACING*(sernum) + (reg)) 409384740dcSRalf Baechle 410384740dcSRalf Baechle 411384740dcSRalf Baechle #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 412384740dcSRalf Baechle 413384740dcSRalf Baechle #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 414384740dcSRalf Baechle ((A_SER_CHANNEL_BASE(sernum)) + \ 415384740dcSRalf Baechle R_SER_DMA_CHANNELS + \ 416384740dcSRalf Baechle (SER_DMA_TXRX_SPACING*(txrx))) 417384740dcSRalf Baechle 418384740dcSRalf Baechle #define A_SER_DMA_REGISTER(sernum, txrx, reg) \ 419384740dcSRalf Baechle (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ 420384740dcSRalf Baechle (reg)) 421384740dcSRalf Baechle 422384740dcSRalf Baechle 423384740dcSRalf Baechle /* 424384740dcSRalf Baechle * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 425384740dcSRalf Baechle */ 426384740dcSRalf Baechle 427384740dcSRalf Baechle #define R_SER_DMA_CONFIG0 0x00000000 428384740dcSRalf Baechle #define R_SER_DMA_CONFIG1 0x00000008 429384740dcSRalf Baechle #define R_SER_DMA_DSCR_BASE 0x00000010 430384740dcSRalf Baechle #define R_SER_DMA_DSCR_CNT 0x00000018 431384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCRA 0x00000020 432384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCRB 0x00000028 433384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCRADDR 0x00000030 434384740dcSRalf Baechle 435384740dcSRalf Baechle #define R_SER_DMA_CONFIG0_RX 0x00000000 436384740dcSRalf Baechle #define R_SER_DMA_CONFIG1_RX 0x00000008 437384740dcSRalf Baechle #define R_SER_DMA_DSCR_BASE_RX 0x00000010 438384740dcSRalf Baechle #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 439384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 440384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 441384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 442384740dcSRalf Baechle 443384740dcSRalf Baechle #define R_SER_DMA_CONFIG0_TX 0x00000080 444384740dcSRalf Baechle #define R_SER_DMA_CONFIG1_TX 0x00000088 445384740dcSRalf Baechle #define R_SER_DMA_DSCR_BASE_TX 0x00000090 446384740dcSRalf Baechle #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 447384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 448384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 449384740dcSRalf Baechle #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 450384740dcSRalf Baechle 451384740dcSRalf Baechle #define R_SER_MODE 0x00000100 452384740dcSRalf Baechle #define R_SER_MINFRM_SZ 0x00000108 453384740dcSRalf Baechle #define R_SER_MAXFRM_SZ 0x00000110 454384740dcSRalf Baechle #define R_SER_ADDR 0x00000118 455384740dcSRalf Baechle #define R_SER_USR0_ADDR 0x00000120 456384740dcSRalf Baechle #define R_SER_USR1_ADDR 0x00000128 457384740dcSRalf Baechle #define R_SER_USR2_ADDR 0x00000130 458384740dcSRalf Baechle #define R_SER_USR3_ADDR 0x00000138 459384740dcSRalf Baechle #define R_SER_CMD 0x00000140 460384740dcSRalf Baechle #define R_SER_TX_RD_THRSH 0x00000160 461384740dcSRalf Baechle #define R_SER_TX_WR_THRSH 0x00000168 462384740dcSRalf Baechle #define R_SER_RX_RD_THRSH 0x00000170 463384740dcSRalf Baechle #define R_SER_LINE_MODE 0x00000178 464384740dcSRalf Baechle #define R_SER_DMA_ENABLE 0x00000180 465384740dcSRalf Baechle #define R_SER_INT_MASK 0x00000190 466384740dcSRalf Baechle #define R_SER_STATUS 0x00000188 467384740dcSRalf Baechle #define R_SER_STATUS_DEBUG 0x000001A8 468384740dcSRalf Baechle #define R_SER_RX_TABLE_BASE 0x00000200 469384740dcSRalf Baechle #define SER_RX_TABLE_COUNT 16 470384740dcSRalf Baechle #define R_SER_TX_TABLE_BASE 0x00000300 471384740dcSRalf Baechle #define SER_TX_TABLE_COUNT 16 472384740dcSRalf Baechle 473384740dcSRalf Baechle /* RMON Counters */ 474384740dcSRalf Baechle #define R_SER_RMON_TX_BYTE_LO 0x000001C0 475384740dcSRalf Baechle #define R_SER_RMON_TX_BYTE_HI 0x000001C8 476384740dcSRalf Baechle #define R_SER_RMON_RX_BYTE_LO 0x000001D0 477384740dcSRalf Baechle #define R_SER_RMON_RX_BYTE_HI 0x000001D8 478384740dcSRalf Baechle #define R_SER_RMON_TX_UNDERRUN 0x000001E0 479384740dcSRalf Baechle #define R_SER_RMON_RX_OVERFLOW 0x000001E8 480384740dcSRalf Baechle #define R_SER_RMON_RX_ERRORS 0x000001F0 481384740dcSRalf Baechle #define R_SER_RMON_RX_BADADDR 0x000001F8 482384740dcSRalf Baechle 483384740dcSRalf Baechle #endif /* 1250/112x */ 484384740dcSRalf Baechle 485384740dcSRalf Baechle /* ********************************************************************* 486384740dcSRalf Baechle * Generic Bus Registers 487384740dcSRalf Baechle ********************************************************************* */ 488384740dcSRalf Baechle 489384740dcSRalf Baechle #define IO_EXT_CFG_COUNT 8 490384740dcSRalf Baechle 491384740dcSRalf Baechle #define A_IO_EXT_BASE 0x0010061000 492384740dcSRalf Baechle #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 493384740dcSRalf Baechle 494384740dcSRalf Baechle #define A_IO_EXT_CFG_BASE 0x0010061000 495384740dcSRalf Baechle #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 496384740dcSRalf Baechle #define A_IO_EXT_START_ADDR_BASE 0x0010061200 497384740dcSRalf Baechle #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 498384740dcSRalf Baechle #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 499384740dcSRalf Baechle 500384740dcSRalf Baechle #define IO_EXT_REGISTER_SPACING 8 501384740dcSRalf Baechle #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 502384740dcSRalf Baechle #define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 503384740dcSRalf Baechle 504384740dcSRalf Baechle #define R_IO_EXT_CFG 0x0000 505384740dcSRalf Baechle #define R_IO_EXT_MULT_SIZE 0x0100 506384740dcSRalf Baechle #define R_IO_EXT_START_ADDR 0x0200 507384740dcSRalf Baechle #define R_IO_EXT_TIME_CFG0 0x0600 508384740dcSRalf Baechle #define R_IO_EXT_TIME_CFG1 0x0700 509384740dcSRalf Baechle 510384740dcSRalf Baechle 511384740dcSRalf Baechle #define A_IO_INTERRUPT_STATUS 0x0010061A00 512384740dcSRalf Baechle #define A_IO_INTERRUPT_DATA0 0x0010061A10 513384740dcSRalf Baechle #define A_IO_INTERRUPT_DATA1 0x0010061A18 514384740dcSRalf Baechle #define A_IO_INTERRUPT_DATA2 0x0010061A20 515384740dcSRalf Baechle #define A_IO_INTERRUPT_DATA3 0x0010061A28 516384740dcSRalf Baechle #define A_IO_INTERRUPT_ADDR0 0x0010061A30 517384740dcSRalf Baechle #define A_IO_INTERRUPT_ADDR1 0x0010061A40 518384740dcSRalf Baechle #define A_IO_INTERRUPT_PARITY 0x0010061A50 519384740dcSRalf Baechle #define A_IO_PCMCIA_CFG 0x0010061A60 520384740dcSRalf Baechle #define A_IO_PCMCIA_STATUS 0x0010061A70 521384740dcSRalf Baechle #define A_IO_DRIVE_0 0x0010061300 522384740dcSRalf Baechle #define A_IO_DRIVE_1 0x0010061308 523384740dcSRalf Baechle #define A_IO_DRIVE_2 0x0010061310 524384740dcSRalf Baechle #define A_IO_DRIVE_3 0x0010061318 525384740dcSRalf Baechle #define A_IO_DRIVE_BASE A_IO_DRIVE_0 526384740dcSRalf Baechle #define IO_DRIVE_REGISTER_SPACING 8 527384740dcSRalf Baechle #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 528384740dcSRalf Baechle #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 529384740dcSRalf Baechle 530384740dcSRalf Baechle #define R_IO_INTERRUPT_STATUS 0x0A00 531384740dcSRalf Baechle #define R_IO_INTERRUPT_DATA0 0x0A10 532384740dcSRalf Baechle #define R_IO_INTERRUPT_DATA1 0x0A18 533384740dcSRalf Baechle #define R_IO_INTERRUPT_DATA2 0x0A20 534384740dcSRalf Baechle #define R_IO_INTERRUPT_DATA3 0x0A28 535384740dcSRalf Baechle #define R_IO_INTERRUPT_ADDR0 0x0A30 536384740dcSRalf Baechle #define R_IO_INTERRUPT_ADDR1 0x0A40 537384740dcSRalf Baechle #define R_IO_INTERRUPT_PARITY 0x0A50 538384740dcSRalf Baechle #define R_IO_PCMCIA_CFG 0x0A60 539384740dcSRalf Baechle #define R_IO_PCMCIA_STATUS 0x0A70 540384740dcSRalf Baechle 541384740dcSRalf Baechle /* ********************************************************************* 542384740dcSRalf Baechle * GPIO Registers 543384740dcSRalf Baechle ********************************************************************* */ 544384740dcSRalf Baechle 545384740dcSRalf Baechle #define A_GPIO_CLR_EDGE 0x0010061A80 546384740dcSRalf Baechle #define A_GPIO_INT_TYPE 0x0010061A88 547384740dcSRalf Baechle #define A_GPIO_INPUT_INVERT 0x0010061A90 548384740dcSRalf Baechle #define A_GPIO_GLITCH 0x0010061A98 549384740dcSRalf Baechle #define A_GPIO_READ 0x0010061AA0 550384740dcSRalf Baechle #define A_GPIO_DIRECTION 0x0010061AA8 551384740dcSRalf Baechle #define A_GPIO_PIN_CLR 0x0010061AB0 552384740dcSRalf Baechle #define A_GPIO_PIN_SET 0x0010061AB8 553384740dcSRalf Baechle 554384740dcSRalf Baechle #define A_GPIO_BASE 0x0010061A80 555384740dcSRalf Baechle 556384740dcSRalf Baechle #define R_GPIO_CLR_EDGE 0x00 557384740dcSRalf Baechle #define R_GPIO_INT_TYPE 0x08 558384740dcSRalf Baechle #define R_GPIO_INPUT_INVERT 0x10 559384740dcSRalf Baechle #define R_GPIO_GLITCH 0x18 560384740dcSRalf Baechle #define R_GPIO_READ 0x20 561384740dcSRalf Baechle #define R_GPIO_DIRECTION 0x28 562384740dcSRalf Baechle #define R_GPIO_PIN_CLR 0x30 563384740dcSRalf Baechle #define R_GPIO_PIN_SET 0x38 564384740dcSRalf Baechle 565384740dcSRalf Baechle /* ********************************************************************* 566384740dcSRalf Baechle * SMBus Registers 567384740dcSRalf Baechle ********************************************************************* */ 568384740dcSRalf Baechle 569384740dcSRalf Baechle #define A_SMB_XTRA_0 0x0010060000 570384740dcSRalf Baechle #define A_SMB_XTRA_1 0x0010060008 571384740dcSRalf Baechle #define A_SMB_FREQ_0 0x0010060010 572384740dcSRalf Baechle #define A_SMB_FREQ_1 0x0010060018 573384740dcSRalf Baechle #define A_SMB_STATUS_0 0x0010060020 574384740dcSRalf Baechle #define A_SMB_STATUS_1 0x0010060028 575384740dcSRalf Baechle #define A_SMB_CMD_0 0x0010060030 576384740dcSRalf Baechle #define A_SMB_CMD_1 0x0010060038 577384740dcSRalf Baechle #define A_SMB_START_0 0x0010060040 578384740dcSRalf Baechle #define A_SMB_START_1 0x0010060048 579384740dcSRalf Baechle #define A_SMB_DATA_0 0x0010060050 580384740dcSRalf Baechle #define A_SMB_DATA_1 0x0010060058 581384740dcSRalf Baechle #define A_SMB_CONTROL_0 0x0010060060 582384740dcSRalf Baechle #define A_SMB_CONTROL_1 0x0010060068 583384740dcSRalf Baechle #define A_SMB_PEC_0 0x0010060070 584384740dcSRalf Baechle #define A_SMB_PEC_1 0x0010060078 585384740dcSRalf Baechle 586384740dcSRalf Baechle #define A_SMB_0 0x0010060000 587384740dcSRalf Baechle #define A_SMB_1 0x0010060008 588384740dcSRalf Baechle #define SMB_REGISTER_SPACING 0x8 589384740dcSRalf Baechle #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 590384740dcSRalf Baechle #define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) 591384740dcSRalf Baechle 592384740dcSRalf Baechle #define R_SMB_XTRA 0x0000000000 593384740dcSRalf Baechle #define R_SMB_FREQ 0x0000000010 594384740dcSRalf Baechle #define R_SMB_STATUS 0x0000000020 595384740dcSRalf Baechle #define R_SMB_CMD 0x0000000030 596384740dcSRalf Baechle #define R_SMB_START 0x0000000040 597384740dcSRalf Baechle #define R_SMB_DATA 0x0000000050 598384740dcSRalf Baechle #define R_SMB_CONTROL 0x0000000060 599384740dcSRalf Baechle #define R_SMB_PEC 0x0000000070 600384740dcSRalf Baechle 601384740dcSRalf Baechle /* ********************************************************************* 602384740dcSRalf Baechle * Timer Registers 603384740dcSRalf Baechle ********************************************************************* */ 604384740dcSRalf Baechle 605384740dcSRalf Baechle /* 606384740dcSRalf Baechle * Watchdog timers 607384740dcSRalf Baechle */ 608384740dcSRalf Baechle 609384740dcSRalf Baechle #define A_SCD_WDOG_0 0x0010020050 610384740dcSRalf Baechle #define A_SCD_WDOG_1 0x0010020150 611384740dcSRalf Baechle #define SCD_WDOG_SPACING 0x100 612384740dcSRalf Baechle #define SCD_NUM_WDOGS 2 613384740dcSRalf Baechle #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 614384740dcSRalf Baechle #define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) 615384740dcSRalf Baechle 616384740dcSRalf Baechle #define R_SCD_WDOG_INIT 0x0000000000 617384740dcSRalf Baechle #define R_SCD_WDOG_CNT 0x0000000008 618384740dcSRalf Baechle #define R_SCD_WDOG_CFG 0x0000000010 619384740dcSRalf Baechle 620384740dcSRalf Baechle #define A_SCD_WDOG_INIT_0 0x0010020050 621384740dcSRalf Baechle #define A_SCD_WDOG_CNT_0 0x0010020058 622384740dcSRalf Baechle #define A_SCD_WDOG_CFG_0 0x0010020060 623384740dcSRalf Baechle 624384740dcSRalf Baechle #define A_SCD_WDOG_INIT_1 0x0010020150 625384740dcSRalf Baechle #define A_SCD_WDOG_CNT_1 0x0010020158 626384740dcSRalf Baechle #define A_SCD_WDOG_CFG_1 0x0010020160 627384740dcSRalf Baechle 628384740dcSRalf Baechle /* 629384740dcSRalf Baechle * Generic timers 630384740dcSRalf Baechle */ 631384740dcSRalf Baechle 632384740dcSRalf Baechle #define A_SCD_TIMER_0 0x0010020070 633384740dcSRalf Baechle #define A_SCD_TIMER_1 0x0010020078 634384740dcSRalf Baechle #define A_SCD_TIMER_2 0x0010020170 635384740dcSRalf Baechle #define A_SCD_TIMER_3 0x0010020178 636384740dcSRalf Baechle #define SCD_NUM_TIMERS 4 637384740dcSRalf Baechle #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 638384740dcSRalf Baechle #define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) 639384740dcSRalf Baechle 640384740dcSRalf Baechle #define R_SCD_TIMER_INIT 0x0000000000 641384740dcSRalf Baechle #define R_SCD_TIMER_CNT 0x0000000010 642384740dcSRalf Baechle #define R_SCD_TIMER_CFG 0x0000000020 643384740dcSRalf Baechle 644384740dcSRalf Baechle #define A_SCD_TIMER_INIT_0 0x0010020070 645384740dcSRalf Baechle #define A_SCD_TIMER_CNT_0 0x0010020080 646384740dcSRalf Baechle #define A_SCD_TIMER_CFG_0 0x0010020090 647384740dcSRalf Baechle 648384740dcSRalf Baechle #define A_SCD_TIMER_INIT_1 0x0010020078 649384740dcSRalf Baechle #define A_SCD_TIMER_CNT_1 0x0010020088 650384740dcSRalf Baechle #define A_SCD_TIMER_CFG_1 0x0010020098 651384740dcSRalf Baechle 652384740dcSRalf Baechle #define A_SCD_TIMER_INIT_2 0x0010020170 653384740dcSRalf Baechle #define A_SCD_TIMER_CNT_2 0x0010020180 654384740dcSRalf Baechle #define A_SCD_TIMER_CFG_2 0x0010020190 655384740dcSRalf Baechle 656384740dcSRalf Baechle #define A_SCD_TIMER_INIT_3 0x0010020178 657384740dcSRalf Baechle #define A_SCD_TIMER_CNT_3 0x0010020188 658384740dcSRalf Baechle #define A_SCD_TIMER_CFG_3 0x0010020198 659384740dcSRalf Baechle 660384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 661384740dcSRalf Baechle #define A_SCD_SCRATCH 0x0010020C10 662384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 */ 663384740dcSRalf Baechle 664384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 665384740dcSRalf Baechle #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 666384740dcSRalf Baechle #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 667384740dcSRalf Baechle #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 668384740dcSRalf Baechle #endif 669384740dcSRalf Baechle 670384740dcSRalf Baechle /* ********************************************************************* 671384740dcSRalf Baechle * System Control Registers 672384740dcSRalf Baechle ********************************************************************* */ 673384740dcSRalf Baechle 674384740dcSRalf Baechle #define A_SCD_SYSTEM_REVISION 0x0010020000 675384740dcSRalf Baechle #define A_SCD_SYSTEM_CFG 0x0010020008 676384740dcSRalf Baechle #define A_SCD_SYSTEM_MANUF 0x0010038000 677384740dcSRalf Baechle 678384740dcSRalf Baechle /* ********************************************************************* 679384740dcSRalf Baechle * System Address Trap Registers 680384740dcSRalf Baechle ********************************************************************* */ 681384740dcSRalf Baechle 682384740dcSRalf Baechle #define A_ADDR_TRAP_INDEX 0x00100200B0 683384740dcSRalf Baechle #define A_ADDR_TRAP_REG 0x00100200B8 684384740dcSRalf Baechle #define A_ADDR_TRAP_UP_0 0x0010020400 685384740dcSRalf Baechle #define A_ADDR_TRAP_UP_1 0x0010020408 686384740dcSRalf Baechle #define A_ADDR_TRAP_UP_2 0x0010020410 687384740dcSRalf Baechle #define A_ADDR_TRAP_UP_3 0x0010020418 688384740dcSRalf Baechle #define A_ADDR_TRAP_DOWN_0 0x0010020420 689384740dcSRalf Baechle #define A_ADDR_TRAP_DOWN_1 0x0010020428 690384740dcSRalf Baechle #define A_ADDR_TRAP_DOWN_2 0x0010020430 691384740dcSRalf Baechle #define A_ADDR_TRAP_DOWN_3 0x0010020438 692384740dcSRalf Baechle #define A_ADDR_TRAP_CFG_0 0x0010020440 693384740dcSRalf Baechle #define A_ADDR_TRAP_CFG_1 0x0010020448 694384740dcSRalf Baechle #define A_ADDR_TRAP_CFG_2 0x0010020450 695384740dcSRalf Baechle #define A_ADDR_TRAP_CFG_3 0x0010020458 696384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 697384740dcSRalf Baechle #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 698384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 699384740dcSRalf Baechle 700384740dcSRalf Baechle #define ADDR_TRAP_SPACING 8 701384740dcSRalf Baechle #define NUM_ADDR_TRAP 4 702384740dcSRalf Baechle #define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) 703384740dcSRalf Baechle #define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) 704384740dcSRalf Baechle #define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) 705384740dcSRalf Baechle 706384740dcSRalf Baechle 707384740dcSRalf Baechle /* ********************************************************************* 708384740dcSRalf Baechle * System Interrupt Mapper Registers 709384740dcSRalf Baechle ********************************************************************* */ 710384740dcSRalf Baechle 711384740dcSRalf Baechle #define A_IMR_CPU0_BASE 0x0010020000 712384740dcSRalf Baechle #define A_IMR_CPU1_BASE 0x0010022000 713384740dcSRalf Baechle #define IMR_REGISTER_SPACING 0x2000 714384740dcSRalf Baechle #define IMR_REGISTER_SPACING_SHIFT 13 715384740dcSRalf Baechle 716384740dcSRalf Baechle #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 717384740dcSRalf Baechle #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) 718384740dcSRalf Baechle 719384740dcSRalf Baechle #define R_IMR_INTERRUPT_DIAG 0x0010 720384740dcSRalf Baechle #define R_IMR_INTERRUPT_LDT 0x0018 721384740dcSRalf Baechle #define R_IMR_INTERRUPT_MASK 0x0028 722384740dcSRalf Baechle #define R_IMR_INTERRUPT_TRACE 0x0038 723384740dcSRalf Baechle #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 724384740dcSRalf Baechle #define R_IMR_LDT_INTERRUPT_SET 0x0048 725384740dcSRalf Baechle #define R_IMR_LDT_INTERRUPT 0x0018 726384740dcSRalf Baechle #define R_IMR_LDT_INTERRUPT_CLR 0x0020 727384740dcSRalf Baechle #define R_IMR_MAILBOX_CPU 0x00c0 728384740dcSRalf Baechle #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 729384740dcSRalf Baechle #define R_IMR_MAILBOX_SET_CPU 0x00C8 730384740dcSRalf Baechle #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 731384740dcSRalf Baechle #define R_IMR_MAILBOX_CLR_CPU 0x00D0 732384740dcSRalf Baechle #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 733384740dcSRalf Baechle #define R_IMR_INTERRUPT_STATUS_COUNT 7 734384740dcSRalf Baechle #define R_IMR_INTERRUPT_MAP_BASE 0x0200 735384740dcSRalf Baechle #define R_IMR_INTERRUPT_MAP_COUNT 64 736384740dcSRalf Baechle 737384740dcSRalf Baechle /* 738384740dcSRalf Baechle * these macros work together to build the address of a mailbox 739384740dcSRalf Baechle * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1) 740384740dcSRalf Baechle * for mbox_0_set_cpu2 returns 0x00100240C8 741384740dcSRalf Baechle */ 742384740dcSRalf Baechle #define A_MAILBOX_REGISTER(reg,cpu) \ 743384740dcSRalf Baechle (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) 744384740dcSRalf Baechle 745384740dcSRalf Baechle /* ********************************************************************* 746384740dcSRalf Baechle * System Performance Counter Registers 747384740dcSRalf Baechle ********************************************************************* */ 748384740dcSRalf Baechle 749384740dcSRalf Baechle #define A_SCD_PERF_CNT_CFG 0x00100204C0 750384740dcSRalf Baechle #define A_SCD_PERF_CNT_0 0x00100204D0 751384740dcSRalf Baechle #define A_SCD_PERF_CNT_1 0x00100204D8 752384740dcSRalf Baechle #define A_SCD_PERF_CNT_2 0x00100204E0 753384740dcSRalf Baechle #define A_SCD_PERF_CNT_3 0x00100204E8 754384740dcSRalf Baechle 755384740dcSRalf Baechle #define SCD_NUM_PERF_CNT 4 756384740dcSRalf Baechle #define SCD_PERF_CNT_SPACING 8 757384740dcSRalf Baechle #define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) 758384740dcSRalf Baechle 759384740dcSRalf Baechle /* ********************************************************************* 760384740dcSRalf Baechle * System Bus Watcher Registers 761384740dcSRalf Baechle ********************************************************************* */ 762384740dcSRalf Baechle 763384740dcSRalf Baechle #define A_SCD_BUS_ERR_STATUS 0x0010020880 764384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 765384740dcSRalf Baechle #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 766384740dcSRalf Baechle #define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 767384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 */ 768384740dcSRalf Baechle #define A_BUS_ERR_DATA_0 0x00100208A0 769384740dcSRalf Baechle #define A_BUS_ERR_DATA_1 0x00100208A8 770384740dcSRalf Baechle #define A_BUS_ERR_DATA_2 0x00100208B0 771384740dcSRalf Baechle #define A_BUS_ERR_DATA_3 0x00100208B8 772384740dcSRalf Baechle #define A_BUS_L2_ERRORS 0x00100208C0 773384740dcSRalf Baechle #define A_BUS_MEM_IO_ERRORS 0x00100208C8 774384740dcSRalf Baechle 775384740dcSRalf Baechle /* ********************************************************************* 776384740dcSRalf Baechle * System Debug Controller Registers 777384740dcSRalf Baechle ********************************************************************* */ 778384740dcSRalf Baechle 779384740dcSRalf Baechle #define A_SCD_JTAG_BASE 0x0010000000 780384740dcSRalf Baechle 781384740dcSRalf Baechle /* ********************************************************************* 782384740dcSRalf Baechle * System Trace Buffer Registers 783384740dcSRalf Baechle ********************************************************************* */ 784384740dcSRalf Baechle 785384740dcSRalf Baechle #define A_SCD_TRACE_CFG 0x0010020A00 786384740dcSRalf Baechle #define A_SCD_TRACE_READ 0x0010020A08 787384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_0 0x0010020A20 788384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_1 0x0010020A28 789384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_2 0x0010020A30 790384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_3 0x0010020A38 791384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 792384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 793384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 794384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 795384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_4 0x0010020A60 796384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_5 0x0010020A68 797384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_6 0x0010020A70 798384740dcSRalf Baechle #define A_SCD_TRACE_EVENT_7 0x0010020A78 799384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 800384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 801384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 802384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 803384740dcSRalf Baechle 804384740dcSRalf Baechle #define TRACE_REGISTER_SPACING 8 805384740dcSRalf Baechle #define TRACE_NUM_REGISTERS 8 806384740dcSRalf Baechle #define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ 807384740dcSRalf Baechle (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 808384740dcSRalf Baechle (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING))) 809384740dcSRalf Baechle #define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ 810384740dcSRalf Baechle (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 811384740dcSRalf Baechle (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING))) 812384740dcSRalf Baechle 813384740dcSRalf Baechle /* ********************************************************************* 814384740dcSRalf Baechle * System Generic DMA Registers 815384740dcSRalf Baechle ********************************************************************* */ 816384740dcSRalf Baechle 817384740dcSRalf Baechle #define A_DM_0 0x0010020B00 818384740dcSRalf Baechle #define A_DM_1 0x0010020B20 819384740dcSRalf Baechle #define A_DM_2 0x0010020B40 820384740dcSRalf Baechle #define A_DM_3 0x0010020B60 821384740dcSRalf Baechle #define DM_REGISTER_SPACING 0x20 822384740dcSRalf Baechle #define DM_NUM_CHANNELS 4 823384740dcSRalf Baechle #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 824384740dcSRalf Baechle #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) 825384740dcSRalf Baechle 826384740dcSRalf Baechle #define R_DM_DSCR_BASE 0x0000000000 827384740dcSRalf Baechle #define R_DM_DSCR_COUNT 0x0000000008 828384740dcSRalf Baechle #define R_DM_CUR_DSCR_ADDR 0x0000000010 829384740dcSRalf Baechle #define R_DM_DSCR_BASE_DEBUG 0x0000000018 830384740dcSRalf Baechle 831384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 832384740dcSRalf Baechle #define A_DM_PARTIAL_0 0x0010020ba0 833384740dcSRalf Baechle #define A_DM_PARTIAL_1 0x0010020ba8 834384740dcSRalf Baechle #define A_DM_PARTIAL_2 0x0010020bb0 835384740dcSRalf Baechle #define A_DM_PARTIAL_3 0x0010020bb8 836384740dcSRalf Baechle #define DM_PARTIAL_REGISTER_SPACING 0x8 837384740dcSRalf Baechle #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 838384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 */ 839384740dcSRalf Baechle 840384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 841384740dcSRalf Baechle #define A_DM_CRC_0 0x0010020b80 842384740dcSRalf Baechle #define A_DM_CRC_1 0x0010020b90 843384740dcSRalf Baechle #define DM_CRC_REGISTER_SPACING 0x10 844384740dcSRalf Baechle #define DM_CRC_NUM_CHANNELS 2 845384740dcSRalf Baechle #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 846384740dcSRalf Baechle #define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) 847384740dcSRalf Baechle 848384740dcSRalf Baechle #define R_CRC_DEF_0 0x00 849384740dcSRalf Baechle #define R_CTCP_DEF_0 0x08 850384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 */ 851384740dcSRalf Baechle 852384740dcSRalf Baechle /* ********************************************************************* 853384740dcSRalf Baechle * Physical Address Map 854384740dcSRalf Baechle ********************************************************************* */ 855384740dcSRalf Baechle 856384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_1250_112x 857384740dcSRalf Baechle #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 858384740dcSRalf Baechle #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 859384740dcSRalf Baechle #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 860384740dcSRalf Baechle #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 861384740dcSRalf Baechle #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 862384740dcSRalf Baechle #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 863384740dcSRalf Baechle #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 864384740dcSRalf Baechle #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 865384740dcSRalf Baechle #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 866384740dcSRalf Baechle #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 867384740dcSRalf Baechle #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 868384740dcSRalf Baechle #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 869384740dcSRalf Baechle #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 870384740dcSRalf Baechle #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 871384740dcSRalf Baechle #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 872384740dcSRalf Baechle #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 873384740dcSRalf Baechle #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 874384740dcSRalf Baechle #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 875384740dcSRalf Baechle #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 876384740dcSRalf Baechle #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 877384740dcSRalf Baechle #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 878384740dcSRalf Baechle #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 879384740dcSRalf Baechle #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 880384740dcSRalf Baechle #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 881384740dcSRalf Baechle #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 882384740dcSRalf Baechle 883384740dcSRalf Baechle #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 884384740dcSRalf Baechle #define PHYS_L2CACHE_NUM_WAYS 4 885384740dcSRalf Baechle #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 886384740dcSRalf Baechle #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 887384740dcSRalf Baechle #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 888384740dcSRalf Baechle #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 889384740dcSRalf Baechle #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 890384740dcSRalf Baechle #endif 891384740dcSRalf Baechle 892384740dcSRalf Baechle 893384740dcSRalf Baechle #endif 894