1 /*  *********************************************************************
2     *  SB1250 Board Support Package
3     *
4     *  Memory Controller constants		File: sb1250_mc.h
5     *
6     *  This module contains constants and macros useful for
7     *  programming the memory controller.
8     *
9     *  SB1250 specification level:  User's manual 1/02/02
10     *
11     *********************************************************************
12     *
13     *  Copyright 2000, 2001, 2002, 2003
14     *  Broadcom Corporation. All rights reserved.
15     *
16     *  This program is free software; you can redistribute it and/or
17     *  modify it under the terms of the GNU General Public License as
18     *  published by the Free Software Foundation; either version 2 of
19     *  the License, or (at your option) any later version.
20     *
21     *  This program is distributed in the hope that it will be useful,
22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24     *  GNU General Public License for more details.
25     *
26     *  You should have received a copy of the GNU General Public License
27     *  along with this program; if not, write to the Free Software
28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29     *  MA 02111-1307 USA
30     ********************************************************************* */
31 
32 
33 #ifndef _SB1250_MC_H
34 #define _SB1250_MC_H
35 
36 #include <asm/sibyte/sb1250_defs.h>
37 
38 /*
39  * Memory Channel Config Register (table 6-14)
40  */
41 
42 #define S_MC_RESERVED0		    0
43 #define M_MC_RESERVED0		    _SB_MAKEMASK(8, S_MC_RESERVED0)
44 
45 #define S_MC_CHANNEL_SEL	    8
46 #define M_MC_CHANNEL_SEL	    _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
47 #define V_MC_CHANNEL_SEL(x)	    _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
48 #define G_MC_CHANNEL_SEL(x)	    _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
49 
50 #define S_MC_BANK0_MAP		    16
51 #define M_MC_BANK0_MAP		    _SB_MAKEMASK(4, S_MC_BANK0_MAP)
52 #define V_MC_BANK0_MAP(x)	    _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
53 #define G_MC_BANK0_MAP(x)	    _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
54 
55 #define K_MC_BANK0_MAP_DEFAULT	    0x00
56 #define V_MC_BANK0_MAP_DEFAULT	    V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
57 
58 #define S_MC_BANK1_MAP		    20
59 #define M_MC_BANK1_MAP		    _SB_MAKEMASK(4, S_MC_BANK1_MAP)
60 #define V_MC_BANK1_MAP(x)	    _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
61 #define G_MC_BANK1_MAP(x)	    _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
62 
63 #define K_MC_BANK1_MAP_DEFAULT	    0x08
64 #define V_MC_BANK1_MAP_DEFAULT	    V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
65 
66 #define S_MC_BANK2_MAP		    24
67 #define M_MC_BANK2_MAP		    _SB_MAKEMASK(4, S_MC_BANK2_MAP)
68 #define V_MC_BANK2_MAP(x)	    _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
69 #define G_MC_BANK2_MAP(x)	    _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
70 
71 #define K_MC_BANK2_MAP_DEFAULT	    0x09
72 #define V_MC_BANK2_MAP_DEFAULT	    V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
73 
74 #define S_MC_BANK3_MAP		    28
75 #define M_MC_BANK3_MAP		    _SB_MAKEMASK(4, S_MC_BANK3_MAP)
76 #define V_MC_BANK3_MAP(x)	    _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
77 #define G_MC_BANK3_MAP(x)	    _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
78 
79 #define K_MC_BANK3_MAP_DEFAULT	    0x0C
80 #define V_MC_BANK3_MAP_DEFAULT	    V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
81 
82 #define M_MC_RESERVED1		    _SB_MAKEMASK(8, 32)
83 
84 #define S_MC_QUEUE_SIZE		    40
85 #define M_MC_QUEUE_SIZE		    _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
86 #define V_MC_QUEUE_SIZE(x)	    _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
87 #define G_MC_QUEUE_SIZE(x)	    _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
88 #define V_MC_QUEUE_SIZE_DEFAULT	    V_MC_QUEUE_SIZE(0x0A)
89 
90 #define S_MC_AGE_LIMIT		    44
91 #define M_MC_AGE_LIMIT		    _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
92 #define V_MC_AGE_LIMIT(x)	    _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
93 #define G_MC_AGE_LIMIT(x)	    _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
94 #define V_MC_AGE_LIMIT_DEFAULT	    V_MC_AGE_LIMIT(8)
95 
96 #define S_MC_WR_LIMIT		    48
97 #define M_MC_WR_LIMIT		    _SB_MAKEMASK(4, S_MC_WR_LIMIT)
98 #define V_MC_WR_LIMIT(x)	    _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
99 #define G_MC_WR_LIMIT(x)	    _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
100 #define V_MC_WR_LIMIT_DEFAULT	    V_MC_WR_LIMIT(5)
101 
102 #define M_MC_IOB1HIGHPRIORITY	    _SB_MAKEMASK1(52)
103 
104 #define M_MC_RESERVED2		    _SB_MAKEMASK(3, 53)
105 
106 #define S_MC_CS_MODE		    56
107 #define M_MC_CS_MODE		    _SB_MAKEMASK(4, S_MC_CS_MODE)
108 #define V_MC_CS_MODE(x)		    _SB_MAKEVALUE(x, S_MC_CS_MODE)
109 #define G_MC_CS_MODE(x)		    _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
110 
111 #define K_MC_CS_MODE_MSB_CS	    0
112 #define K_MC_CS_MODE_INTLV_CS	    15
113 #define K_MC_CS_MODE_MIXED_CS_10    12
114 #define K_MC_CS_MODE_MIXED_CS_30    6
115 #define K_MC_CS_MODE_MIXED_CS_32    3
116 
117 #define V_MC_CS_MODE_MSB_CS	    V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
118 #define V_MC_CS_MODE_INTLV_CS	    V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
119 #define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
120 #define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
121 #define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
122 
123 #define M_MC_ECC_DISABLE	    _SB_MAKEMASK1(60)
124 #define M_MC_BERR_DISABLE	    _SB_MAKEMASK1(61)
125 #define M_MC_FORCE_SEQ		    _SB_MAKEMASK1(62)
126 #define M_MC_DEBUG		    _SB_MAKEMASK1(63)
127 
128 #define V_MC_CONFIG_DEFAULT	V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
129 				V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
130 				V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
131 				M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
132 
133 
134 /*
135  * Memory clock config register (Table 6-15)
136  *
137  * Note: this field has been updated to be consistent with the errata to 0.2
138  */
139 
140 #define S_MC_CLK_RATIO		    0
141 #define M_MC_CLK_RATIO		    _SB_MAKEMASK(4, S_MC_CLK_RATIO)
142 #define V_MC_CLK_RATIO(x)	    _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
143 #define G_MC_CLK_RATIO(x)	    _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
144 
145 #define K_MC_CLK_RATIO_2X	    4
146 #define K_MC_CLK_RATIO_25X	    5
147 #define K_MC_CLK_RATIO_3X	    6
148 #define K_MC_CLK_RATIO_35X	    7
149 #define K_MC_CLK_RATIO_4X	    8
150 #define K_MC_CLK_RATIO_45X	    9
151 
152 #define V_MC_CLK_RATIO_2X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
153 #define V_MC_CLK_RATIO_25X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
154 #define V_MC_CLK_RATIO_3X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
155 #define V_MC_CLK_RATIO_35X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
156 #define V_MC_CLK_RATIO_4X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
157 #define V_MC_CLK_RATIO_45X	    V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
158 #define V_MC_CLK_RATIO_DEFAULT	    V_MC_CLK_RATIO_25X
159 
160 #define S_MC_REF_RATE		     8
161 #define M_MC_REF_RATE		     _SB_MAKEMASK(8, S_MC_REF_RATE)
162 #define V_MC_REF_RATE(x)	     _SB_MAKEVALUE(x, S_MC_REF_RATE)
163 #define G_MC_REF_RATE(x)	     _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
164 
165 #define K_MC_REF_RATE_100MHz	     0x62
166 #define K_MC_REF_RATE_133MHz	     0x81
167 #define K_MC_REF_RATE_200MHz	     0xC4
168 
169 #define V_MC_REF_RATE_100MHz	     V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
170 #define V_MC_REF_RATE_133MHz	     V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
171 #define V_MC_REF_RATE_200MHz	     V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
172 #define V_MC_REF_RATE_DEFAULT	     V_MC_REF_RATE_100MHz
173 
174 #define S_MC_CLOCK_DRIVE	     16
175 #define M_MC_CLOCK_DRIVE	     _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
176 #define V_MC_CLOCK_DRIVE(x)	     _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
177 #define G_MC_CLOCK_DRIVE(x)	     _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
178 #define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
179 
180 #define S_MC_DATA_DRIVE		     20
181 #define M_MC_DATA_DRIVE		     _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
182 #define V_MC_DATA_DRIVE(x)	     _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
183 #define G_MC_DATA_DRIVE(x)	     _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
184 #define V_MC_DATA_DRIVE_DEFAULT	     V_MC_DATA_DRIVE(0x0)
185 
186 #define S_MC_ADDR_DRIVE		     24
187 #define M_MC_ADDR_DRIVE		     _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
188 #define V_MC_ADDR_DRIVE(x)	     _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
189 #define G_MC_ADDR_DRIVE(x)	     _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
190 #define V_MC_ADDR_DRIVE_DEFAULT	     V_MC_ADDR_DRIVE(0x0)
191 
192 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
193 #define M_MC_REF_DISABLE	     _SB_MAKEMASK1(30)
194 #endif /* 1250 PASS3 || 112x PASS1 */
195 
196 #define M_MC_DLL_BYPASS		     _SB_MAKEMASK1(31)
197 
198 #define S_MC_DQI_SKEW		    32
199 #define M_MC_DQI_SKEW		    _SB_MAKEMASK(8, S_MC_DQI_SKEW)
200 #define V_MC_DQI_SKEW(x)	    _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
201 #define G_MC_DQI_SKEW(x)	    _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
202 #define V_MC_DQI_SKEW_DEFAULT	    V_MC_DQI_SKEW(0)
203 
204 #define S_MC_DQO_SKEW		    40
205 #define M_MC_DQO_SKEW		    _SB_MAKEMASK(8, S_MC_DQO_SKEW)
206 #define V_MC_DQO_SKEW(x)	    _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
207 #define G_MC_DQO_SKEW(x)	    _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
208 #define V_MC_DQO_SKEW_DEFAULT	    V_MC_DQO_SKEW(0)
209 
210 #define S_MC_ADDR_SKEW		     48
211 #define M_MC_ADDR_SKEW		     _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
212 #define V_MC_ADDR_SKEW(x)	     _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
213 #define G_MC_ADDR_SKEW(x)	     _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
214 #define V_MC_ADDR_SKEW_DEFAULT	     V_MC_ADDR_SKEW(0x0F)
215 
216 #define S_MC_DLL_DEFAULT	     56
217 #define M_MC_DLL_DEFAULT	     _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
218 #define V_MC_DLL_DEFAULT(x)	     _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
219 #define G_MC_DLL_DEFAULT(x)	     _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
220 #define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
221 
222 #define V_MC_CLKCONFIG_DEFAULT	     V_MC_DLL_DEFAULT_DEFAULT |	 \
223 				     V_MC_ADDR_SKEW_DEFAULT | \
224 				     V_MC_DQO_SKEW_DEFAULT | \
225 				     V_MC_DQI_SKEW_DEFAULT | \
226 				     V_MC_ADDR_DRIVE_DEFAULT | \
227 				     V_MC_DATA_DRIVE_DEFAULT | \
228 				     V_MC_CLOCK_DRIVE_DEFAULT | \
229 				     V_MC_REF_RATE_DEFAULT
230 
231 
232 
233 /*
234  * DRAM Command Register (Table 6-13)
235  */
236 
237 #define S_MC_COMMAND		    0
238 #define M_MC_COMMAND		    _SB_MAKEMASK(4, S_MC_COMMAND)
239 #define V_MC_COMMAND(x)		    _SB_MAKEVALUE(x, S_MC_COMMAND)
240 #define G_MC_COMMAND(x)		    _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
241 
242 #define K_MC_COMMAND_EMRS	    0
243 #define K_MC_COMMAND_MRS	    1
244 #define K_MC_COMMAND_PRE	    2
245 #define K_MC_COMMAND_AR		    3
246 #define K_MC_COMMAND_SETRFSH	    4
247 #define K_MC_COMMAND_CLRRFSH	    5
248 #define K_MC_COMMAND_SETPWRDN	    6
249 #define K_MC_COMMAND_CLRPWRDN	    7
250 
251 #define V_MC_COMMAND_EMRS	    V_MC_COMMAND(K_MC_COMMAND_EMRS)
252 #define V_MC_COMMAND_MRS	    V_MC_COMMAND(K_MC_COMMAND_MRS)
253 #define V_MC_COMMAND_PRE	    V_MC_COMMAND(K_MC_COMMAND_PRE)
254 #define V_MC_COMMAND_AR		    V_MC_COMMAND(K_MC_COMMAND_AR)
255 #define V_MC_COMMAND_SETRFSH	    V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
256 #define V_MC_COMMAND_CLRRFSH	    V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
257 #define V_MC_COMMAND_SETPWRDN	    V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
258 #define V_MC_COMMAND_CLRPWRDN	    V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
259 
260 #define M_MC_CS0		    _SB_MAKEMASK1(4)
261 #define M_MC_CS1		    _SB_MAKEMASK1(5)
262 #define M_MC_CS2		    _SB_MAKEMASK1(6)
263 #define M_MC_CS3		    _SB_MAKEMASK1(7)
264 
265 /*
266  * DRAM Mode Register (Table 6-14)
267  */
268 
269 #define S_MC_EMODE		    0
270 #define M_MC_EMODE		    _SB_MAKEMASK(15, S_MC_EMODE)
271 #define V_MC_EMODE(x)		    _SB_MAKEVALUE(x, S_MC_EMODE)
272 #define G_MC_EMODE(x)		    _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
273 #define V_MC_EMODE_DEFAULT	    V_MC_EMODE(0)
274 
275 #define S_MC_MODE		    16
276 #define M_MC_MODE		    _SB_MAKEMASK(15, S_MC_MODE)
277 #define V_MC_MODE(x)		    _SB_MAKEVALUE(x, S_MC_MODE)
278 #define G_MC_MODE(x)		    _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
279 #define V_MC_MODE_DEFAULT	    V_MC_MODE(0x22)
280 
281 #define S_MC_DRAM_TYPE		    32
282 #define M_MC_DRAM_TYPE		    _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
283 #define V_MC_DRAM_TYPE(x)	    _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
284 #define G_MC_DRAM_TYPE(x)	    _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
285 
286 #define K_MC_DRAM_TYPE_JEDEC	    0
287 #define K_MC_DRAM_TYPE_FCRAM	    1
288 #define K_MC_DRAM_TYPE_SGRAM	    2
289 
290 #define V_MC_DRAM_TYPE_JEDEC	    V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
291 #define V_MC_DRAM_TYPE_FCRAM	    V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
292 #define V_MC_DRAM_TYPE_SGRAM	    V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
293 
294 #define M_MC_EXTERNALDECODE	    _SB_MAKEMASK1(35)
295 
296 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
297 #define M_MC_PRE_ON_A8		    _SB_MAKEMASK1(36)
298 #define M_MC_RAM_WITH_A13	    _SB_MAKEMASK1(37)
299 #endif /* 1250 PASS3 || 112x PASS1 */
300 
301 
302 
303 /*
304  * SDRAM Timing Register  (Table 6-15)
305  */
306 
307 #define M_MC_w2rIDLE_TWOCYCLES	  _SB_MAKEMASK1(60)
308 #define M_MC_r2wIDLE_TWOCYCLES	  _SB_MAKEMASK1(61)
309 #define M_MC_r2rIDLE_TWOCYCLES	  _SB_MAKEMASK1(62)
310 
311 #define S_MC_tFIFO		  56
312 #define M_MC_tFIFO		  _SB_MAKEMASK(4, S_MC_tFIFO)
313 #define V_MC_tFIFO(x)		  _SB_MAKEVALUE(x, S_MC_tFIFO)
314 #define G_MC_tFIFO(x)		  _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
315 #define K_MC_tFIFO_DEFAULT	  1
316 #define V_MC_tFIFO_DEFAULT	  V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
317 
318 #define S_MC_tRFC		  52
319 #define M_MC_tRFC		  _SB_MAKEMASK(4, S_MC_tRFC)
320 #define V_MC_tRFC(x)		  _SB_MAKEVALUE(x, S_MC_tRFC)
321 #define G_MC_tRFC(x)		  _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
322 #define K_MC_tRFC_DEFAULT	  12
323 #define V_MC_tRFC_DEFAULT	  V_MC_tRFC(K_MC_tRFC_DEFAULT)
324 
325 #if SIBYTE_HDR_FEATURE(1250, PASS3)
326 #define M_MC_tRFC_PLUS16	  _SB_MAKEMASK1(51)	/* 1250C3 and later.  */
327 #endif
328 
329 #define S_MC_tCwCr		  40
330 #define M_MC_tCwCr		  _SB_MAKEMASK(4, S_MC_tCwCr)
331 #define V_MC_tCwCr(x)		  _SB_MAKEVALUE(x, S_MC_tCwCr)
332 #define G_MC_tCwCr(x)		  _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
333 #define K_MC_tCwCr_DEFAULT	  4
334 #define V_MC_tCwCr_DEFAULT	  V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
335 
336 #define S_MC_tRCr		  28
337 #define M_MC_tRCr		  _SB_MAKEMASK(4, S_MC_tRCr)
338 #define V_MC_tRCr(x)		  _SB_MAKEVALUE(x, S_MC_tRCr)
339 #define G_MC_tRCr(x)		  _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
340 #define K_MC_tRCr_DEFAULT	  9
341 #define V_MC_tRCr_DEFAULT	  V_MC_tRCr(K_MC_tRCr_DEFAULT)
342 
343 #define S_MC_tRCw		  24
344 #define M_MC_tRCw		  _SB_MAKEMASK(4, S_MC_tRCw)
345 #define V_MC_tRCw(x)		  _SB_MAKEVALUE(x, S_MC_tRCw)
346 #define G_MC_tRCw(x)		  _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
347 #define K_MC_tRCw_DEFAULT	  10
348 #define V_MC_tRCw_DEFAULT	  V_MC_tRCw(K_MC_tRCw_DEFAULT)
349 
350 #define S_MC_tRRD		  20
351 #define M_MC_tRRD		  _SB_MAKEMASK(4, S_MC_tRRD)
352 #define V_MC_tRRD(x)		  _SB_MAKEVALUE(x, S_MC_tRRD)
353 #define G_MC_tRRD(x)		  _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
354 #define K_MC_tRRD_DEFAULT	  2
355 #define V_MC_tRRD_DEFAULT	  V_MC_tRRD(K_MC_tRRD_DEFAULT)
356 
357 #define S_MC_tRP		  16
358 #define M_MC_tRP		  _SB_MAKEMASK(4, S_MC_tRP)
359 #define V_MC_tRP(x)		  _SB_MAKEVALUE(x, S_MC_tRP)
360 #define G_MC_tRP(x)		  _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
361 #define K_MC_tRP_DEFAULT	  4
362 #define V_MC_tRP_DEFAULT	  V_MC_tRP(K_MC_tRP_DEFAULT)
363 
364 #define S_MC_tCwD		  8
365 #define M_MC_tCwD		  _SB_MAKEMASK(4, S_MC_tCwD)
366 #define V_MC_tCwD(x)		  _SB_MAKEVALUE(x, S_MC_tCwD)
367 #define G_MC_tCwD(x)		  _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
368 #define K_MC_tCwD_DEFAULT	  1
369 #define V_MC_tCwD_DEFAULT	  V_MC_tCwD(K_MC_tCwD_DEFAULT)
370 
371 #define M_tCrDh			  _SB_MAKEMASK1(7)
372 #define M_MC_tCrDh		  M_tCrDh
373 
374 #define S_MC_tCrD		  4
375 #define M_MC_tCrD		  _SB_MAKEMASK(3, S_MC_tCrD)
376 #define V_MC_tCrD(x)		  _SB_MAKEVALUE(x, S_MC_tCrD)
377 #define G_MC_tCrD(x)		  _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
378 #define K_MC_tCrD_DEFAULT	  2
379 #define V_MC_tCrD_DEFAULT	  V_MC_tCrD(K_MC_tCrD_DEFAULT)
380 
381 #define S_MC_tRCD		  0
382 #define M_MC_tRCD		  _SB_MAKEMASK(4, S_MC_tRCD)
383 #define V_MC_tRCD(x)		  _SB_MAKEVALUE(x, S_MC_tRCD)
384 #define G_MC_tRCD(x)		  _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
385 #define K_MC_tRCD_DEFAULT	  3
386 #define V_MC_tRCD_DEFAULT	  V_MC_tRCD(K_MC_tRCD_DEFAULT)
387 
388 #define V_MC_TIMING_DEFAULT	V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
389 				V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
390 				V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
391 				V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
392 				V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
393 				V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
394 				V_MC_tRP(K_MC_tRP_DEFAULT) | \
395 				V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
396 				V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
397 				V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
398 				M_MC_r2rIDLE_TWOCYCLES
399 
400 /*
401  * Errata says these are not the default
402  *				 M_MC_w2rIDLE_TWOCYCLES | \
403  *				 M_MC_r2wIDLE_TWOCYCLES | \
404  */
405 
406 
407 /*
408  * Chip Select Start Address Register (Table 6-17)
409  */
410 
411 #define S_MC_CS0_START		    0
412 #define M_MC_CS0_START		    _SB_MAKEMASK(16, S_MC_CS0_START)
413 #define V_MC_CS0_START(x)	    _SB_MAKEVALUE(x, S_MC_CS0_START)
414 #define G_MC_CS0_START(x)	    _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
415 
416 #define S_MC_CS1_START		    16
417 #define M_MC_CS1_START		    _SB_MAKEMASK(16, S_MC_CS1_START)
418 #define V_MC_CS1_START(x)	    _SB_MAKEVALUE(x, S_MC_CS1_START)
419 #define G_MC_CS1_START(x)	    _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
420 
421 #define S_MC_CS2_START		    32
422 #define M_MC_CS2_START		    _SB_MAKEMASK(16, S_MC_CS2_START)
423 #define V_MC_CS2_START(x)	    _SB_MAKEVALUE(x, S_MC_CS2_START)
424 #define G_MC_CS2_START(x)	    _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
425 
426 #define S_MC_CS3_START		    48
427 #define M_MC_CS3_START		    _SB_MAKEMASK(16, S_MC_CS3_START)
428 #define V_MC_CS3_START(x)	    _SB_MAKEVALUE(x, S_MC_CS3_START)
429 #define G_MC_CS3_START(x)	    _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
430 
431 /*
432  * Chip Select End Address Register (Table 6-18)
433  */
434 
435 #define S_MC_CS0_END		    0
436 #define M_MC_CS0_END		    _SB_MAKEMASK(16, S_MC_CS0_END)
437 #define V_MC_CS0_END(x)		    _SB_MAKEVALUE(x, S_MC_CS0_END)
438 #define G_MC_CS0_END(x)		    _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
439 
440 #define S_MC_CS1_END		    16
441 #define M_MC_CS1_END		    _SB_MAKEMASK(16, S_MC_CS1_END)
442 #define V_MC_CS1_END(x)		    _SB_MAKEVALUE(x, S_MC_CS1_END)
443 #define G_MC_CS1_END(x)		    _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
444 
445 #define S_MC_CS2_END		    32
446 #define M_MC_CS2_END		    _SB_MAKEMASK(16, S_MC_CS2_END)
447 #define V_MC_CS2_END(x)		    _SB_MAKEVALUE(x, S_MC_CS2_END)
448 #define G_MC_CS2_END(x)		    _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
449 
450 #define S_MC_CS3_END		    48
451 #define M_MC_CS3_END		    _SB_MAKEMASK(16, S_MC_CS3_END)
452 #define V_MC_CS3_END(x)		    _SB_MAKEVALUE(x, S_MC_CS3_END)
453 #define G_MC_CS3_END(x)		    _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
454 
455 /*
456  * Chip Select Interleave Register (Table 6-19)
457  */
458 
459 #define S_MC_INTLV_RESERVED	    0
460 #define M_MC_INTLV_RESERVED	    _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
461 
462 #define S_MC_INTERLEAVE		    7
463 #define M_MC_INTERLEAVE		    _SB_MAKEMASK(18, S_MC_INTERLEAVE)
464 #define V_MC_INTERLEAVE(x)	    _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
465 
466 #define S_MC_INTLV_MBZ		    25
467 #define M_MC_INTLV_MBZ		    _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
468 
469 /*
470  * Row Address Bits Register (Table 6-20)
471  */
472 
473 #define S_MC_RAS_RESERVED	    0
474 #define M_MC_RAS_RESERVED	    _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
475 
476 #define S_MC_RAS_SELECT		    12
477 #define M_MC_RAS_SELECT		    _SB_MAKEMASK(25, S_MC_RAS_SELECT)
478 #define V_MC_RAS_SELECT(x)	    _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
479 
480 #define S_MC_RAS_MBZ		    37
481 #define M_MC_RAS_MBZ		    _SB_MAKEMASK(27, S_MC_RAS_MBZ)
482 
483 
484 /*
485  * Column Address Bits Register (Table 6-21)
486  */
487 
488 #define S_MC_CAS_RESERVED	    0
489 #define M_MC_CAS_RESERVED	    _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
490 
491 #define S_MC_CAS_SELECT		    5
492 #define M_MC_CAS_SELECT		    _SB_MAKEMASK(18, S_MC_CAS_SELECT)
493 #define V_MC_CAS_SELECT(x)	    _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
494 
495 #define S_MC_CAS_MBZ		    23
496 #define M_MC_CAS_MBZ		    _SB_MAKEMASK(41, S_MC_CAS_MBZ)
497 
498 
499 /*
500  * Bank Address Address Bits Register (Table 6-22)
501  */
502 
503 #define S_MC_BA_RESERVED	    0
504 #define M_MC_BA_RESERVED	    _SB_MAKEMASK(5, S_MC_BA_RESERVED)
505 
506 #define S_MC_BA_SELECT		    5
507 #define M_MC_BA_SELECT		    _SB_MAKEMASK(20, S_MC_BA_SELECT)
508 #define V_MC_BA_SELECT(x)	    _SB_MAKEVALUE(x, S_MC_BA_SELECT)
509 
510 #define S_MC_BA_MBZ		    25
511 #define M_MC_BA_MBZ		    _SB_MAKEMASK(39, S_MC_BA_MBZ)
512 
513 /*
514  * Chip Select Attribute Register (Table 6-23)
515  */
516 
517 #define K_MC_CS_ATTR_CLOSED	    0
518 #define K_MC_CS_ATTR_CASCHECK	    1
519 #define K_MC_CS_ATTR_HINT	    2
520 #define K_MC_CS_ATTR_OPEN	    3
521 
522 #define S_MC_CS0_PAGE		    0
523 #define M_MC_CS0_PAGE		    _SB_MAKEMASK(2, S_MC_CS0_PAGE)
524 #define V_MC_CS0_PAGE(x)	    _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
525 #define G_MC_CS0_PAGE(x)	    _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
526 
527 #define S_MC_CS1_PAGE		    16
528 #define M_MC_CS1_PAGE		    _SB_MAKEMASK(2, S_MC_CS1_PAGE)
529 #define V_MC_CS1_PAGE(x)	    _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
530 #define G_MC_CS1_PAGE(x)	    _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
531 
532 #define S_MC_CS2_PAGE		    32
533 #define M_MC_CS2_PAGE		    _SB_MAKEMASK(2, S_MC_CS2_PAGE)
534 #define V_MC_CS2_PAGE(x)	    _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
535 #define G_MC_CS2_PAGE(x)	    _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
536 
537 #define S_MC_CS3_PAGE		    48
538 #define M_MC_CS3_PAGE		    _SB_MAKEMASK(2, S_MC_CS3_PAGE)
539 #define V_MC_CS3_PAGE(x)	    _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
540 #define G_MC_CS3_PAGE(x)	    _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
541 
542 /*
543  * ECC Test ECC Register (Table 6-25)
544  */
545 
546 #define S_MC_ECC_INVERT		    0
547 #define M_MC_ECC_INVERT		    _SB_MAKEMASK(8, S_MC_ECC_INVERT)
548 
549 
550 #endif
551