1 /*  *********************************************************************
2     *  SB1250 Board Support Package
3     *
4     *  DMA definitions				File: sb1250_dma.h
5     *
6     *  This module contains constants and macros useful for
7     *  programming the SB1250's DMA controllers, both the data mover
8     *  and the Ethernet DMA.
9     *
10     *  SB1250 specification level:  User's manual 10/21/02
11     *  BCM1280 specification level: User's manual 11/24/03
12     *
13     *********************************************************************
14     *
15     *  Copyright 2000,2001,2002,2003
16     *  Broadcom Corporation. All rights reserved.
17     *
18     *  This program is free software; you can redistribute it and/or
19     *  modify it under the terms of the GNU General Public License as
20     *  published by the Free Software Foundation; either version 2 of
21     *  the License, or (at your option) any later version.
22     *
23     *  This program is distributed in the hope that it will be useful,
24     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
25     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26     *  GNU General Public License for more details.
27     *
28     *  You should have received a copy of the GNU General Public License
29     *  along with this program; if not, write to the Free Software
30     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31     *  MA 02111-1307 USA
32     ********************************************************************* */
33 
34 
35 #ifndef _SB1250_DMA_H
36 #define _SB1250_DMA_H
37 
38 
39 #include <asm/sibyte/sb1250_defs.h>
40 
41 /*  *********************************************************************
42     *  DMA Registers
43     ********************************************************************* */
44 
45 /*
46  * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
47  * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
48  * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
49  * Registers: DMA_CONFIG0_SER_x_RX
50  * Registers: DMA_CONFIG0_SER_x_TX
51  */
52 
53 
54 #define M_DMA_DROP		    _SB_MAKEMASK1(0)
55 
56 #define M_DMA_CHAIN_SEL		    _SB_MAKEMASK1(1)
57 #define M_DMA_RESERVED1		    _SB_MAKEMASK1(2)
58 
59 #define S_DMA_DESC_TYPE		    _SB_MAKE64(1)
60 #define M_DMA_DESC_TYPE		    _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
61 #define V_DMA_DESC_TYPE(x)	    _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
62 #define G_DMA_DESC_TYPE(x)	    _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
63 
64 #define K_DMA_DESC_TYPE_RING_AL		0
65 #define K_DMA_DESC_TYPE_CHAIN_AL	1
66 
67 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
68 #define K_DMA_DESC_TYPE_RING_UAL_WI	2
69 #define K_DMA_DESC_TYPE_RING_UAL_RMW	3
70 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
71 
72 #define M_DMA_EOP_INT_EN	    _SB_MAKEMASK1(3)
73 #define M_DMA_HWM_INT_EN	    _SB_MAKEMASK1(4)
74 #define M_DMA_LWM_INT_EN	    _SB_MAKEMASK1(5)
75 #define M_DMA_TBX_EN		    _SB_MAKEMASK1(6)
76 #define M_DMA_TDX_EN		    _SB_MAKEMASK1(7)
77 
78 #define S_DMA_INT_PKTCNT	    _SB_MAKE64(8)
79 #define M_DMA_INT_PKTCNT	    _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
80 #define V_DMA_INT_PKTCNT(x)	    _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
81 #define G_DMA_INT_PKTCNT(x)	    _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
82 
83 #define S_DMA_RINGSZ		    _SB_MAKE64(16)
84 #define M_DMA_RINGSZ		    _SB_MAKEMASK(16, S_DMA_RINGSZ)
85 #define V_DMA_RINGSZ(x)		    _SB_MAKEVALUE(x, S_DMA_RINGSZ)
86 #define G_DMA_RINGSZ(x)		    _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
87 
88 #define S_DMA_HIGH_WATERMARK	    _SB_MAKE64(32)
89 #define M_DMA_HIGH_WATERMARK	    _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
90 #define V_DMA_HIGH_WATERMARK(x)	    _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
91 #define G_DMA_HIGH_WATERMARK(x)	    _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
92 
93 #define S_DMA_LOW_WATERMARK	    _SB_MAKE64(48)
94 #define M_DMA_LOW_WATERMARK	    _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
95 #define V_DMA_LOW_WATERMARK(x)	    _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
96 #define G_DMA_LOW_WATERMARK(x)	    _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
97 
98 /*
99  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
100  * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
101  * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
102  * Registers: DMA_CONFIG1_SER_x_RX
103  * Registers: DMA_CONFIG1_SER_x_TX
104  */
105 
106 #define M_DMA_HDR_CF_EN		    _SB_MAKEMASK1(0)
107 #define M_DMA_ASIC_XFR_EN	    _SB_MAKEMASK1(1)
108 #define M_DMA_PRE_ADDR_EN	    _SB_MAKEMASK1(2)
109 #define M_DMA_FLOW_CTL_EN	    _SB_MAKEMASK1(3)
110 #define M_DMA_NO_DSCR_UPDT	    _SB_MAKEMASK1(4)
111 #define M_DMA_L2CA		    _SB_MAKEMASK1(5)
112 
113 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
114 #define M_DMA_RX_XTRA_STATUS	    _SB_MAKEMASK1(6)
115 #define M_DMA_TX_CPU_PAUSE	    _SB_MAKEMASK1(6)
116 #define M_DMA_TX_FC_PAUSE_EN	    _SB_MAKEMASK1(7)
117 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
118 
119 #define M_DMA_MBZ1		    _SB_MAKEMASK(6, 15)
120 
121 #define S_DMA_HDR_SIZE		    _SB_MAKE64(21)
122 #define M_DMA_HDR_SIZE		    _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
123 #define V_DMA_HDR_SIZE(x)	    _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
124 #define G_DMA_HDR_SIZE(x)	    _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
125 
126 #define M_DMA_MBZ2		    _SB_MAKEMASK(5, 32)
127 
128 #define S_DMA_ASICXFR_SIZE	    _SB_MAKE64(37)
129 #define M_DMA_ASICXFR_SIZE	    _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
130 #define V_DMA_ASICXFR_SIZE(x)	    _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
131 #define G_DMA_ASICXFR_SIZE(x)	    _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
132 
133 #define S_DMA_INT_TIMEOUT	    _SB_MAKE64(48)
134 #define M_DMA_INT_TIMEOUT	    _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
135 #define V_DMA_INT_TIMEOUT(x)	    _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
136 #define G_DMA_INT_TIMEOUT(x)	    _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
137 
138 /*
139  * Ethernet and Serial DMA Descriptor base address (Table 7-6)
140  */
141 
142 #define M_DMA_DSCRBASE_MBZ	    _SB_MAKEMASK(4, 0)
143 
144 
145 /*
146  * ASIC Mode Base Address (Table 7-7)
147  */
148 
149 #define M_DMA_ASIC_BASE_MBZ	    _SB_MAKEMASK(20, 0)
150 
151 /*
152  * DMA Descriptor Count Registers (Table 7-8)
153  */
154 
155 /* No bitfields */
156 
157 
158 /*
159  * Current Descriptor Address Register (Table 7-11)
160  */
161 
162 #define S_DMA_CURDSCR_ADDR	    _SB_MAKE64(0)
163 #define M_DMA_CURDSCR_ADDR	    _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
164 #define S_DMA_CURDSCR_COUNT	    _SB_MAKE64(40)
165 #define M_DMA_CURDSCR_COUNT	    _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
166 
167 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
168 #define M_DMA_TX_CH_PAUSE_ON	    _SB_MAKEMASK1(56)
169 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
170 
171 /*
172  * Receive Packet Drop Registers
173  */
174 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
175 #define S_DMA_OODLOST_RX	   _SB_MAKE64(0)
176 #define M_DMA_OODLOST_RX	   _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
177 #define G_DMA_OODLOST_RX(x)	   _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
178 
179 #define S_DMA_EOP_COUNT_RX	   _SB_MAKE64(16)
180 #define M_DMA_EOP_COUNT_RX	   _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
181 #define G_DMA_EOP_COUNT_RX(x)	   _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
182 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
183 
184 /*  *********************************************************************
185     *  DMA Descriptors
186     ********************************************************************* */
187 
188 /*
189  * Descriptor doubleword "A"  (Table 7-12)
190  */
191 
192 #define S_DMA_DSCRA_OFFSET	    _SB_MAKE64(0)
193 #define M_DMA_DSCRA_OFFSET	    _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
194 #define V_DMA_DSCRA_OFFSET(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
195 #define G_DMA_DSCRA_OFFSET(x)	    _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
196 
197 /* Note: Don't shift the address over, just mask it with the mask below */
198 #define S_DMA_DSCRA_A_ADDR	    _SB_MAKE64(5)
199 #define M_DMA_DSCRA_A_ADDR	    _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
200 
201 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
202 
203 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
204 #define S_DMA_DSCRA_A_ADDR_UA	     _SB_MAKE64(0)
205 #define M_DMA_DSCRA_A_ADDR_UA	     _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
206 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
207 
208 #define S_DMA_DSCRA_A_SIZE	    _SB_MAKE64(40)
209 #define M_DMA_DSCRA_A_SIZE	    _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
210 #define V_DMA_DSCRA_A_SIZE(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
211 #define G_DMA_DSCRA_A_SIZE(x)	    _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
212 
213 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
214 #define S_DMA_DSCRA_DSCR_CNT	    _SB_MAKE64(40)
215 #define M_DMA_DSCRA_DSCR_CNT	    _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
216 #define G_DMA_DSCRA_DSCR_CNT(x)	    _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
217 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
218 
219 #define M_DMA_DSCRA_INTERRUPT	    _SB_MAKEMASK1(49)
220 #define M_DMA_DSCRA_OFFSETB	    _SB_MAKEMASK1(50)
221 
222 #define S_DMA_DSCRA_STATUS	    _SB_MAKE64(51)
223 #define M_DMA_DSCRA_STATUS	    _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
224 #define V_DMA_DSCRA_STATUS(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
225 #define G_DMA_DSCRA_STATUS(x)	    _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
226 
227 /*
228  * Descriptor doubleword "B"  (Table 7-13)
229  */
230 
231 
232 #define S_DMA_DSCRB_OPTIONS	    _SB_MAKE64(0)
233 #define M_DMA_DSCRB_OPTIONS	    _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
234 #define V_DMA_DSCRB_OPTIONS(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
235 #define G_DMA_DSCRB_OPTIONS(x)	    _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
236 
237 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238 #define S_DMA_DSCRB_A_SIZE	  _SB_MAKE64(8)
239 #define M_DMA_DSCRB_A_SIZE	  _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
240 #define V_DMA_DSCRB_A_SIZE(x)	  _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
241 #define G_DMA_DSCRB_A_SIZE(x)	  _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
242 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
243 
244 #define R_DMA_DSCRB_ADDR	    _SB_MAKE64(0x10)
245 
246 /* Note: Don't shift the address over, just mask it with the mask below */
247 #define S_DMA_DSCRB_B_ADDR	    _SB_MAKE64(5)
248 #define M_DMA_DSCRB_B_ADDR	    _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
249 
250 #define S_DMA_DSCRB_B_SIZE	    _SB_MAKE64(40)
251 #define M_DMA_DSCRB_B_SIZE	    _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
252 #define V_DMA_DSCRB_B_SIZE(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
253 #define G_DMA_DSCRB_B_SIZE(x)	    _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
254 
255 #define M_DMA_DSCRB_B_VALID	    _SB_MAKEMASK1(49)
256 
257 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
258 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
259 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
260 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
261 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
262 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
263 
264 #define S_DMA_DSCRB_PKT_SIZE	    _SB_MAKE64(50)
265 #define M_DMA_DSCRB_PKT_SIZE	    _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
266 #define V_DMA_DSCRB_PKT_SIZE(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
267 #define G_DMA_DSCRB_PKT_SIZE(x)	    _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
268 
269 /*
270  * from pass2 some bits in dscr_b are also used for rx status
271  */
272 #define S_DMA_DSCRB_STATUS	    _SB_MAKE64(0)
273 #define M_DMA_DSCRB_STATUS	    _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
274 #define V_DMA_DSCRB_STATUS(x)	    _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
275 #define G_DMA_DSCRB_STATUS(x)	    _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
276 
277 /*
278  * Ethernet Descriptor Status Bits (Table 7-15)
279  */
280 
281 #define M_DMA_ETHRX_BADIP4CS	    _SB_MAKEMASK1(51)
282 #define M_DMA_ETHRX_DSCRERR	    _SB_MAKEMASK1(52)
283 
284 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
285 /* Note: This bit is in the DSCR_B options field */
286 #define M_DMA_ETHRX_BADTCPCS	_SB_MAKEMASK1(0)
287 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
288 
289 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
290 /* Note: These bits are in the DSCR_B options field */
291 #define M_DMA_ETH_VLAN_FLAG	_SB_MAKEMASK1(1)
292 #define M_DMA_ETH_CRC_FLAG	_SB_MAKEMASK1(2)
293 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 
295 #define S_DMA_ETHRX_RXCH	    53
296 #define M_DMA_ETHRX_RXCH	    _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
297 #define V_DMA_ETHRX_RXCH(x)	    _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
298 #define G_DMA_ETHRX_RXCH(x)	    _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
299 
300 #define S_DMA_ETHRX_PKTTYPE	    55
301 #define M_DMA_ETHRX_PKTTYPE	    _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
302 #define V_DMA_ETHRX_PKTTYPE(x)	    _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
303 #define G_DMA_ETHRX_PKTTYPE(x)	    _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
304 
305 #define K_DMA_ETHRX_PKTTYPE_IPV4    0
306 #define K_DMA_ETHRX_PKTTYPE_ARPV4   1
307 #define K_DMA_ETHRX_PKTTYPE_802	    2
308 #define K_DMA_ETHRX_PKTTYPE_OTHER   3
309 #define K_DMA_ETHRX_PKTTYPE_USER0   4
310 #define K_DMA_ETHRX_PKTTYPE_USER1   5
311 #define K_DMA_ETHRX_PKTTYPE_USER2   6
312 #define K_DMA_ETHRX_PKTTYPE_USER3   7
313 
314 #define M_DMA_ETHRX_MATCH_HASH	    _SB_MAKEMASK1(58)
315 #define M_DMA_ETHRX_MATCH_EXACT	    _SB_MAKEMASK1(59)
316 #define M_DMA_ETHRX_BCAST	    _SB_MAKEMASK1(60)
317 #define M_DMA_ETHRX_MCAST	    _SB_MAKEMASK1(61)
318 #define M_DMA_ETHRX_BAD		    _SB_MAKEMASK1(62)
319 #define M_DMA_ETHRX_SOP		    _SB_MAKEMASK1(63)
320 
321 /*
322  * Ethernet Transmit Status Bits (Table 7-16)
323  */
324 
325 #define M_DMA_ETHTX_SOP		    _SB_MAKEMASK1(63)
326 
327 /*
328  * Ethernet Transmit Options (Table 7-17)
329  */
330 
331 #define K_DMA_ETHTX_NOTSOP	    _SB_MAKE64(0x00)
332 #define K_DMA_ETHTX_APPENDCRC	    _SB_MAKE64(0x01)
333 #define K_DMA_ETHTX_REPLACECRC	    _SB_MAKE64(0x02)
334 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
335 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
336 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
337 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
338 #define K_DMA_ETHTX_NOMODS	    _SB_MAKE64(0x07)
339 #define K_DMA_ETHTX_RESERVED1	    _SB_MAKE64(0x08)
340 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
341 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
342 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
343 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
344 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
345 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
346 #define K_DMA_ETHTX_RESERVED2	    _SB_MAKE64(0x0F)
347 
348 /*
349  * Serial Receive Options (Table 7-18)
350  */
351 #define M_DMA_SERRX_CRC_ERROR	    _SB_MAKEMASK1(56)
352 #define M_DMA_SERRX_ABORT	    _SB_MAKEMASK1(57)
353 #define M_DMA_SERRX_OCTET_ERROR	    _SB_MAKEMASK1(58)
354 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
355 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
356 #define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
357 #define M_DMA_SERRX_GOOD	    _SB_MAKEMASK1(62)
358 #define M_DMA_SERRX_SOP		    _SB_MAKEMASK1(63)
359 
360 /*
361  * Serial Transmit Status Bits (Table 7-20)
362  */
363 
364 #define M_DMA_SERTX_FLAG	    _SB_MAKEMASK1(63)
365 
366 /*
367  * Serial Transmit Options (Table 7-21)
368  */
369 
370 #define K_DMA_SERTX_RESERVED	    _SB_MAKEMASK1(0)
371 #define K_DMA_SERTX_APPENDCRC	    _SB_MAKEMASK1(1)
372 #define K_DMA_SERTX_APPENDPAD	    _SB_MAKEMASK1(2)
373 #define K_DMA_SERTX_ABORT	    _SB_MAKEMASK1(3)
374 
375 
376 /*  *********************************************************************
377     *  Data Mover Registers
378     ********************************************************************* */
379 
380 /*
381  * Data Mover Descriptor Base Address Register (Table 7-22)
382  * Register: DM_DSCR_BASE_0
383  * Register: DM_DSCR_BASE_1
384  * Register: DM_DSCR_BASE_2
385  * Register: DM_DSCR_BASE_3
386  */
387 
388 #define M_DM_DSCR_BASE_MBZ	    _SB_MAKEMASK(4, 0)
389 
390 /*  Note: Just mask the base address and then OR it in. */
391 #define S_DM_DSCR_BASE_ADDR	    _SB_MAKE64(4)
392 #define M_DM_DSCR_BASE_ADDR	    _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
393 
394 #define S_DM_DSCR_BASE_RINGSZ	    _SB_MAKE64(40)
395 #define M_DM_DSCR_BASE_RINGSZ	    _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
396 #define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
397 #define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
398 
399 #define S_DM_DSCR_BASE_PRIORITY	    _SB_MAKE64(56)
400 #define M_DM_DSCR_BASE_PRIORITY	    _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
401 #define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
402 #define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
403 
404 #define K_DM_DSCR_BASE_PRIORITY_1   0
405 #define K_DM_DSCR_BASE_PRIORITY_2   1
406 #define K_DM_DSCR_BASE_PRIORITY_4   2
407 #define K_DM_DSCR_BASE_PRIORITY_8   3
408 #define K_DM_DSCR_BASE_PRIORITY_16  4
409 
410 #define M_DM_DSCR_BASE_ACTIVE	    _SB_MAKEMASK1(59)
411 #define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
412 #define M_DM_DSCR_BASE_RESET	    _SB_MAKEMASK1(61)	/* write register */
413 #define M_DM_DSCR_BASE_ERROR	    _SB_MAKEMASK1(61)	/* read register */
414 #define M_DM_DSCR_BASE_ABORT	    _SB_MAKEMASK1(62)
415 #define M_DM_DSCR_BASE_ENABL	    _SB_MAKEMASK1(63)
416 
417 /*
418  * Data Mover Descriptor Count Register (Table 7-25)
419  */
420 
421 /* no bitfields */
422 
423 /*
424  * Data Mover Current Descriptor Address (Table 7-24)
425  * Register: DM_CUR_DSCR_ADDR_0
426  * Register: DM_CUR_DSCR_ADDR_1
427  * Register: DM_CUR_DSCR_ADDR_2
428  * Register: DM_CUR_DSCR_ADDR_3
429  */
430 
431 #define S_DM_CUR_DSCR_DSCR_ADDR	    _SB_MAKE64(0)
432 #define M_DM_CUR_DSCR_DSCR_ADDR	    _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
433 
434 #define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
435 #define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
436 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
437 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
438 				     M_DM_CUR_DSCR_DSCR_COUNT)
439 
440 
441 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
442 /*
443  * Data Mover Channel Partial Result Registers
444  * Register: DM_PARTIAL_0
445  * Register: DM_PARTIAL_1
446  * Register: DM_PARTIAL_2
447  * Register: DM_PARTIAL_3
448  */
449 #define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
450 #define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
451 #define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
452 #define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
453 				       M_DM_PARTIAL_CRC_PARTIAL)
454 
455 #define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
456 #define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
457 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
458 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
459 				       M_DM_PARTIAL_TCPCS_PARTIAL)
460 
461 #define M_DM_PARTIAL_ODD_BYTE	      _SB_MAKEMASK1(48)
462 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
463 
464 
465 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466 /*
467  * Data Mover CRC Definition Registers
468  * Register: CRC_DEF_0
469  * Register: CRC_DEF_1
470  */
471 #define S_CRC_DEF_CRC_INIT	      _SB_MAKE64(0)
472 #define M_CRC_DEF_CRC_INIT	      _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
473 #define V_CRC_DEF_CRC_INIT(r)	      _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
474 #define G_CRC_DEF_CRC_INIT(r)	      _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
475 				       M_CRC_DEF_CRC_INIT)
476 
477 #define S_CRC_DEF_CRC_POLY	      _SB_MAKE64(32)
478 #define M_CRC_DEF_CRC_POLY	      _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
479 #define V_CRC_DEF_CRC_POLY(r)	      _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
480 #define G_CRC_DEF_CRC_POLY(r)	      _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
481 				       M_CRC_DEF_CRC_POLY)
482 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 
484 
485 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
486 /*
487  * Data Mover CRC/Checksum Definition Registers
488  * Register: CTCP_DEF_0
489  * Register: CTCP_DEF_1
490  */
491 #define S_CTCP_DEF_CRC_TXOR	      _SB_MAKE64(0)
492 #define M_CTCP_DEF_CRC_TXOR	      _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
493 #define V_CTCP_DEF_CRC_TXOR(r)	      _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
494 #define G_CTCP_DEF_CRC_TXOR(r)	      _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
495 				       M_CTCP_DEF_CRC_TXOR)
496 
497 #define S_CTCP_DEF_TCPCS_INIT	      _SB_MAKE64(32)
498 #define M_CTCP_DEF_TCPCS_INIT	      _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
499 #define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
500 #define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
501 				       M_CTCP_DEF_TCPCS_INIT)
502 
503 #define S_CTCP_DEF_CRC_WIDTH	      _SB_MAKE64(48)
504 #define M_CTCP_DEF_CRC_WIDTH	      _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
505 #define V_CTCP_DEF_CRC_WIDTH(r)	      _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
506 #define G_CTCP_DEF_CRC_WIDTH(r)	      _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
507 				       M_CTCP_DEF_CRC_WIDTH)
508 
509 #define K_CTCP_DEF_CRC_WIDTH_4	      0
510 #define K_CTCP_DEF_CRC_WIDTH_2	      1
511 #define K_CTCP_DEF_CRC_WIDTH_1	      2
512 
513 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
514 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
515 
516 
517 /*
518  * Data Mover Descriptor Doubleword "A"	 (Table 7-26)
519  */
520 
521 #define S_DM_DSCRA_DST_ADDR	    _SB_MAKE64(0)
522 #define M_DM_DSCRA_DST_ADDR	    _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
523 
524 #define M_DM_DSCRA_UN_DEST	    _SB_MAKEMASK1(40)
525 #define M_DM_DSCRA_UN_SRC	    _SB_MAKEMASK1(41)
526 #define M_DM_DSCRA_INTERRUPT	    _SB_MAKEMASK1(42)
527 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
528 #define M_DM_DSCRA_THROTTLE	    _SB_MAKEMASK1(43)
529 #endif /* up to 1250 PASS1 */
530 
531 #define S_DM_DSCRA_DIR_DEST	    _SB_MAKE64(44)
532 #define M_DM_DSCRA_DIR_DEST	    _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
533 #define V_DM_DSCRA_DIR_DEST(x)	    _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
534 #define G_DM_DSCRA_DIR_DEST(x)	    _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
535 
536 #define K_DM_DSCRA_DIR_DEST_INCR    0
537 #define K_DM_DSCRA_DIR_DEST_DECR    1
538 #define K_DM_DSCRA_DIR_DEST_CONST   2
539 
540 #define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
541 #define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
542 #define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
543 
544 #define S_DM_DSCRA_DIR_SRC	    _SB_MAKE64(46)
545 #define M_DM_DSCRA_DIR_SRC	    _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
546 #define V_DM_DSCRA_DIR_SRC(x)	    _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
547 #define G_DM_DSCRA_DIR_SRC(x)	    _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
548 
549 #define K_DM_DSCRA_DIR_SRC_INCR	    0
550 #define K_DM_DSCRA_DIR_SRC_DECR	    1
551 #define K_DM_DSCRA_DIR_SRC_CONST    2
552 
553 #define V_DM_DSCRA_DIR_SRC_INCR	    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
554 #define V_DM_DSCRA_DIR_SRC_DECR	    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
555 #define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
556 
557 
558 #define M_DM_DSCRA_ZERO_MEM	    _SB_MAKEMASK1(48)
559 #define M_DM_DSCRA_PREFETCH	    _SB_MAKEMASK1(49)
560 #define M_DM_DSCRA_L2C_DEST	    _SB_MAKEMASK1(50)
561 #define M_DM_DSCRA_L2C_SRC	    _SB_MAKEMASK1(51)
562 
563 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
564 #define M_DM_DSCRA_RD_BKOFF	    _SB_MAKEMASK1(52)
565 #define M_DM_DSCRA_WR_BKOFF	    _SB_MAKEMASK1(53)
566 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
567 
568 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
569 #define M_DM_DSCRA_TCPCS_EN	    _SB_MAKEMASK1(54)
570 #define M_DM_DSCRA_TCPCS_RES	    _SB_MAKEMASK1(55)
571 #define M_DM_DSCRA_TCPCS_AP	    _SB_MAKEMASK1(56)
572 #define M_DM_DSCRA_CRC_EN	    _SB_MAKEMASK1(57)
573 #define M_DM_DSCRA_CRC_RES	    _SB_MAKEMASK1(58)
574 #define M_DM_DSCRA_CRC_AP	    _SB_MAKEMASK1(59)
575 #define M_DM_DSCRA_CRC_DFN	    _SB_MAKEMASK1(60)
576 #define M_DM_DSCRA_CRC_XBIT	    _SB_MAKEMASK1(61)
577 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 
579 #define M_DM_DSCRA_RESERVED2	    _SB_MAKEMASK(3, 61)
580 
581 /*
582  * Data Mover Descriptor Doubleword "B"	 (Table 7-25)
583  */
584 
585 #define S_DM_DSCRB_SRC_ADDR	    _SB_MAKE64(0)
586 #define M_DM_DSCRB_SRC_ADDR	    _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
587 
588 #define S_DM_DSCRB_SRC_LENGTH	    _SB_MAKE64(40)
589 #define M_DM_DSCRB_SRC_LENGTH	    _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
590 #define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
591 #define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
592 
593 
594 #endif
595