1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * ip22.h: Definitions for SGI IP22 machines 7 * 8 * Copyright (C) 1996 David S. Miller 9 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle 10 */ 11 12 #ifndef _SGI_IP22_H 13 #define _SGI_IP22_H 14 15 /* 16 * These are the virtual IRQ numbers, we divide all IRQ's into 17 * 'spaces', the 'space' determines where and how to enable/disable 18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts 19 * are not supported this way. Driver is supposed to allocate HPC/MC 20 * interrupt as shareable and then look to proper status bit (see 21 * HAL2 driver). This will prevent many complications, trust me ;-) 22 */ 23 24 #include <irq.h> 25 #include <asm/sgi/ioc.h> 26 27 #define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ 28 #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */ 29 #define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */ 30 #define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */ 31 #define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */ 32 #define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */ 33 #define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */ 34 35 /* 36 * Individual interrupt definitions for the Indy and Indigo2 37 */ 38 39 #define SGI_SOFT_0_IRQ SGINT_CPU + 0 40 #define SGI_SOFT_1_IRQ SGINT_CPU + 1 41 #define SGI_LOCAL_0_IRQ SGINT_CPU + 2 42 #define SGI_LOCAL_1_IRQ SGINT_CPU + 3 43 #define SGI_8254_0_IRQ SGINT_CPU + 4 44 #define SGI_8254_1_IRQ SGINT_CPU + 5 45 #define SGI_BUSERR_IRQ SGINT_CPU + 6 46 #define SGI_TIMER_IRQ SGINT_CPU + 7 47 48 #define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */ 49 #define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */ 50 #define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ 51 #define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ 52 #define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ 53 #define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ 54 #define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ 55 #define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ 56 #define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ 57 58 #define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */ 59 #define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ 60 #define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */ 61 #define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */ 62 #define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */ 63 #define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */ 64 #define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ 65 #define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */ 66 67 /* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */ 68 #define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */ 69 #define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ 70 #define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ 71 #define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ 72 #define SGI_GIOEXP0_IRQ (SGINT_LOCAL2 + 6) /* Indy GIO EXP0 */ 73 #define SGI_GIOEXP1_IRQ (SGINT_LOCAL2 + 7) /* Indy GIO EXP1 */ 74 75 #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) 76 77 extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg); 78 extern unsigned short ip22_nvram_read(int reg); 79 80 #endif 81