1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_PROCESSOR_H 12 #define _ASM_PROCESSOR_H 13 14 #include <linux/atomic.h> 15 #include <linux/cpumask.h> 16 #include <linux/sizes.h> 17 #include <linux/threads.h> 18 19 #include <asm/cachectl.h> 20 #include <asm/cpu.h> 21 #include <asm/cpu-info.h> 22 #include <asm/dsemul.h> 23 #include <asm/mipsregs.h> 24 #include <asm/prefetch.h> 25 26 /* 27 * System setup and hardware flags.. 28 */ 29 30 extern unsigned int vced_count, vcei_count; 31 32 /* 33 * MIPS does have an arch_pick_mmap_layout() 34 */ 35 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 36 37 #ifdef CONFIG_32BIT 38 #ifdef CONFIG_KVM_GUEST 39 /* User space process size is limited to 1GB in KVM Guest Mode */ 40 #define TASK_SIZE 0x3fff8000UL 41 #else 42 /* 43 * User space process size: 2GB. This is hardcoded into a few places, 44 * so don't change it unless you know what you are doing. 45 */ 46 #define TASK_SIZE 0x80000000UL 47 #endif 48 49 #define STACK_TOP_MAX TASK_SIZE 50 51 #define TASK_IS_32BIT_ADDR 1 52 53 #endif 54 55 #ifdef CONFIG_64BIT 56 /* 57 * User space process size: 1TB. This is hardcoded into a few places, 58 * so don't change it unless you know what you are doing. TASK_SIZE 59 * is limited to 1TB by the R4000 architecture; R10000 and better can 60 * support 16TB; the architectural reserve for future expansion is 61 * 8192EB ... 62 */ 63 #define TASK_SIZE32 0x7fff8000UL 64 #ifdef CONFIG_MIPS_VA_BITS_48 65 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits)) 66 #else 67 #define TASK_SIZE64 0x10000000000UL 68 #endif 69 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 70 #define STACK_TOP_MAX TASK_SIZE64 71 72 #define TASK_SIZE_OF(tsk) \ 73 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 74 75 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 76 77 #endif 78 79 #define VDSO_RANDOMIZE_SIZE (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M) 80 81 extern unsigned long mips_stack_top(void); 82 #define STACK_TOP mips_stack_top() 83 84 /* 85 * This decides where the kernel will search for a free chunk of vm 86 * space during mmap's. 87 */ 88 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 89 90 91 #define NUM_FPU_REGS 32 92 93 #ifdef CONFIG_CPU_HAS_MSA 94 # define FPU_REG_WIDTH 128 95 #else 96 # define FPU_REG_WIDTH 64 97 #endif 98 99 union fpureg { 100 __u32 val32[FPU_REG_WIDTH / 32]; 101 __u64 val64[FPU_REG_WIDTH / 64]; 102 }; 103 104 #ifdef CONFIG_CPU_LITTLE_ENDIAN 105 # define FPR_IDX(width, idx) (idx) 106 #else 107 # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1)) 108 #endif 109 110 #define BUILD_FPR_ACCESS(width) \ 111 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ 112 { \ 113 return fpr->val##width[FPR_IDX(width, idx)]; \ 114 } \ 115 \ 116 static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \ 117 u##width val) \ 118 { \ 119 fpr->val##width[FPR_IDX(width, idx)] = val; \ 120 } 121 122 BUILD_FPR_ACCESS(32) 123 BUILD_FPR_ACCESS(64) 124 125 /* 126 * It would be nice to add some more fields for emulator statistics, 127 * the additional information is private to the FPU emulator for now. 128 * See arch/mips/include/asm/fpu_emulator.h. 129 */ 130 131 struct mips_fpu_struct { 132 union fpureg fpr[NUM_FPU_REGS]; 133 unsigned int fcr31; 134 unsigned int msacsr; 135 }; 136 137 #define NUM_DSP_REGS 6 138 139 typedef unsigned long dspreg_t; 140 141 struct mips_dsp_state { 142 dspreg_t dspr[NUM_DSP_REGS]; 143 unsigned int dspcontrol; 144 }; 145 146 #define INIT_CPUMASK { \ 147 {0,} \ 148 } 149 150 struct mips3264_watch_reg_state { 151 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a 152 64 bit kernel. We use unsigned long as it has the same 153 property. */ 154 unsigned long watchlo[NUM_WATCH_REGS]; 155 /* Only the mask and IRW bits from watchhi. */ 156 u16 watchhi[NUM_WATCH_REGS]; 157 }; 158 159 union mips_watch_reg_state { 160 struct mips3264_watch_reg_state mips3264; 161 }; 162 163 #if defined(CONFIG_CPU_CAVIUM_OCTEON) 164 165 struct octeon_cop2_state { 166 /* DMFC2 rt, 0x0201 */ 167 unsigned long cop2_crc_iv; 168 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ 169 unsigned long cop2_crc_length; 170 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ 171 unsigned long cop2_crc_poly; 172 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ 173 unsigned long cop2_llm_dat[2]; 174 /* DMFC2 rt, 0x0084 */ 175 unsigned long cop2_3des_iv; 176 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ 177 unsigned long cop2_3des_key[3]; 178 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ 179 unsigned long cop2_3des_result; 180 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ 181 unsigned long cop2_aes_inp0; 182 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ 183 unsigned long cop2_aes_iv[2]; 184 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 185 * rt, 0x0107 */ 186 unsigned long cop2_aes_key[4]; 187 /* DMFC2 rt, 0x0110 */ 188 unsigned long cop2_aes_keylen; 189 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ 190 unsigned long cop2_aes_result[2]; 191 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 192 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, 193 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, 194 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, 195 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ 196 unsigned long cop2_hsh_datw[15]; 197 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 198 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, 199 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ 200 unsigned long cop2_hsh_ivw[8]; 201 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ 202 unsigned long cop2_gfm_mult[2]; 203 /* DMFC2 rt, 0x025E - Pass2 */ 204 unsigned long cop2_gfm_poly; 205 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 206 unsigned long cop2_gfm_result[2]; 207 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */ 208 unsigned long cop2_sha3[2]; 209 }; 210 #define COP2_INIT \ 211 .cp2 = {0,}, 212 213 struct octeon_cvmseg_state { 214 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 215 [cpu_dcache_line_size() / sizeof(unsigned long)]; 216 }; 217 218 #elif defined(CONFIG_CPU_XLP) 219 struct nlm_cop2_state { 220 u64 rx[4]; 221 u64 tx[4]; 222 u32 tx_msg_status; 223 u32 rx_msg_status; 224 }; 225 226 #define COP2_INIT \ 227 .cp2 = {{0}, {0}, 0, 0}, 228 #else 229 #define COP2_INIT 230 #endif 231 232 typedef struct { 233 unsigned long seg; 234 } mm_segment_t; 235 236 #ifdef CONFIG_CPU_HAS_MSA 237 # define ARCH_MIN_TASKALIGN 16 238 # define FPU_ALIGN __aligned(16) 239 #else 240 # define ARCH_MIN_TASKALIGN 8 241 # define FPU_ALIGN 242 #endif 243 244 struct mips_abi; 245 246 /* 247 * If you change thread_struct remember to change the #defines below too! 248 */ 249 struct thread_struct { 250 /* Saved main processor registers. */ 251 unsigned long reg16; 252 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; 253 unsigned long reg29, reg30, reg31; 254 255 /* Saved cp0 stuff. */ 256 unsigned long cp0_status; 257 258 #ifdef CONFIG_MIPS_FP_SUPPORT 259 /* Saved fpu/fpu emulator stuff. */ 260 struct mips_fpu_struct fpu FPU_ALIGN; 261 #endif 262 /* Assigned branch delay slot 'emulation' frame */ 263 atomic_t bd_emu_frame; 264 /* PC of the branch from a branch delay slot 'emulation' */ 265 unsigned long bd_emu_branch_pc; 266 /* PC to continue from following a branch delay slot 'emulation' */ 267 unsigned long bd_emu_cont_pc; 268 #ifdef CONFIG_MIPS_MT_FPAFF 269 /* Emulated instruction count */ 270 unsigned long emulated_fp; 271 /* Saved per-thread scheduler affinity mask */ 272 cpumask_t user_cpus_allowed; 273 #endif /* CONFIG_MIPS_MT_FPAFF */ 274 275 /* Saved state of the DSP ASE, if available. */ 276 struct mips_dsp_state dsp; 277 278 /* Saved watch register state, if available. */ 279 union mips_watch_reg_state watch; 280 281 /* Other stuff associated with the thread. */ 282 unsigned long cp0_badvaddr; /* Last user fault */ 283 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 284 unsigned long error_code; 285 unsigned long trap_nr; 286 #ifdef CONFIG_CPU_CAVIUM_OCTEON 287 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 288 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 289 #endif 290 #ifdef CONFIG_CPU_XLP 291 struct nlm_cop2_state cp2; 292 #endif 293 struct mips_abi *abi; 294 }; 295 296 #ifdef CONFIG_MIPS_MT_FPAFF 297 #define FPAFF_INIT \ 298 .emulated_fp = 0, \ 299 .user_cpus_allowed = INIT_CPUMASK, 300 #else 301 #define FPAFF_INIT 302 #endif /* CONFIG_MIPS_MT_FPAFF */ 303 304 #ifdef CONFIG_MIPS_FP_SUPPORT 305 # define FPU_INIT \ 306 .fpu = { \ 307 .fpr = {{{0,},},}, \ 308 .fcr31 = 0, \ 309 .msacsr = 0, \ 310 }, 311 #else 312 # define FPU_INIT 313 #endif 314 315 #define INIT_THREAD { \ 316 /* \ 317 * Saved main processor registers \ 318 */ \ 319 .reg16 = 0, \ 320 .reg17 = 0, \ 321 .reg18 = 0, \ 322 .reg19 = 0, \ 323 .reg20 = 0, \ 324 .reg21 = 0, \ 325 .reg22 = 0, \ 326 .reg23 = 0, \ 327 .reg29 = 0, \ 328 .reg30 = 0, \ 329 .reg31 = 0, \ 330 /* \ 331 * Saved cp0 stuff \ 332 */ \ 333 .cp0_status = 0, \ 334 /* \ 335 * Saved FPU/FPU emulator stuff \ 336 */ \ 337 FPU_INIT \ 338 /* \ 339 * FPU affinity state (null if not FPAFF) \ 340 */ \ 341 FPAFF_INIT \ 342 /* Delay slot emulation */ \ 343 .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ 344 .bd_emu_branch_pc = 0, \ 345 .bd_emu_cont_pc = 0, \ 346 /* \ 347 * Saved DSP stuff \ 348 */ \ 349 .dsp = { \ 350 .dspr = {0, }, \ 351 .dspcontrol = 0, \ 352 }, \ 353 /* \ 354 * saved watch register stuff \ 355 */ \ 356 .watch = {{{0,},},}, \ 357 /* \ 358 * Other stuff associated with the process \ 359 */ \ 360 .cp0_badvaddr = 0, \ 361 .cp0_baduaddr = 0, \ 362 .error_code = 0, \ 363 .trap_nr = 0, \ 364 /* \ 365 * Platform specific cop2 registers(null if no COP2) \ 366 */ \ 367 COP2_INIT \ 368 } 369 370 struct task_struct; 371 372 /* Free all resources held by a thread. */ 373 #define release_thread(thread) do { } while(0) 374 375 /* 376 * Do necessary setup to start up a newly executed thread. 377 */ 378 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); 379 380 static inline void flush_thread(void) 381 { 382 } 383 384 unsigned long get_wchan(struct task_struct *p); 385 386 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 387 THREAD_SIZE - 32 - sizeof(struct pt_regs)) 388 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 389 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 390 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 391 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) 392 393 #ifdef CONFIG_CPU_LOONGSON3 394 /* 395 * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a 396 * tight read loop is executed, because reads take priority over writes & the 397 * hardware (incorrectly) doesn't ensure that writes will eventually occur. 398 * 399 * Since spin loops of any kind should have a cpu_relax() in them, force an SFB 400 * flush from cpu_relax() such that any pending writes will become visible as 401 * expected. 402 */ 403 #define cpu_relax() smp_mb() 404 #else 405 #define cpu_relax() barrier() 406 #endif 407 408 /* 409 * Return_address is a replacement for __builtin_return_address(count) 410 * which on certain architectures cannot reasonably be implemented in GCC 411 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). 412 * Note that __builtin_return_address(x>=1) is forbidden because GCC 413 * aborts compilation on some CPUs. It's simply not possible to unwind 414 * some CPU's stackframes. 415 * 416 * __builtin_return_address works only for non-leaf functions. We avoid the 417 * overhead of a function call by forcing the compiler to save the return 418 * address register on the stack. 419 */ 420 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) 421 422 #ifdef CONFIG_CPU_HAS_PREFETCH 423 424 #define ARCH_HAS_PREFETCH 425 #define prefetch(x) __builtin_prefetch((x), 0, 1) 426 427 #define ARCH_HAS_PREFETCHW 428 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 429 430 #endif 431 432 /* 433 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options 434 * to the prctl syscall. 435 */ 436 extern int mips_get_process_fp_mode(struct task_struct *task); 437 extern int mips_set_process_fp_mode(struct task_struct *task, 438 unsigned int value); 439 440 #define GET_FP_MODE(task) mips_get_process_fp_mode(task) 441 #define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value) 442 443 #endif /* _ASM_PROCESSOR_H */ 444